Ageing of Integrated Circuits: Causes, Effects and Mitigation Techniques [1st ed. 2020] 978-3-030-23780-6, 978-3-030-23781-3

Table of contents :
Front Matter ....Pages i-xiii
Front Matter ....Pages 1-1
Understanding Ageing Mechanisms (Domenik Helms)....Pages 3-34
The Effects of Ageing on the Reliability and Performance of Integrated Circuits (Daniele Rossi)....Pages 35-64
Front Matter ....Pages 65-65
Aging Mitigation Techniques for Microprocessors Using Anti-aging Software (Haider Muhi Abbas, Mark Zwolinski, Basel Halak)....Pages 67-89
Ageing Mitigation Techniques for SRAM Memories (Mohd Syafiq Mispan, Mark Zwolinski, Basel Halak)....Pages 91-111
Ageing-Aware Logic Synthesis (Shengyu Duan, Mark Zwolinski, Basel Halak)....Pages 113-145
Front Matter ....Pages 147-147
On-Chip Ageing Monitoring and System Adaptation (Lorena Anghel, Florian Cacho, Riddhi Jitendrakumar Shah)....Pages 149-180
Aging Monitors for SRAM Memory Cells and Sense Amplifiers (Helen-Maria Dounavi, Yiorgos Sfikas, Yiorgos Tsiatouhas)....Pages 181-210
A Cost-Efficient Aging Sensor Based on Multiple Paths Delay Fault Monitoring (Gaole Sai, Mark Zwolinski, Basel Halak)....Pages 211-223
Back Matter ....Pages 225-228

Citation preview

Basel Halak Editor

Ageing of Integrated Circuits Causes, Effects and Mitigation Techniques

Ageing of Integrated Circuits

Basel Halak Editor

Ageing of Integrated Circuits Causes, Effects and Mitigation Techniques

123

Editor Basel Halak The School of Electronics and Computer Science University of Southampton Southampton, UK

ISBN 978-3-030-23780-6 ISBN 978-3-030-23781-3 (eBook) https://doi.org/10.1007/978-3-030-23781-3 © Springer Nature Switzerland AG 2020 This work is subject to copyright. All rights are reserved by the Publisher, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed. The use of general descriptive names, registered names, trademarks, service marks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use. The publisher, the authors, and the editors are safe to assume that the advice and information in this book are believed to be true and accurate at the date of publication. Neither the publisher nor the authors or the editors give a warranty, express or implied, with respect to the material contained herein or for any errors or omissions that may have been made. The publisher remains neutral with regard to jurisdictional claims in published maps and institutional affiliations. This Springer imprint is published by the registered company Springer Nature Switzerland AG. The registered company address is: Gewerbestrasse 11, 6330 Cham, Switzerland

To my parents as well as Suzanne, Hanin, and Sophia with love

Preface

The ageing of an organism in biology is defined as a progressive, irreversible process that inevitably ends with death. The maximal lifetime of an individual is significantly affected by ageing. The same is true for integrated circuits wherein ageing can be caused by several physical mechanisms, including bias temperature instability (BTI), hot carrier injection (HCI), and time-dependent dielectric breakdown (TDDB). Ageing effects lead to a degradation in the performance and reliability of an electronic system, hence limiting its expected lifetime. Variation-aware design techniques, such as conservative safety margins, can be used to reduce the impact of ageing on system reliability; however, the applications of such methods make it harder to develop competitive products and may lead to the elimination of performance gains of technology scaling. Therefore, there is a need for innovative approaches to improve the resilience of integrated circuit to ageinginduced failure without affecting its performance. The prime objective of this book is to provide a timely and coherent account of the latest advances in the key research areas of IC’s ageing; it has been developed as a collaborative effort among several international research groups, each providing an up-to-date summary of their latest findings and highlighting the remaining challenges and research opportunities. To facilitate the understanding of the material, each chapter includes a background section explaining related terminologies and principles, in addition to a comprehensive list of relevant references. The book is divided into three parts to enhance its readability, namely, physical mechanisms, mitigation techniques, and monitoring and adaptation approaches.

The Contents at Glance This book explains the physical mechanism causing the ageing of integrated circuits, including a comprehensive analysis of its effects on the performance and reliability of integrated circuits. Afterwards, the book presents a number of mitigation vii

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techniques that can be applied at different stages of the life cycle of silicon chips. At the design stage, the book presents a synthesis algorithm that help produce ageingresilient digital systems; in addition, it explores a number of application-dependent methods to improve system reliability. The book also discusses the state-of-the-art approaches for predicting ageing-induced failures and associated design adaptation techniques. More details on each chapter are provided below: Part I: Ageing Physical Mechanisms and Effects Chapter 1 provides a comprehensive review of the physical mechanisms causing the ageing of CMOS circuits. Chapter 2 provides a detailed analysis of the impact of ageing on the reliability and performance of integrated circuits. Part II: Ageing Mitigation Techniques Chapter 3 presents an application-level solution to mitigate the impact of ageing on microprocessors using an anti-ageing software. Chapter 4 discusses the impact of ageing on SRAM memories and review different approaches to mitigate against such effects. Chapter 5 reviews the state-of-the-art techniques employed to enhance BTI lifetime reliability during digital synthesis. Part III: Ageing Monitoring and Adaptation Techniques Chapter 6 discusses the latest techniques used in ageing monitoring, including monitor designs and on-chip insertion methods. Chapter 7 discusses the design of an ageing monitor to detect ageing-induced performance degradation in SRAM memories. Chapter 8 presents a new design for a multipath delay monitor that used to predict ageing-induced timing errors.

Book Audience The book is intended to provide a comprehensive coverage of the latest research advances in the key research areas of integrated circuits’ ageing; this makes it a valuable resource for graduate students, researchers, and engineers working in these areas. I hope this book will complement the ongoing research and teaching activities in this field. Southampton, UK March 2019

Basel Halak

Acknowledgments

I would like to thank all of those who contributed to the emergence, creation, and correction of this book. First, I would like to thank my colleagues who have contributed chapters to this manuscript for taking the time to share their knowledge and for being very accommodating throughout the publication process. Special thanks go to the graduate students at Southampton, Grenoble, and Ioannina Universities for the many hours they have spent working in their labs to generate the experimental results. Of course, the book would not be successful without the contributions of many researches and expert in field of CMOS ageing.

ix

Contents

Part I Ageing Physical Mechanisms and Effects 1

Understanding Ageing Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Domenik Helms

2

The Effects of Ageing on the Reliability and Performance of Integrated Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Daniele Rossi

3

35

Part II Ageing Mitigation Techniques 3

Aging Mitigation Techniques for Microprocessors Using Anti-aging Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Haider Muhi Abbas, Mark Zwolinski, and Basel Halak

67

4

Ageing Mitigation Techniques for SRAM Memories . . . . . . . . . . . . . . . . . . . . Mohd Syafiq Mispan, Mark Zwolinski, and Basel Halak

91

5

Ageing-Aware Logic Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Shengyu Duan, Mark Zwolinski, and Basel Halak

Part III Ageing Monitoring and Adaptation Techniques 6

On-Chip Ageing Monitoring and System Adaptation . . . . . . . . . . . . . . . . . . . 149 Lorena Anghel, Florian Cacho, and Riddhi Jitendrakumar Shah

7

Aging Monitors for SRAM Memory Cells and Sense Amplifiers . . . . . . . 181 Helen-Maria Dounavi, Yiorgos Sfikas, and Yiorgos Tsiatouhas

8

A Cost-Efficient Aging Sensor Based on Multiple Paths Delay Fault Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 Gaole Sai, Mark Zwolinski, and Basel Halak

Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

xi

About the Editor

Basel Halak is the founder and director of the embedded system program at the University of Southampton and a fellow of the royal academy of engineering. He is currently a member of sustainable electronics and materials research group, as well as the cyber security group. He has written over 70 refereed conference and journal papers and authored two books, including the first textbook on physically unclonable functions. He received his PhD degree in Microelectronics System Design from Newcastle University and was then awarded a Knowledge Transfer Fellowship to develop secure and energy-efficient design for portable healthcare monitoring systems. He joined Southampton University in 2011 where he continued pursuing his research on developing reliable and secure systems. He has a long experience of the implementation flow of intergraded circuit from concept to silicon. His research expertise include the evaluation of security of hardware devices, the development of appropriate countermeasures and mathematical formalisms of reliability issues in CMOS circuits (e.g., cross talk, radiation, ageing), and the use of fault tolerance techniques to improve the robustness of electronics systems against such issues. He serves in several technical program committees such as HOST, IEEE IVSW, ICCCA, ICCCS, MTV, and EWME. Furthermore, he is an associate editor of IEEE Access and an editor of the IET Circuits, Devices & Systems journal and is also member of hardware security working group of the World Wide Web Consortium (W3C).

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Part I

Ageing Physical Mechanisms and Effects

Chapter 1

Understanding Ageing Mechanisms Domenik Helms

1.1 Introduction Besides the pure functional correctness of an integrated circuit, IC designers at all times had to also regard other important design metrics, called extra-functional properties. The first two extra-functional properties, existing since the dawn of integrated circuits, were die area and circuit delay. The advent of power concerns in the 1980s introduced a third extra-functional property and made severe technology changes necessary such as the transition from NMOS to CMOS or the introduction of constant field scaling. In the 2000s, several new extra-functional properties, such as the various leakage currents, process variations, self-heating and IR drops, added a wide variety of new physical effects [19]. These new effects made several drastic architecture changes necessary, such as hafnium-based high-k oxides and multi-gate transistors. Even though being known for quite a long time [24, 41], ageing effects did not start to become relevant extra-functional properties before the 2010s. As their impact rises with each upcoming ever-smaller technology generation, there is so far no transistor architecture-based solution available. At all times in the design of integrated circuits, an accurate prediction of the relevant extra-functional properties was the key for an effective design, keeping that property within its constraints. This is even more relevant for ageing effects: All former extra-functional properties, when poorly designed to be out of their constraints, failed in testing at the latest. Even though this might cause expensive design iterations, there is no in-field reduction in quality of service at stake. With ageing effects in contrast, even a careful testing cannot reduce the risk of an early system failure. Ageing aware design thus needs a reliable prediction of the

D. Helms () OFFIS – Institute for Information Technology, Oldenburg, Germany e-mail: [email protected] © Springer Nature Switzerland AG 2020 B. Halak, Ageing of Integrated Circuits, https://doi.org/10.1007/978-3-030-23781-3_1

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effects of ageing in order to optimize the system’s performance at its end of life. Optimally, this ageing prediction is not just reliable (never underestimated) but also tight. Today’s ageing models tend to vastly overestimate the ageing effects in many cases just to be on the safe side for some very rare occasions. This leads to huge overdesign efforts and thus finally to less performant or more expensive ICs. Ageing-related and unrelated failures can be studied, when comparing the two most famous and most expensive hardware bugs, Intel shipped in their entire history: The most famous hardware bug ever occurred was surely the FDIV bug from 1994. Five incorrect table entries (thus an erroneous design) led to false division results. As this did only affect a small number of value pairs, this bug was not found, and the chip was shipped. The necessary callback did cost Intel some 475 M$. Even though Intel did drastic improvements in their test coverage afterwards, the Sandy Bridge bug in 2011, which was caused by an ageing effect, could affect some of the SATA driver transistors. The chips all passed testing and were shipped to the customers, failing then in field after a short time. This bug did cost Intel an estimated 700 M$.

1.2 Chapter Overview The next section will introduce some basic concepts and give a brief overview on the observable ageing phenomenon, as well as over the fundamental working principles of MOSFET transistors. Section 1.4 will then detail the physics of oxide traps, explaining what oxide traps are, how they can be understood, how they can be activated and how they dominate the threshold voltage degradation of transistors. Section 1.5 then presents ageing models at all abstraction levels. Instead of explicitly modelling the trap physic, CET maps introduce a useful abstraction for virtually all ageing models. To enable modelling over years of operation time, models can additionally apply lifetime abstractions.

1.3 Basic Concepts Before going into the details needed to understand and predict the ageing effects, this section will introduce the basic terminology and concepts for the later sections. Ageing will phenomenologically be introduced, and finally, the relevant working principles of MOSFET transistors will be discussed.

1.3.1 Terminology At first, it is handy to introduce a clear definition of the terminology of the ageingrelated effects, which might occur: First of all, an error in general is any kind

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of action, which is producing an incorrect result. This might include everything from a wrong decision made by a human designer, leading to a design error up to an automated productions step, not behaving exactly as anticipated, leading to a production error. In contrast, a fault, which is also known as a defect is defined as an abnormal condition of a component. In the case of integrated circuits, faults are usually caused by a design or a production error, but an error does not necessarily have to lead to a fault. Faults changing the functional behaviour of the component are called functional faults, faults changing the extra-functional properties are called parametric faults. A typical example for a parametric fault is a too weak driving strength of a gate due to a design error or too high threshold voltage due to an error occurring in the oxidation process. Both errors will lead to an increase of the gate’s propagation delay, which might either be within the tolerable margins or lead to an abnormal timing behaviour of this gate. An unintended electrical connection (short circuit) or a missing connection (open circuit) due to a designer’s violation of design rules or due to process imperfections will lead to a change in the logic behaviour of a gate, thus a functional fault. Finally, a failure is a deviation of the expected service of a component. Failures in general are caused by faults, but especially a parametric fault can also lead to no failure and then called a masked fault. In the above example, a gate timing fault may or may not lead to a timing deviation for the entire network, the gate is used in. Only if the gate lies on a path with critical or near critical timing, the overall network’s timing is changed at all. Only if the timing is shifted outside the constraints, a timing failure will occur. Note that even though two individual timing faults do not have to cause a timing failure, both of them in combination might. It is a typical property of parametric faults that they do not lead to a direct failure where they occur but instead lead to a failure in a higher hierarchy: A too thick oxide is a parametric fault for a transistor, which leads to a parametric timing fault not a failure from the perspective of a single gate. For an entire netlist of gates building a register transfer (RT) component, strict timing bounds can be defined; thus the gate timing fault might or might not be translated into an RT timing failure. In the context of integrated circuits, failures which are not caused by a design error are either coming from process variations (already existing at production) or from ageing (occurring over time). While process variations is a deviation between the planned design and a concretely produced chip due to production errors and prediction (thus design) errors, ageing is in the context of this chapter a deviation from the initial quality of a component due to the accumulation of faults over the lifetime of a component. As presented in Table 1.1, process variations and ageing can be further sub-divided: Process variations can either be random variations, occurring in an unpredictable way per feature (transistor, metal line, isolation area); a variation gradient, effecting all features in a certain area in the same way, leading to hot spots, corner-to-corner deviations, die-to-die variations, wafer-to-wafer variations, lot-to-lot variations or even fab-to-fab variations; or systematic variations, occurring in the same way in each instance.

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Table 1.1 Failure taxonomy and examples for each failure class Failure Ageing Degradation Bias temperature instability Hot electron degradation

···

Spontaneous Electro migration

Process variations Random Random dopant fluctuation

Time dependent dielectric breakdown

Line edge roughness

···

···

Gradient Mask tilt

Systematic Sidewall ion scattering

Thermal gradients at oxide formation ···

Optical proximity correction artefacts ···

An ageing failure caused by the occurrence of a single (usually functional) fault is referred to as spontaneous failure; an ageing failure caused by a drift in parameters due to the accumulation of parametric faults is called degradation. An ageing failure that, once occurred, will remain forever is called a permanent failure. If the failure can disappear, it is called a transient failure instead.

1.3.2 Ageing Phenomena The most effective, earliest reported and thus most prominent ageing effect surely is the negative bias temperature instability effect (NBTI). NBTI occurs predominantly in PMOS (or p-type or p channel) transistors and causes an increase in the transistor’s absolute threshold voltage. In analogue circuits, NBTI typically directly leads to a functional fault, which can accumulate to a functional failure over time. In digital circuits, it leads to a degradation of the switching speed, which does not directly lead to a failure but accumulates each time the system is under stress. Finally, NBTI can lead to a parametric transient timing failure for digital systems. Stress in the case of NBTI means that the PMOS transistor is in inversion; that means that its gate to body potential is substantially below 0 V for analogue circuits or at VGB = −VDD for digital circuits. Higher voltages and higher temperatures both have an exponential impact onto the degradation, induced by NBTI. As soon as the stress is removed, the threshold degradation can regenerate, again with an exponential temperature dependence. Regeneration of NBTI obviously does not depend onto voltage levels, as the condition of stress removal is that VGB is close to zero. Especially for so-called high-k devices, also a similar effect, positive bias temperature instability (PBTI) can occur; predominantly in NMOS (or n-type or n channel) devices, PBTI has a similar degradation and healing behaviour and voltage and temperature dependency as NBTI. In fact, NBTI and PBTI are both manifestations of the same underlying process, even though the molecular basis

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for both effects is slightly different (see Sect. 1.4). High-k devices are typical for all technology nodes from 45 nm (introduced in 2007) and below. High-k devices replace most of the silicon oxide from the gate insulation layer by hafnium oxide for the sake of a high subthreshold slope (see Sect. 1.3.4) while keeping the gate tunnel effect [20] low. Only PMOS NBTI and NMOS PBTI play an important role in terms of ageing. Nevertheless also the two further combinations of PMOS PBTI for high-k devices and NMOS NBTI can occur. As all four effects can be explained by the same mechanism just with changed polarity, in the remainder of this chapter, all four combinations are referred to as bias temperature instability (BTI). The second important and also long-time known [41] effect is hot carrier degradation (HCI), which is often referred to as hot carrier injection. As finally it turned out that there is no injection taking place in this effect, we refer to it as hot carrier degradation but nevertheless use the much more common abbreviation HCI, trying to avoid confusion. Like BTI, HCI leads to an increase of the transistor’s threshold voltage, affecting both NMOS and PMOS devices. HCI seems to have just a weak temperature dependency. Instead, HCI dominantly occurs under a certain combination of drain and gate voltages [5]. In fact the difference in thermal and especially voltage dependency is the best option to separate both effects in measurement [38]. Unlike BTI, it seems to be no or just little recovery for this effect [43]; thus HCI and BTI both contribute to the same parametric permanent timing failures for digital systems and functional failures for analogue systems. It is assumed, that BTI and HCI can both be explained by the same molecular faults but with different electrical activation mechanisms. Even though random telegraph noise (RTN) is rather a noise than an ageing effect, it is nevertheless closely linked, especially to the BTI effect. A substantial part of the RTN effect can be explained by the BTI effect degrading and regenerating on very short time scales [48]. BTI is caused by discrete events (see Sect. 1.4), each with their individual typical timing for degradation and regeneration [15]. The shortest of these events are distributed over the μs range. Their frequent degradation and regeneration can explain the RTN behaviour. In that sense, RTN is similar to BTI, just occurring on shorter time scales. In time-dependent dielectric breakdown (TDDB), disturbances (conductive faults) in the transistors oxide silently sum up over a long period of operation time. At first the observable tunnelling current rises in discrete steps, which is called a soft breakdown, causing parametric power and timing faults as the gate tunnelling leakage rises and thus the charging of a fan-in slows down. Finally, the gate tunnelling current enters a runaway situation in which the drastic increase in tunnelling current results in a short circuit of the gate oxide and thus a spontaneous permanent failure of the gate [6]. In electro migration (EM), high currents and high temperatures in the interconnect structures can lead to a relocation of the interconnect metal, again leading to open circuits (where metal is lost) and short circuits (where the metal is accumulated) [27]. Even though these effects are caused by an accumulation of

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faults, they lead to almost no noticeable parameter degradation until the component spontaneously fails, thus leading to spontaneous permanent failures. Ionizing radiation, striking the transistor can ignite the latch-up effect, causing two parasitic bipolar transistors inside the MOSFET structure to amplify each other leading to uncontrollable supply to ground current flow and finally the thermal destruction of that gate, thus clearly leading to spontaneous permanent failures. Ionizing radiation might also cause a glitch, a transient change of a transistor’s output voltage. In sequential circuits such as latches, registers and memory cells, these glitches can also cause the sequential loop to switch its state. This effect can cause permanent failures from a data point of view but only leaves a transient fault from a hardware perspective. Besides these microscopic ageing effects, occurring in the fundamental structures of an embedded system, there are also many macroscopic effects such as thermal cracking, occurring due to diverging thermal expansion of different materials or delamination. These macroscopic material science effects are not in the scope of this chapter.

1.3.3 Mission Scenarios As described in Sect. 1.3.1, while producing integrated circuits, production defects, imperfections and process variations may occur, which may either directly lead to a failure (then accounted for as yield loss) or may never lead to a failure (then called masked errors) or may lead to a spontaneous failure sometime within the lifetime of the component. Over-proportionally many of these spontaneous failures are activated very soon after the first usage of the component. Due to various effects, integrated circuits suffer from a high infant mortality. Thus, the systems are usually applied to high stress conditions for a short time (called burn-in) before testing in order to be able to provoke these effects and screen for early deaths. Over the entire lifetime of the system, the system may fail with a low but finite probability due to the spontaneous failures such as latch-ups. After a certain mission-dependent time, the probability for a parametric failure caused by a degradation mechanism will start to exceed the failure rates for the spontaneous failures. In total, this results in a characteristic bathtub distribution (Fig. 1.1). The point in time, where this wear-out begins, and generally the entire degradation behaviour, both are determined by two factors: Firstly, the initial condition of the system will mainly due to production errors (process variations) result in an individual distribution of faults, directly or indirectly influencing the degradation behaviour per transistor. For instance, the distribution and structure of defects in the oxide are directly influencing the BTI timing; the distribution of dopants in the channel then influences the impact of each oxide defect onto the device’s threshold voltage. Secondly, ageing strictly depends on the dynamically changing operation conditions, especially voltage levels, temperatures and duty factors. A duty factor describes the ratio of time in which a digital system is under stress. Due to power

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Fig. 1.1 The three major contributors to the integrated circuit failure probability over time are the early life failures, quickly reducing in probability over the first hours or days of operation; failures with a constant failure probability, such as radiation induced failures; and wear-out failures due to ageing

management techniques such as dynamic voltage and frequency scaling or power gating, due to typical idle phases and due to effects such as signal correlation, selfheating and IR drop, these quantities (temperature, voltage and duty factor) are neither constant nor unpredictable. In contrast, they have a vast impact onto the pace of degradation. In order to assess the ageing behaviour of an integrated circuit, either by measurement, by simulation or by modelling, these factors have to be understood and well defined. If the expected lifetime of the system, as well as the history of temperature, voltage and duty factor for the system, is specified, this specification is referred to as a mission scenario. In the simplest case, the mission scenario just states worst-case assumptions, asking to measure, simulate or model the ageing behaviour of a system, which is for its entire lifetime at the worst-case end of its specifications (i.e. highest temperature, highest voltage, always under stress). For some applications, with highest reliability demand, this assumption might be a good choice even though it obviously leads to a drastic over-prediction of the ageing and thus to reduced system quality and/or increased design cost. At and below moderate reliability requirements, it is possible to loosen the worst-case assumptions to some degree in order to increase quality or reduce cost. For instance, a car manufacturer might shoot for 20 years of failure-free regular operation but only if the system shows a typical pattern of usage, such as being active for less than 2 h per day on average. For more heavy usage, their lifetime requirements might be lower. When specifying these requirements into the mission scenario such as worstcase temperature of 175 °C (from ambient, motor heat and circuit self-heating) only for 2 h a day and worst-case ambient temperature of 55 °C for the other 22 h as well as a duty factor of 2 h a day, a much tighter ageing assessment can be made, leading to less overdesign, less design costs and/or higher quality.

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1.3.4 MOSFET Transistor Basics This section aims at giving the reader the background in transistor physics, needed to understand the context of the following sections, especially Sect. 1.4. Even though there are various transistor technologies available, virtually all transistors used today are metal oxide semiconductor field effect transistors (MOSFET). The basic working principle of a MOSFET transistor is that a silicon lattice is doped to become a majority carrier conductor at both ends (source and drain) and a minority carrier conductor in between (channel). Majority carrier means an electron in case of an NMOS transistor and a hole in case of a PMOS transistor; minority carrier refers to the opposite polarity, respectively. The gate is above to the channel, only separated by an isolating layer, called the oxide layer. In the same way that the doping can control the ratio of free electrons and holes (and thus which of them becomes the majority carrier), also an electric field, applied by a gate voltage, can change this ratio. The working principle of MOSFET now is that the gate field acts on the channel in exactly the opposite way, the doping did, thus converting the minority carrier dominated channel into a majority carrier conductor. This process is called inversion, and it exponentially increases the amount of majority carriers, available for the source to drain current. The rate at which the inversion takes place is described by the source-drain current equation [35]: ISD = I0 · e

VGS −Vth nVT

(1.1)

where n is called subthreshold slope which can be computed as n=1+

Cdep , Cox

(1.2)

where Cox is the capacitance between gate and channel and Cdep is the capacitance between substrate and channel. The subthreshold slope is the fundamental problem of today’s MOSFET transistors in general: In order to switch on and off quickly without huge power consumption, ISD needs to be reduced and increased as much as possible by as little VGS voltage swing as possible. Therefore the subthreshold swing n needs to be as small as possible. From Eq. 1.2 we can immediately see that we therefore need to make the channel to substrate capacitance as small and the oxide capacitance as large as possible. We can also see from Eq. 1.2 that n can never become less than one. That means that at room temperature T = 300 K ⇒ VT =

kB T = 1.38 · 10−23 J/K · 300 K/1.60 · 10−19 As ≈ 25.85 mV e− (1.3)

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Fig. 1.2 Qualitative behaviour of a 130 nm SiO2 bulk, a 45 nm high-k, and a 14 nm FinFET technology: The higher gate capacitance from the HfO2 oxide already resulted in a substantial decrease in subthreshold slope. The multi-gate structure of the FinFET also reduces Cdep while further increasing Cox . The coming nanowire devices might even approach the theoretical slope limit of 60 mV/dec. Together with the threshold voltage, these two parameters dominate the transistors operation speed (Ion ), standby power (Ioff ) and efficiency (Ion /Ioff )

Thus, without knowing any other transistor parameter and assuming optimal values for Cox and Cdep , we can deduce that an increase of 25.85 mV in VGS is at least needed to rise the drain to source current by a factor e or equivalently VGS and must rise by a factor 25.85 mV · ln (10) ≈ 60 mV

(1.4)

to let IDS rise by a factor of ten (see Fig. 1.2). This slope limitation ultimately caused the end of voltage scaling back in 2003 as the threshold voltage should not be below 3–4 times the subthreshold slope to ensure a factor 1000–10,000 Ion to Ioff ratio. The slope limitation is also the main motivation behind all major technology changes such as high-k devices (increasing Cox while keeping tunnelling currents under control) and multi-gate devices (increasing Cox and decreasing Cdep at the same time). In the near future, this slope limitation may even cause a technology change away from MOSFET towards so-called steep slope devices. Most promising candidates here are tunnel FETs, being theoretically able to reduce the subthreshold swing to below 1 mV and being demonstrated to actually do below 32 mV[40], allowing stable operation at 0.1 V supply voltage. For our recent 3D multi-gate MOSFET devices, the unavoidable process variations are already spoiling deeper scaling, as variations in the cutting edge threshold

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voltage lead to extreme power and timing issues. In these deeply scaled devices, the charge of a single electron or hole, when trapped in the oxide, will lead to a measurable change of the effective threshold voltage of the entire device. This is exactly what causes ageing: charges can get trapped in the oxide and will then accumulate over time. For the most dominant effects, this leads to an increase in threshold, most dominantly for the PMOS devices, which then leads to lower Ion , which again leads to longer transition times. To conclude this section: As MOSFET devices have a finite subthreshold slope, their power and timing behaviour is extremely vulnerable towards variations in the threshold voltage. Ageing occurs due to traps in the oxide, modifying the threshold voltage. In the following chapter, we will thus study oxide traps in more detail and will understand that knowing the state of each trap in each transistor at any time completely specifies the ageing behaviour of our system.

1.4 Oxide Defects Despite the large variety of ageing effects introduced in Sect. 1.3.2, it turns out that most of the relevant effects, such as NBTI, PBTI, HCI, RTN, and TDDB, all can be explained by imperfections in the gate oxide. Thus this section discusses the recent understanding of formation and activation of these oxide traps in detail.

1.4.1 Trap Formation The first observations ever made on any ageing effect were already reported in 1977. There is a systematic upshift in the threshold voltage of PMOS devices over their lifetime [24]. This effect, at first referred to as negative bias stress, was since then observed in all PMOS devices. In those early days, the technology structures were large, and the BTI behaviour was very smooth as presented in Fig. 1.3. From this figure, it is obvious that the BTI effect depends on both the temperature and the voltage and it leads to an increase in threshold voltage under stress and a decrease once the stress is removed. The first explanation at hand for this phenomenon was the reaction-diffusion model (RD), which was already proposed by [24]. The RD model is explained by the hydrogen atoms passivating the channel oxide barrier [31]. Hydrogen naturally occurs at the oxide to channel interface. It is used to passivate dangling bonds stemming from the slight lattice size mismatch between the channel’s silicon and oxide’s silicon oxide. If a dangling bond is not passivated, it leads to a positive charge in the interface, which will effectively counteract the field from the gate – thus increasing the threshold voltage. The RD model now proposes that positive charges can enter the silicon-hydrogen bond under stress, leaving a silicon with only three bonds to other silicon atoms and a positive charge due the one missing

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Fig. 1.3 Influence of temperature and voltage onto threshold degradation and regeneration

Fig. 1.4 Reaction-diffusion model for BTI. Trapped holes can weaken the bonds of the hydrogen passivation in the channel interface. Over time, the diffusion front moves under stress

electron, which used to be shared with the hydrogen to form this bond. The now free hydrogen can get lost, reacting with another hydrogen ion to form a neutral hydrogen molecule. The neutral hydrogen can then diffuse away (see Fig. 1.4), as it is no longer affected by any fields, holding it back. In RD, healing was explained by hydrogen, recombining with the defects if the stress is removed soon enough before the hydrogen diffused away for good. Once the hydrogen diffused away a certain distance, the open bond remains open and leaves a permanent damage. Even though the predictions of the RD model suited the observations of the early technologies well, measurements using more recent transistors showed significant deviations. RD completely failed to explain the time constants, observed for small devices. In 2009, the alternative trap charge model (TC) was thus proposed [14].

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In the TC model, BTI is explained by molecular defects inside the oxide. In a first version, it was assumed that oxide vacancies (defects, where silicon directly bonds to another silicon without an oxygen bridge) cause such defects. The initial model also proposed a two-state process [14], where the traps in the oxide are initially uncharged (state 1) and can capture and store a positive charge (state 2). Even though this model could much better explain the measured time constants, it still stood in contradiction with the measured distributions of capture and emission times. In [15], the model was extended to a four-state model (equivalent to Fig. 1.5a, b, d, e) but with oxygen vacancies instead of hydroxyl groups as follows: The neutral state (Fig. 1.5a) can trap a charge under stress, which will usually discharge again after a short time. In the trapped state (Fig. 1.5d), a silicon-oxygen bond is weakened,

a

b

c

d

e

f

Fig. 1.5 Charge traps in the oxide are formed by lattice imperfections. In the initial configuration (a), a single hydrogen atom might cause a deviation from the conventional silicon-oxygensilicon structure. Under stress, holes will be frequently captured and reemitted (ad). Elevated temperatures increase the probability for a molecular change of the oxide (de). Depending on the exact molecular arrangement, (e) might be stable over long periods of time. Transitions such as efc can also explain, why certain traps seem to disappear and reappear over larger time spans

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facilitating a structural (molecular) transformation into another quasi-permanent state (Fig. 1.5e). In state (e), a positive charge is trapped inside the oxide, leading to an increase of the threshold voltage in PMOS. Once the stress is removed, a trapped charge (Fig. 1.5e) can then either undergo a structural relaxation (Fig. 1.5d) first and discharge to the neutral state afterwards (Fig. 1.5e) or discharge first (Fig. 1.5b) before the structural relaxation. This four state model could already explain oxide traps with individual capture and emission times. When measuring BTI in silicon, there is another effect which is in contradiction to this TC model [15]: Individual traps in the oxide can be observed over a period of time, after which they seem to disappear. After some time, up to weeks of absence, the traps then reappeared with exactly the initial behaviour. In [48], the TC model was thus extended again, resulting in a six-state model, as displayed in Fig. 1.5. Other molecular disturbances than oxide vacancies, such as hydroxyl groups or hydrogen bridges, are analysed in [48]. They then added two additional states the system can pass, finally ending in a neutral quasi-permanent state (Fig. 1.5c), explaining the disappearance of a trap. As there was strong evidence that hydrogen plays an important role in BTI, the RD model was favoured by many research groups, even after the introduction of the TC model and even though the time constants observed in BTI could better be explained by the TC model. Detailed measurements at single traps showed time constants up to weeks, while small devices with just 1–2 nm thick oxides can explain time constants in the order of milliseconds [15]. As of today, this dispute is settled [16], with the updated version of the TC model, where traps are formed not by oxide vacancies but by hydrogen bridges (silicon-hydrogen-silicon bonds) or hydroxyl groups (silicon-oxygen-hydrogen-silicon bonds) inside the silicon oxide [48]. As this new model fits well to all observed NBTI and PBTI data for NMOS and PMOS, most scientists today agree on the TC model. Nevertheless, there are some recent publications, still referring to RD.

1.4.2 Trap Activation Section 1.4.1 explained how charges can be captured and released inside the gate oxide and how this qualitatively influences the threshold voltage of large devices in a seemingly continuous way. Today’s transistors are very small, the density of these oxide charge traps is not too high in silicon oxide, and they are randomly distributed. Thus, when screening small enough transistors on a test chip in a decent technology, it is possible to find single transistors having just a few or even just one single trap in their oxide. When finding such a transistor, it is possible to study the behaviour of each individual trap in great detail. Such an analysis is then called time-dependent trap spectroscopy [15]. As sketched in Fig. 1.6, it seems as if each single trap has a fixed contribution to the threshold voltage. When analysing devices of different sizes, the absolute shift (in mV) of the threshold voltage tends to become larger with smaller device

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Fig. 1.6 Regeneration behaviour for a small transistor, with only five significant traps in the oxide. Top part: After a standardized stress phase, the threshold voltage regeneration is observed several runs for the same transistor. Threshold degradation and regeneration both occur in discrete steps. Bottom part: Each regeneration (as well as degradation) step shows a tight temporal distribution around an average emission (as well as capture) time. The step height per trap is almost identical for all runs

geometries [48]. For a fixed temperature and voltage, the time to capture and reemit a single trap shows a characteristic distribution around a certain average capture time (τc ) and emission time (τe ). Repeating the measurement for the same device at different temperatures indicates that the capture and emission effect are both thermally activated, requiring the thermal energy to overcome a certain activation energy, described by an Arrhenius term eEa /kb T with fixed activation energy Ea . In [15] a nonradioactive multiphoton process (NMP) is suggested. It leads to the following average capture time τc and emission time τe and their dependency towards temperature T and stress voltage V : τc = τc,0 (V ) · eEc /kB T

(1.5)

τe = τe,0 · eEe /kB T

(1.6)

Both constants τc,0 and τe,0 depend on several other parameters. Especially τc,0 shows an exponential dependence onto the stress voltage, while τe,0 is almost independent of the stress voltage. In contrast to the simple temperature dependency,

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each trap has a certain minimal voltage, needed for activation. Below this voltage, the trap is never activated [9]. Both time constants are typically roughly in the same order of magnitude. In contrast, the distribution of both time constants for capture and emission, induced by the distribution of the τ0 values, is spread over many orders of magnitude ranging from at least the microseconds below which no measurement data is available and ranging to years, decades and even beyond centuries. The activation energies Ec and Ea are both typically around 0.54 eV±0.07 eV for PMOS [13] and as the Boltzmann constant is kB = 8.62 · 10−5 eV/K, thus E/kB ≈ 6000 K. This rough estimation allows predicting the acceleration of the ageing effect under thermal influence: Assuming a trap with a given capture or emission time constant τ at room temperature (300 K) and increasing the temperature by 100 K will reduce the time constants for degradation and regeneration as follows: τ = τ (300 K) = τ0 · e6000 K/300 K = τ0 · e20 τ (400 K) = τ0 · e

6000 K/400 K

= τ0 · e

(1.7)

15

(1.8)

⇒ τ (300 K) ≈ τ (400 K) · 800

(1.9)

We have seen that from room temperature to typical worst-case conditions of integrated circuits, the time constants for degradation and regeneration are both reduced by almost three orders of magnitude. This strong and well-known thermal dependence can be used for accelerated ageing, enabling to measure the ageing behaviour to be expected over decades within weeks at elevated temperatures.

1.4.3 Trap-Based Degradation The trap physics presented in Sect. 1.4.2 is well suited to explain NBTI, PBTI, and RTN as follows: The oxide forms charge traps with time constants ranging from microseconds to beyond centuries. Traps for which both capture and emission times are small (below and around seconds) will be constantly captured and reemitted, thus inducing a constant, step-wise change of the threshold voltage, explaining the occurrence of random telegraph noise. The same kind of traps with intermediate (minutes to days) time constants can explain NBTI degradation under stress as well as regeneration. Finally traps with extremely long emission times (above month) can explain a certain share of (quasi-)permanent threshold voltage damage, observed in NBTI. Even though the molecular mechanics of trap formation is different in hafnium oxides, used in high-k devices, they can form similar traps for negative charges [26], leading to a very similar threshold voltage degradation behaviour in NMOS and NBTI does in PMOS (see Fig. 1.7). In contrast to BTI and RTN, which are caused by carriers attracted by the gate field, tunnelling into the traps, HCI is caused by hot carriers, accelerated by the source to drain field. Even though HCI is completely independent from BTI, both

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Fig. 1.7 While NBTI occurs due to imperfections in the silicon oxide layer, leading to hole traps, PBTI occurs due to imperfections in the hafnium oxide layer of high-k transistors, leading to electron traps

Fig. 1.8 HCI is explained by hot electrons breaking the silicon-hydrogen bonds, thus depassivating the dangling bonds. A multi-vibrational mode excitation model can explain how the hot electrons can gain enough energy to overcome the high energy barrier towards the transport state

lead to oxide traps being activated, again leading to a threshold voltage degradation. HCI is explained by completely different physical mechanisms and also shows a different voltage behaviour and almost no temperature dependency. These properties can also be used to separate BTI and HCI in measurements [38]. Due to the nature of hot electrons, HCI leads to trap activation predominantly at the drain side of the transistor. The exact mechanisms of HCI are still controversial. In [44], a model is developed, where the traps are formed by the hydrogen passivation, which was originally proposed for the explanation of the BTI effect in the RD model (see Sect. 1.4.1). Earlier models suggested hot lucky electrons to break the bonds, but as the energy of the individual hot electrons is very unlikely to exceed the energy needed to activate a single of these silicon-hydrogen bonds, [44] proposes an accumulation of several excitements until the activation energy is finally exceeded (see Fig. 1.8).

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Besides these effects, there is the TDDB effect, also related to oxide traps. In general, TDDB refers to the loss of isolating properties of a dielectric layer. If this dielectric layer is the gate oxide, TDDB will initially lead to an increase in the gate tunnelling current [20]. This soft breakdown can already lead to a parametric degradation. After a long accumulation period, TDDB leads to a catastrophic reduction of the channel to gate insulation and thus a functional failure of the transistor. Two different physical models for explaining the TDDB effect were proposed. In the anode hole injection model, it is assumed that electrons tunnelling through the oxide can generate holes, which can tunnel back into the oxide. Once a critical hole density in the oxide is reached, the oxide breaks down. An alternative model proposed that electron traps in the oxide trigger the breakdown. Both models were combined by [8] into the percolation model: Each oxide trap creates an area of higher conductivity where it is located in the oxide. The first traps occurring increase the tunnelling probability via the trap and through the oxide. With a rising number of traps, these can form conducting paths through the oxide, finally causing hard breakdown.

1.5 Ageing Models We have seen that oxide traps are the major cause for all the ageing effects, presented in Sect. 1.4.3. Thus modelling these ageing effects usually means finding abstract descriptions of the oxide trap occupation and describing their impact onto the circuit behaviour. In this section, we will discuss ageing models at different abstraction levels. At each level, more assumptions and restrictions have to be made, resulting in less accurate models on one hand, but in much simpler, quicker and more applicable models on the other hand. The models presented in the following sections are applicable at different abstraction levels from TCAD to system level. They also differ in the handling of traps – describing them individually causing threshold voltage steps or, as a distribution function, influencing the expectation value of the threshold voltage. Finally they differ in their flexibility describing varying stress over time from accurately regarding time dependencies to just accepting a single worst-case value per parameter.

1.5.1 Explicit Trap Model A first model abstraction step, which is employed by virtually all ageing models, is the following. Instead of measuring the trap distribution for each individual transistor, a trap distribution function for many devices of a certain technology is measured. This step results in a large list of traps with their influence onto the threshold voltage and the activation energies for capture and emission.

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The most direct models at the technology CAD (TCAD) level, such as [18], actually regard each trap individually as well as an explicit instance of process variations. Thus, such tools need a concrete trap list. Nevertheless, a trap distribution is used in the first place, from which several instances of concrete trap lists can be randomly generated, thus allowing a Monte Carlo variation analysis of a device. Explicitly regarding each trap individually allows to model the quantization of threshold voltage degradation and regeneration. This is also necessary for the prediction of RTN. As the activation energies for each trap are explicitly known, the model reacts most accurately onto temperature and voltage variations. This allows to accurately perform a BTI, HCI, and RTN analysis and derive, for instance, Spice models from there. Based on the knowledge of the distribution of time constants per trap and the distribution of variation parameters, it is possible to do statistical Monte Carlo simulation and thus get example traces for possible threshold damages per transistor, but this is a very time-consuming process. A good TCAD tool will also regard the interplay between the exact horizontal trap position and the distortions of the channel due to process variations. In real devices, the channel is not uniformly conducting, but due to process variations, such as random dopant fluctuation [42], the current through the channel flows predominantly through certain hot routes. A trap above such a hot route will have a much larger impact onto the devices threshold voltage than a trap above a region with almost no drain to source current flowing.

1.5.2 Stochastic Trap Models A second model abstraction step, which is taken by all ageing models above the TCAD level, is to replace the binary trap activation with an activation probability: Instead of a trap activating with a 50% chance in a certain time, it will be assumed to be 50% active after this time – thus contributing half of its assigned threshold voltage damage. Explicit trap models describe the physics of each trap effectively by at least three parameters, the average capture (trap activation) time, the average emission (trap passivation) time and the per trap impact onto the threshold voltage. One of the first abstractions of this was [37], enabling a simulation in Spice by introducing a representative circuit. Here the real nature of a discrete trap, which can be either charged or uncharged, was replaced by a continuous probability of being charged. This simplification disables the prediction of random telegraph noise effects, as no spontaneous increases or decreases in threshold voltage can be described anymore. In contrast, the model allows the prediction of the average ageing behaviour of a transistor – or more precisely – the prediction of the expectation value of the threshold damage due to ageing. When using stochastic trap models, a Monte Carlo analysis is only needed to assess the impact of process variations. Short of the averaging, the stress, temperature and voltage history influences are still very accurately represented with stochastic models.

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If we assume having two individual traps with almost identical capture (τc ) and emission (τe ) times and individual contributions to the threshold voltage damage Vth,1 and Vth,2 , they will behave differently from a single trap with the same τc and τe but a total threshold voltage damage of Vth,1 + Vth,2 . And while an explicit trap model would simulate two discrete steps in threshold voltage of Vth,1 and Vth,2 closely together in time, in a stochastic trap model, both models would be exactly half activated and thus contributing Vth,1 /2 + Vth,2 /2. Thus in a stochastic trap model, it is no longer necessary to simulate all traps from an entire distribution individually. Instead, traps with similar capture and emission times can be lumped together into a single representative trap. Such a simplification to the trap list was already proposed [37]. They introduced a two-dimensional histogram, summing up the threshold voltage damage of all traps within a certain range of capture and emission times. This histogram is referred to as capture-emission time (CET) map, see Fig. 1.9. That way, the number of traps to be regarded per transistor can be drastically reduced. They proposed to describe the activation of each CET map class directly in Spice using a representative RC circuit. CET maps can also be obtained much more efficiently than trap lists: Instead of applying a TDDS analysis [15] to a large number of small devices, each with identifiable trap contribution, it is possible to directly measure the CET map by monitoring the degradation and regeneration of a large device, having many traps [17]. This can be done conveniently using a differential method. The transistor is stressed for a period of time referring to the upper boundary of the first capture time bin, in the example of Fig. 1.9, this was tstress = 3.16 μs,1 and the threshold voltage damage Vth,0,0 is measured immediately. Now the threshold voltage regeneration Vth,i,0 by emission of traps is measured at times, corresponding to the upper limits of the histogram bins. In our example at trelax,i ∈ [3.16 μs, 10 μs, 31.6 μs, 100 μs, . . .]. The cumulative threshold voltage damages for the first row in our CET map now results to Vth,0,i = Vth,0,i − −Vth,0,i+1 . large device

CET map 109

106

106

106

10

3

100

10

capture time τc [s]

109

capture time τc [s]

capture time τc [s]

small device 109

3

100 10-3

10-3 10-6 -6 10

10 -3 10 0 10 3 10 6 emission time τe [s]

10 9

10-6 -6 10

10 -3

10 0 10 3 10 6 emission time τe [s]

10 9

103 100 10-3 10-6 10 -6

10 -3 10 0 10 3 10 6 emission time τe [s]

10 9

Fig. 1.9 Individual trap distribution for a minimal sized (left) and a very large (centre) transistor. A CET map (right) can be obtained by building a two-dimensional histogram over the threshold damages per trap. Colour coded in the CET MAP is the overall threshold damage, summed up for all traps within the same τc and τe range 1 3.16

≈

√ 10, resulting in two equally spaced bins per factor 10 for logarithmic axes.

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Afterwards the transistor is completely regenerated by applying no stress voltage at high temperature for a sufficiently long time. The procedure is repeated, this time for an initial stress time corresponding to the upper limit of the second capture time bin; in our case tstress = 10 μs. The next row of the CET map then results as Vth,j,i = Vth,j,i − −Vth,j,i+1 − Vth,j−1,i . We have to subtract Vth,j−1,i for each row, since we otherwise also get the threshold voltage regeneration from bins with smaller capture times into the recent bin. A handy feature of the CET map abstraction, at least if we are looking for average ageing behaviour is that we can use the same full CET map even for small devices. Instead of randomly picking a small number of explicit traps (Fig. 1.9 left) from a typical distribution (Fig. 1.9 centre), transistors in each size can be described by the same CET map (Fig. 1.9 right). While a ten times larger transistor also has ten times more traps due to a constant trap density in the oxide, each single trap also has ten times less impact onto the threshold voltage. But CET map-based ageing modelling can even go one step further: [39] introduced a model for replacing a trap list for every transistor with a description of the average distribution of traps over all transistors, thus enabling to compute the expectation value of degradation far more easily. The extremely high time constants in typical CET maps, such as the 109 s ≈ 32 years in Fig. 1.9, obviously cannot be measured directly. Instead, it is extrapolated from a much smaller measurement window up to the 103 s, which is feasible for a repeated measurement campaign. In principle, healing also takes place under stress conditions, reducing the measured effect of degradation. This effect is described and modelled in [39]. The result of this model is extrapolated CET maps. In this model, the activation probability per histogram bin (with capture time τc and emission time τe ) can be predicted iteratively by P (τc , τe , t + t) = 1 − (1 − P (τc , τe , t)) · e

−t τc

(1.10)

if the system is under stress and by P (τc , τe , t + t) = P (τc , τe , t) · e

−t τe

(1.11)

if the stress is removed. The capture and emission times themselves capture the temperature T and voltage V dependency: τc = τc (T , V ), and τe = τe (T ). The overall threshold damage can then be computed as  Vth (t) =

 dτc

dτe Vth (τc , τe ) · P (τc , τe , t) .

(1.12)

This CET approach is able to describe HCI as well as BTI with the same trap data [23]. As direct trap models are the most accurate models, they usually serve as a baseline for all other, more abstract model assessments. Models that are more abstract are needed for ageing assessment of larger circuits as in the CET mapbased models there is still the need for recomputing the occupation probability for

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each trap in each transistor. Moreover, the time intervals (t in Eqs. 1.10 and 1.11) are many orders of magnitude smaller compared to the entire lifetime over which a simulation needs to happen.

1.5.3 Lifetime Abstraction The stochastic trap models presented in Sect. 1.5.2 have to operate in microscopic time intervals in the order of micro- or even nanoseconds to accurately capture the behaviour of all CET map bins. They may want to regard variable mission scenarios, usually varying in mesoscopic time intervals of seconds, minutes, or hours. Evaluating typical macroscopic operation times of years and decades is obviously prohibitive in such time bases. Several ideas for a third model abstraction step have been proposed. This step bridges the gap between microscopic cycle and macroscopic lifetimes. Such models can be classified into three distinct classes, each introducing some restrictions to model application and accuracy. 1.5.3.1

Analytic Models

The earliest models proposed at all where analytical models [1], which are still quite common in literature [2, 34]. Analytic modelling means ignoring the accurate mission scenario of activation, temperature and voltage completely or at least to a large extend. Analytic models instead assume worst-case temperature and voltage conditions as well as a periodic duty cycle or even permanent stress. They try to fit a parametric analytical function, describing the threshold degradation. The older reaction-diffusion-based models are usually approximated with power law functions [21, 30], typically with a time coefficient of Vth ∝ t 1/6 . Trap charge-based models are usually described by a logarithmic law [36] such as Vth ∝ a + ln(1 + t/t0 ) [4]. For trap charge models, it is even possible to determine the fitting parameters directly from the trap parameters themselves [3] . In order to assess the effect of the threshold degradation, these models either extrapolate the threshold voltage degradation over time and back-propagate it to a Spice description (for analogue or digital circuitry) or add a timing degradation model (for digital circuitry only) and use it to derate the per gate timings. The analytic models were the earliest reliability models at and above the Spice level. Prior to more sophisticated models, such as discussed below, it was not possible to compare their accuracy as a direct comparison against more accurate models over long times, even just over hours of lifetime. Having more accurate long-term predictions available, it is meanwhile clear that analytic models lead to a drastic overestimation of the timing degradation easily by a factor of seven (for 45 nm) and five (for 16 nm) [32] for a reasonable mission scenario. In contrast to most other analytic models, [2] can also include stress conditions, varying over mesoscopic time scales. They solved this issue by using piecewise analytical functions patching together the system’s behaviour over macroscopic phases of constant stress.

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1.5.4 CET Map Abstraction Stochastic trap models can accurately describe ageing under a given, nonconstant mission scenario but are orders of magnitude too complex to describe the behaviour of a larger circuit over its entire lifetime. In contrast, the analytic models are capable of providing lifetime ageing predictions, but they introduce very strict limitations onto the flexibility of the mission scenarios. Many safety critical systems, for instance, in the avionic or automotive application do not see a permanent maximum stress. Instead, their mission scenarios contain vast idle phases in which the system does not see any stress at all. For such systems, an analytic model will vastly overestimate the effect of ageing, leading to expensive overdesign. The CET map abstractions bridge this gap by enabling the definition of stress phases in the mesoscopic time, allowing ageing prediction over macroscopic times and being almost as accurate as the stochastic models, working in microscopic times. The idea of CET map abstraction is to describe the occupation of a given CET map with only a few abstract parameters. In such a map, the traps become activated bottom up (the capture time is the map’s y-axis) and passivated from left to right (the emission time is the map’s x-axis). The influence of stress patterns onto these parameters is then modelled, for stress phases, which can be assumed as constant over mesoscopic timescales. The art of finding a good CET map abstraction model is thus to find a good set of parameters, describing this map occupation sufficiently accurately while behaving predictably under stress. These models exploit the fact that the CET map entries are sorted from left to right by emission time and from bottom to top by capture time. The most obvious and direct choice for a parametric description of a CET map and thus of the ageing state of a transistor is threshold voltage degradation p1 = Vth . While p1 is a useful parameter for abstracting a CET map as it directly is what we need to conclude from this map, it is not sufficient on its own. Figure 1.10 left presents the threshold voltage degradation of two similar transistors. A long stress phase is applied to transistor A, followed by a shorter phase without stress. Transistor B sees a very long relax phase first then very short stress. If we interrupt the analysis in t2 , both transistors have the same threshold voltage damage. Nevertheless p1 is not sufficiently describing the ageing state of the transistors: If both from t2 and on see exactly the same stress, they will not however behave identically. Due to its stress history, transistor A has just active traps with long emission times activated (see Fig. 1.10 centre), all the quickly emitting traps have already been emitted. Transistor B has many traps with very short emission times activated (see Fig. 1.10 right). Thus in the next relax time, transistor B will heal its threshold damage quicker than transistor A. A model just abstracting a CET map to p1 would see no difference between transistors A and B and thus describe their behaviour identically. The idea of CET map abstraction is to improve the accuracy by adding further parameters, trying to describe the ability to heal the traps. In [10], P2 = max τc,act is suggested, which corresponds to τA and τB in Fig. 1.10. P1 is a measure of the total threshold voltage damage, and P2 is a measure of the total stress time, and the

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Fig. 1.10 Left: After a long stress phase followed by a long relax phase, transistor A has the same threshold damage as transistor B, which has a history of a very long relax and a short stress phase. Even under the same mission scenario, both transistors will behave differently. Centre: In the CET map of transistor A, only traps with high emission times are still active. (Passive traps are greyed out.) Right: In transistor B, only traps with low capture times and thus typically low emission times are active. In the future under the same mission scenario, transistor B will see more threshold voltage healing than transistor A Σ=500s

A

109

Σ=500s

B

106 P3

103 100

100

10

10–3

100

103 τe [s]

P2

P1

–3

10–6 –6 10

P3

103

P2

2ms

1000s

B

106

τc [s]

1000s 4ms

109

A 1ms

τc [s]

2ms

10–3

106

109

10

P1

–6

10–6

10–3

100 103 τe [s]

106

109

Fig. 1.11 After several stress – relax cycles, the shape of the active area closely resembles a pentagonal shape. Only the effect of the last active phase (right CET map) with trap times in the order of the duty cycle frequency is not correctly described by the abstraction

transistor has ever seen and thus a useful second model parameter. With P1 and P2 together, transistors A and B do no longer fall into the same abstraction class but can be well distinguished by the model. After a single stress phase, the active region in the CET map has rectangular shape, such as presented in Fig. 1.10 centre. After many stress and relax cycles, the active region takes a more complex shape: If, for example, the stress is applied periodically with 500 Hz and 50% duty cycle for 1000 s, the traps at the τc = τe , τc < 500 s, τc  1 ms line are all 50% activated. Traps with τc > 500 s are less than 50% activated, as 500 s exceeds the overall stress time that was applied. The traps with τc ≈ 2 ms are completely dominated by the very recent history, especially by the question if the mission scenario ended with a stress or relax phase (see Fig. 1.11). To actually get a very close abstraction, [10] suggests a third parameter. The more complex parameter P3 basically describes the average emission times of the active traps. While P2 just describes the long-term traps and P1 describes the overall effect, there is also a strong contribution from the duty cycle, captured by P3 .

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In [10] it is proposed that two transistors having identical area, height and slope width (or, respectively, having the same recent threshold degradation, the same overall stress time and a similar stress history) so far will behave very similarly onto future stress conditions. By introducing the abstract parameters P1 to P3 , [10] can accurately cluster all transistors to be analysed into classes of transistors, behaving almost identically under the same future stress. Modelling in this work is accelerated by precomputing the change in the threeparameter space as caused by different duty factors assuming constant temperature and voltage for short time steps. They use the low dimensionality of their abstraction to precompute the effect of different stress levels onto all possible parameter combinations: For each combination (P1 , P2 , P3 ) within reasonable bounds and with a small stride size, they generate a typical CET map activation, fulfilling p = (P1 , P2 , P3 ). A new CET map activation is computed by explicitly modelling each trap in the distribution individually. The new CET map activation then is backabstracted into p = (P1 , P2 , P3 ). Thus for each constant stress phase, for instance, for several seconds t of stress with a fixed duty factor d, a vector p (d) is computed for each p. From this, it is possible to compute a gradient gP1 ,P2 ,P3 (d) =

p (d) − p t

(1.13)

This approach enables describing the influence of duty cycles varying over time, e.g. due to power gating. The stress phases can be clustered into mesoscopic time steps, still having just a few percent error when compared with a stochastic trap model (see Sect. 1.5.2). This model was then extended [9] to also describe the effect of temperature and voltage, changing over time. Each time, the temperature changes; the shape of the CET map also changes in a predictable way. For both the capture and emission times, the thermal dependency is described by an Arrhenius term eEa /kT with fixed activation energy Ea . The parameters describing the occupation area are shifted accordingly. This especially means that at elevated temperatures, the total stress time rises quicker – according to the trap physic described in Sect. 1.4.2. Varying voltages are harder to handle in this approach: Each individual trap, contributing to a CET map, needs a certain minimum voltage to become activated. This means that this approach cannot correctly handle continuous voltages, but at least it is extendible to a set of fixed voltages, for instance, in order to describe the effect of voltage scaling in digital logic. Unfortunately, this restriction renders this approach almost useless for analogue circuitry. Stochastic trap models are very accurate but can only be computed for short lifetimes of seconds to hours within reasonable computation effort. For these lifetimes, the CET map abstraction models are comparatively accurate. In contrast to the stochastic trap models, the CET map abstraction models can also predict realistic lifetimes of several years. These extrapolations enable a fair evaluation of the analytic models. It turns out that disregarding variation of duty cycle, temperature

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Table 1.2 Comparison of the simulation times for 4 models for 100 transistors and 1 month of mission scenario and for a million transistors and 10 years of mission scenario (extrapolated). In all models, the stress state was averaged over periods of 1 s. The accuracy only refers to the period of 1 month and was not extrapolated but explicitly simulated Model Explicit trap [39] Stochastic trap [37] CET map abstraction [9] Trap centric [32]

Accuracy Ref. 4.2% 8.2% 0.5%

100 transistors, 1 month 89 h 26 min 14.1 s 0. On the other hand, when at least one of the inputs IN2 and IN3 is at low logic value (Fig. 2.1b), n1 source is charged up to Vs1 = Vdd − Vth . As a result, it is Vgs1 = Vth and, according to (2.1), transistor n1 does not experience any stress condition (ΔVth = 0), yet having its input at high logic value. Another interesting consideration can be given for transistors n2 in Fig. 2.3, for input configurations (IN1, IN2, IN3) = (0, 1, 0). In this case, in fact, the source

2 The Effects of Ageing on the Reliability and Performance of Integrated Circuits

43

node of the considered transistor is in a high impedance state, if we neglect leakage mechanisms. Consequently, its voltage value Vs2 depends on the input configuration at previous clock cycle (j − 1), as shown in the expressions of α n2 for the NAND gate in Table 2.3. Only if the node was discharged during the previous clock cycle, the nMOS transistor n2 turns out to be under stress. Analogous considerations hold true for the series pMOS transistors in the pull-up network of NOR gate, and the analysis performed can be easily extended to 4-input gates.

2.4.2 Ageing-Aware Gate Library and Delay Degradation In order to evaluate the BTI-induced degradation of logic gates’ propagation delay, a BTI ageing-aware gate library needs to be developed. A flow to derive such a gate library is depicted in Fig. 2.4. Stress ratios of logic gate transistors are first evaluated considering gate netlist and input signal probabilities; then, the obtained stress ratio values, along with operating temperature and power supply value, are utilised to calculate transistor threshold voltage degradation for each transistor in the gate, for all values of lifetime. The obtained data for each gate are then utilised to generate an “aged” library, which is then used to simulate complex circuits with all transistors mapped to the proper ageing [28]. The obtained aged library supports SPICE simulations that allow us to evaluate the effect of BTI ageing on propagation delay of basic logic gates, thus logic paths. The simulated NAND and NOR logic gates, with 2–4 inputs, have been implemented with a 32-nm metal gate, high-k strained-Si CMOS technology [29], considering a power supply of Vdd = 1 V and an operating temperature of 75 ◦ C. Simulation results are shown in Fig. 2.5. In particular, the normalised propagation delay is represented, where the normalisation factor is the delay exhibited by a logic

Fig. 2.4 Flow for workload and operating conditions – aware gate model characterisation

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D. Rossi

Fig. 2.5 Normalised propagation delay for different input signal probabilities for basic gates (operating temperature T = 75 ◦ C; NF: normalisation factor): (a) 2-in NAND (NF = 8.08 ps), (b) 3-in NAND (NF = 11.98 ps), (c) 4-in NAND (NF = 16.62 ps), (d) 2-in NOR (NF = 11.29 ps), (e) 3-in NOR (NF = 19.93 ps), (f, d) 4-in NOR (NF = 30.17 ps)

gate at time zero. Therefore, the plots in Fig. 2.5 highlight the degradation of the propagation delay over time, for different values of the input probabilities. Namely, for the input probability, there are two extreme cases Pi = 0.25 and Pi = 0.75, ∀i = 2 . . . 4, together with the average case Pi = 0.5. Therefore, in this analysis the input probabilities for all transistors have been considered all the same, and they have been labelled as Pin in Fig. 2.5. As we can see, the trend over time of gate propagation delays in Fig. 2.5 resembles the transistor threshold voltage degradation represented in Fig. 2.2. This is an expected result since, for the first-order analysis performed in Sect. 2.3, propagation delay varies almost linearly with the transistor drain current which, in turn, features a linear dependency on transistor threshold voltage, as shown in (2.4). For all simulated gates and input probabilities, delay degradation after only 6 months of operation exceeds 50% of overall degradation in 10 years of operation. It is interesting to notice that delay degradation is dominated by pMOS transistors ageing (Pin = 0.25) and increases with number of inputs for

2 The Effects of Ageing on the Reliability and Performance of Integrated Circuits Table 2.4 Normalised propagation delay for different input probabilities and delay variability after 10 years of operation

Logic gate NOT NAND 2in 3in 4in NOR 2in 3in 4in Average variability

Normalised propagation delay Input probability var1 0.25 0.5 0.75 (%) 1.179 1.177 1.165 1.40 1.156 1.149 1.142 1.138 1.160 1.151 1.141 1.92 1.165 1.154 1.142 2.27 1.142 1.136 1.130 1.27 1.124 1.129 1.125 0.85 1.106 1.107 1.105 0.07 – – – 1.31

45

var2 (%) 1.19 1.120 1.67 1.97 1.12 0.76 0.06 1.14

NAND gate, whereas decreases for NOR gate. Indeed, the stress probability of series pMOS transistors in NOR gates diminishes noticeably with the increase in number of inputs, as highlighted by Tables 2.2 and 2.3. This consideration does not apply to the parallel pMOS transistors in NAND gates. Another important characteristic that is worth highlighting is the generally small variability of delay degradation for different input probabilities and the noticeable difference between degradation trend for NAND and NOR gates. In order to better assess this variability, the following two metrics can be defined: var1 =

delay|max delay|max , ; var2 = delay0 delay (Pin = 0.5)

(2.11)

where Δdelay|max is the maximum difference of propagation delay for different input probabilities, and it is given by Δdelay|max = delay(Pin = 02.5) − delay (Pin = 0.75). Therefore, var1 represents the variability of propagation delay for different input probabilities against the delay exhibited by the considered gate at time zero; var2 is instead the variability of propagation delay for different input probabilities against the average case (Pin = 0.5). Values for the defined variabilities, along with those for the normalised propagation delays, are reported in Table 2.4. As can be seen, variability is very limited for all basic gates, with the NOR gate exhibiting a variability which is sensibly lower than for the NAND gate for all number of inputs.

2.5 Impact of BTI on Soft Error Rate of CMOS Circuits In the previous section, we have highlighted that BTI may induce a considerable delay degradation in CMOS logic circuits, possibly leading to an erroneous IC behaviour over time. In addition, recent works [18, 30, 31] have shown that BTI has a negative impact on the soft error susceptibility of ICs. Indeed, soft errors affecting CMOS ICs are of great concern for advanced technologies [12, 13, 32]. Due to

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the reduction in the technology node size accompanied by a decrease in supply voltage, charge stored on circuit nodes has been considerably decreasing in the past few years. As a result, CMOS circuits have become more prone to soft error due to energetic particle hitting sensitive areas in the circuit [33]. In fact, when an energetic particle (alpha particle, cosmic ray, etc.) hits a sensitive area of a CMOS device, it can generate a voltage glitch [34], also referred to as single-event transient. If the affected node belongs to a storage element, the induced voltage glitch can cause the flip of the stored logic value, thus causing a so-called soft error (SE) [35]. Similarly, if the affected node belongs to a combinational circuit, it can propagate through the downstream logic and being sampled by a storage element. Also in this case, a soft error manifests with an erroneous logic value at the output of the circuit [36]. Therefore, it is clear that, since BTI ageing degrades the electrical characteristics of CMOS devices, it makes them more susceptible to single-event transients and consequent soft errors. Indeed, as shown in [8, 18], the critical charge of a node strongly depends on the value of the restoring current of its pull-up/pull-down networks. Since BTI reduces the conductance of the circuit driving the affected node, the value of its critical charge reduces as well [18]. The effects of ageing on circuit soft error rate (SER) have been analysed in [14– 18, 30]. In particular, in [14, 30] the impact of ageing on the critical charge of SRAM cells has been assessed, showing that NBTI has a limited impact on the memory cell critical charge, thus on the memory SER. Instead, in [15], it has been analysed how the SER of some combinational benchmark circuits varies with circuit operating time. In [18], a detailed analysis on the impact of NBTI on the critical charge and SER is developed, showing that BTI makes combinational circuits more prone to SEs induced by energetic particles. In the next subsections, the impact of BTI on SER for both combinational logic and storage elements is analysed in detail, and hints for IC designers aiming at BTI resilient circuit design are provided.

2.5.1 Modelling of Single-Event Transients As known, when an energetic particle strikes the silicon, it travels and loses energy along a straight path. The denser the material, the quicker the particle loses energy, due to the higher density of charge with which it interacts [12]. Considering an alpha particle hitting an IC dies, while it loses kinetic energy, thus reducing its velocity, it allows more time for its positive charge to induce electron-hole pairs through Coulombic interaction [12]. Consequently, the charge generation rate increases with the distance travelled by the alpha particle and reaches its maximum near the end of the alpha-particle path. If an electric field is present in the region hit by the particle, such as the depletion region of a reversed biased p–n junction (usually referred to as critical area), the generated electron-hole pairs disturb the depletion layer. Inside the depletion region, the generated electrons drift to a more positive potential

2 The Effects of Ageing on the Reliability and Performance of Integrated Circuits

47

area, whereas the holes drift to a more negative one. This phenomenon reduces the net charge, causing a voltage variation, usually referred to as single-event transient (SET). For this analysis, alpha particles have been considered as energetic particles generating SETs, but the derived considerations and conclusions can be extended to other energetic particles. The current induced by an alpha particle hitting a CMOS circuit has been modelled in [37] by a double-exponential current pulse: I (t) =

 Q  −t/τα e − e−t/τβ . τα − τβ

(2.12)

Q is the total amount of charge collected by the affected node (dependent on the particle energy and trajectory), τ α is the collection time constant of the junction, and τ β accounts for the ion-track establishment time constant. These time constants depend on several process-related factors. For simulation purposes, we will hereinafter consider the values given in [38]: τ α = 1.64 × 10−10 s, and τ β = 5 × 10−11 s. If the collected charge reaches a critical value high enough to result in a voltage glitch with an amplitude exceeding the fan-out gate logic threshold, an incorrect logic value can be propagated. The minimum amount of collected charge that generates an incorrect logic value on the affected circuit is usually referred to as critical charge, and denoted by Qcrit . In combinational logic, the generated voltage glitch may propagate through the downstream logic and be captured by a sampling element, thus resulting in an SE. Instead, in sequential elements, the generated voltage glitch may directly result in an SE, also referred to as single-event upset (SEU) [12, 39]. Figure 2.6 shows the equivalent circuits used to emulate the current generated by a SET. In particular, Fig. 2.6a shows the equivalent circuit to be considered when the hit node is driven by pull-up network to high logic value and the SET generates a negative glitch. Analogously, Fig. 2.6b illustrates the circuit emulating a positive glitch affecting a node driven by pull-down network to low logic value. The critical charge Qcrit is employed to determine the SER of an electronic circuit. Indeed, the probability that an alpha particle striking a node j generates a

Fig. 2.6 Equivalent circuits used for the simulation of negative (a) and positive (b) glitches

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D. Rossi

SET exceeding the fan-out gate logic is inversely proportional to the node critical charge [40, 41]: Pgen,j (t) ∝ e−σ Qcrit,j (t) ,

(2.13)

where Qcrit is a function of operating time t because of BTI ageing, as detailed in Sect. 2.5.2, and σ is a fitting parameter. It is worth noting that, for an SE to be generated as a result of a SET, the voltage glitch induced by an energetic particle hit needs to propagate through the downstream logic up to a primary output of the affected circuit. In addition, if the particle hits a combinational block, the glitch that has propagated to one of its output needs to be captured by a latching element, as is discussed in detail in Sect. 2.5.2.3. Nevertheless, the estimation of the Qcrit is of utmost importance to evaluate the SER of a circuit.

2.5.2 Analysis of the BTI Impact on SER in Combinational Logic In this section, we analyse the impact of the n/pMOS transistor threshold voltage shift induced by BTI on the Qcrit of combinational circuits. Particularly, by means of HSPICE simulations, we evaluate the variation of Qcrit at the output of NOT, NAND and NOR gates, with a variable number of inputs (up to 4). Indeed, soft errors have been an important reliability threat for memory cells and storage elements for decades. However, with advances of semiconductor technology, combinational logic vulnerability to SETs has increased noticeably in the last few years, due to the reduction of the charge stored on circuit nodes and the decrease in noise margins. Meanwhile, with the increase in operating frequency, the likelihood that signals affected by SETs are sampled, thus giving rise to SEs, can no longer be neglected [32, 42]. In order to evaluate BTI-induced Qcrit variation, we have implemented elementary gates by a high-performance metal gate, high-k, strained-Si, 32-nm CMOS technology (with 1 V power supply) from PTM [29]. The gates have been designed in order to be with minimum area and symmetric. We have evaluated the threshold voltage shift of n/pMOS transistors induced by PBTI/NBTI degradation by utilising the model in (2.1). Particularly, we have simulated alternating stress and recovery phases, considering a 50% switching activity of inputs and an operating time up to 10 years. The estimated voltage shifts Vth for the considered operating time have been adopted to customise the HSPICE device model employed for simulation, as discussed in Sect. 2.4.2. To identify the worst-case condition for Qcrit evaluation, let us consider a generic symmetric gate described by an equivalent inverter [31]. Indeed, it is worth noting that CMOS logic gates are usually designed in order to be symmetric (at time zero) in the worst-case condition. In this case, the currents provided by the pull-up and

2 The Effects of Ageing on the Reliability and Performance of Integrated Circuits

49

pull-down equivalent transistors are equal to each other, and only the less conductive path between the output and Vdd or ground is considered to be active [18]. Assume that transistors always work in velocity saturation condition [32]. Considering (2.2 and 2.3), at time zero we can write: IDn0 = IDp0 ⇒   Keqn (VGSn − VTn0 ) = Keqp VSGp − VTp0 ,

(2.14)

where K eqn(p) = Weqn(p) Cox vsatn(p) . Considering the BTI-induced degradation ΔVth (t) and specialising (2.4) for the equivalent nMOS and pMOS transistors, it is: IDn (t) = ID0 − Keqn VTn (t)

(2.15)

IDp (t) = ID0 − Keqp VTp (t),

(2.16)

where the values of the transistor threshold voltage variations ΔVTp (t) = 2ΔVTn (t) can be calculated by means of (2.1), and Keqn ∼ = Keqp. As a result, it can be derived that it is always IDp (t) ≤ IDn (t), ∀ t > 0. Consequently, it is Gp (t) ≤ Gn (t), ∀ t > 0, where Gn (t) (Gp (t)) denotes the conductance of the nMOS (pMOS) transistors, as a function of time. Therefore, if a gate is sized to be symmetric at time zero, the worst-case condition to compute Qcrit is the case in which the output is driven by the pMOS pull-up network, independently of the considered kind of the gate and number of its inputs. As an example, Fig. 2.7 depicts the simulation results obtained when two alpha particles with the same energy hit the same node in a NOT chain. Two different operating times are considered: the beginning of the gate operating life (Fig. 2.7a) and after 10 years of operation (Fig. 2.7b) [18]. Results refer to the worst-case scenario, that is, when the node hit is driven by a pMOS transistor. As can be seen, even if the energy of the two hitting particles is the same, the glitch induced by the particle hit occurring after 10 years of circuit operation has a higher amplitude than the glitch induced at the beginning of circuit lifetime. This means that the Qcrit is considerably smaller after 10 years of circuit operation than at the beginning of circuit lifetime. In the following subsections, results on the BTI impact on the critical charge for several elementary gates are discussed in detail.

2.5.2.1

Symmetric, Minimum-Sized NOT Gate

Figure 2.8 shows the trend over time of the Qcrit at the output of a minimum-sized, symmetric inverter. It considers the case of a hitting particle temporarily charging (discharging) the output node, when it is driven by the pull-down (pull-up) network affected by PBTI (NBTI) degradation. As can be noticed, at time zero (non-aged

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Fig. 2.7 Simulation results for the case of an alpha particle hitting a node of a NOT chain: (a) at the beginning of circuit operation; (b) after 10 years of circuit operation [18]

Fig. 2.8 Critical charge of a NOT gate, as a function of circuit operating time

circuit) the Qcrit values are approximately the same, whether the pull-up (solid line) or the pull-down network (dashed line) is active. This is in accordance to the symmetric design of the NOT. As the circuit ages, the Qcrit obtained when the output is driven by the pMOS transistor decreases with a higher rate than when it is driven by the nMOS transistor. The relative difference in Vth reaches −9.3%

2 The Effects of Ageing on the Reliability and Performance of Integrated Circuits

51

Table 2.5 Critical charge (fC) for minimum-sized, symmetric gates with 2, 3 and 4 inputs Operating time 0 1 year 5 years 10 years

NAND 2 in NBTI PBTI 5.13 5.13 4.71 4.88 4.40 4.75 4.34 4.73

3 in NBTI 3.97 3.61 3.42 3.39

4 in PBTI NBTI 3.97 3.60 3.83 3.27 3.73 3.10 3.71 3.06

NOR 2 in 3 in 4 in PBTI NBTI PBTI NBTI PBTI NBTI PBTI 3.60 10.16 10.16 10.34 10.34 10.68 10.68 3.53 9.01 9.62 9.18 9.80 9.23 9.91 3.44 8.47 9.32 8.54 9.52 8.58 9.64 3.42 8.25 9.26 8.38 9.45 8.40 9.58

for t = 10 years. Therefore, as expected, the NBTI-induced Qcrit degradation is noticeably higher than PBTI, and the case of a node driven by the pull-up network is to be considered when a worst-case analysis is to be performed. We can observe that the value of Qcrit is a monotonic function, decreasing with circuit operating time; in addition, during the first 2–3 years of circuit operation, it decreases with a much higher rate than during the remaining circuit operating time.

2.5.2.2

Symmetric NOR and NAND Gates

Table 2.5 reports the values of the Qcrit at the output of minimum-sized, symmetric NAND and NOR gates with 2, 3 and 4 inputs, for several values of operating time, in case of both NBTI affecting the pull-up network and PBTI affecting the pull-down network, in the worst-case condition, as clarified in Sect. 2.5.2. In case of no degradation (t = 0), the Qcrit at the output of the NOR gate can be equivalently computed by considering the output driven by either the pull-up network or a single nMOS transistor of the pull-down network, since gates are symmetric in the worst-case condition; similarly, for the NAND gate, the critical charge can be equivalently evaluated by considering the output driven by a single pMOS transistor of the pull-up network. As the gates start ageing, the degradation of the pull-up network exceeds that of the pull-down, and so Qcrit (NBTI) < Qcrit (PBTI) for t > 0. In addition, it is interesting to observe that the relative difference between the critical charge values at t = 10 years and t = 0 also increases with the number of inputs and is much larger for NOR gates. For the latter, it ranges from −17.8% for a 2-input NOR to −21.3% for a 4-input NOR. This can be explained by considering that the number of pMOS series transistors increases with the number of inputs, thus giving rise to a cumulative degradation effect on Qcrit [18]. Finally, we can see that critical charge of minimum-sized symmetric NOR gates exceeds that of minimum-sized symmetric NAND gates. This might lead to the wrong conclusion that NOR gates are more robust to SE and ageing than NAND gates. In fact, the difference in Qcrit values reported in Table 2.5 depends on the chosen sizing of the two types of gate, and minimum-sized symmetric NANDs are considerably smaller than minimum-sized symmetric NORs. If the gate area

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is estimated in terms of squares (ϒ), where a square represents an area equal to 0.32 μm × 0.32 μm = 0.1024 μm2 , the following values can be derived [18]: ANOR−2 = 11.4ϒ; ANOR−3 = 24.3ϒ; ANOR−4 = 42ϒ ANAND−2 = 4.7ϒ; ANAND−3 = 6.2ϒ; ANAND−4 = 8.4ϒ

(2.17) (2.18)

For comparison purposes, we will now consider NAND and NOR gates with the same area. Figure 2.9 depicts the trend over time of the Qcrit at the output of NOR and NAND gates with 2, 3 and 4 inputs [18]. Only the worst-case scenario for Qcrit is considered, which is the case of the pull-up network. As can be seen, for all considered number of inputs, the Qcrit values obtained for the NAND gates are considerably higher than those for NOR gates of the same area. The relative difference slightly increases with time and with the number of inputs. It ranges from 1.4X at t = 0, for 2-input gates, to 2.3X at t = 10 years, for 4-input gates. Therefore, we can conclude that NAND gates, other than outperforming NOR gates of the same area and number of inputs, are considerably more robust against soft errors and BTI ageing effects.

Fig. 2.9 Worst-case Qcrit as a function of circuit operating time, for NANDs (dashed lines) and NORs (solid lines) having the same area, with (a) 2, (b) 3 and (c) 4 inputs

2 The Effects of Ageing on the Reliability and Performance of Integrated Circuits

2.5.2.3

53

BTI-Induced Soft Error Rate Variation

Consider a particle hitting a node j of a combinational circuit and generating a SET. To generate an SE, the SET must propagate up to a storage element m, satisfying its set-up and hold times. Therefore, the probability that an SE is generated is [43]: PSE,j m = Pgen,j Psens,j m Pprop,j m Platch,j m ,

(2.19)

where Pgen, j is the probability that a particle hitting the node j generates a collected charge higher than Qcrit,j , Psens, jm is the probability that the path between node j and the storage element m is sensitised by the input configuration, Pprop, jm is the probability that the glitch generated at node j arrives at the input of the storage element m with amplitude and duration large enough to be sampled and Platch, jm is the probability that the generated voltage glitch satisfies the set-up and hold times of the storage element and gets latched. The overall PSE can be written as: PSE =

 j

m

   PSE,j m = Pgen,j Psens,j m Pprop,j m Platch,j m . j

m

(2.20) It is worth noting that the probability Psens and Platch are not affected by BTI, thus they do not vary over time. As for the probability Pprop , it can slightly decrease with ageing, since the ability of a gate to propagate a voltage glitch depends on the gate conductance [44–46]. Therefore, in order to account for the impact of BTI on SER, we can focus our analysis on the generation probability only, which enables to determine the maximum impact of BTI on SE generation probability. For the node j, it is [40, 41]: γ Pgen,j (t) = kj φ e−σ Qcrit,j (t) , σ

(2.21)

where φ is a parameter depending on the alpha-particle flux, while γ and σ are fitting parameters. The parameter kj accounts for the probability that a particle impacting the considered circuit hits the critical area at node j, denoted by Aj . It is: kj = Aj /ATOT , where ATOT is the total area of the circuit, evaluated as the summation of the transistors’ gate and junction area. The parameter Aj is the critical area of the gate driving the node j. Particularly, when the pull-up network of the driver is ON, the critical area is the drain junction of the nMOS transistor in the OFF state connected to the output node of the gate. Similarly, when the pull-down is ON, the area of the drain junction of the pMOS transistor in the OFF state connected to the output node of the gate should be considered. Therefore, not only different critical charges, but also different critical areas must be accounted for when a generic node j is driven by the pull-up or pull-down network.

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Considering equal to 0.5 the probability that a generic node j is driven by the pull-up/pull-down network, the SET generation probability in (2.21) can be written as:   (p) 1 γ (p) −σ Q(n) (t) (n) −σ Qcrit,j (t) crit,j . (2.22) kj e Pgen,j (t) = φ + kj e 2 σ Therefore, the maximum SER relative variation induced by BTI during circuit lifetime (t > 0), with respect to its value at t = 0, is:

Pgen,j (t) − Pgen,j (0) j Pgen,j (0)   (p) (p) −σ Qcrit,j (t) −σ Qcrit,j (0) (n) e k − e

j

max SERmax (t) = PSE (t) = Pgen =

=

j (n) −σ Q(p) (0) crit,j kj e



(p)

+

kj

(n)

e

(p) −σ Q(n) crit,j (0)

+ kj e

−σ Qcrit,j (t)

j (n) −σ Q(p) (0) crit,j kj e

−e

(n)

−σ Qcrit,j (t)

(2.23) 

(p) −σ Q(n) crit,j (0)

.

+ kj e

In order to assess the variation of SE with circuit ageing, we have evaluated the Qcrit of the nodes of the benchmark circuit b02 from the itc’99 benchmark set [47]. Gates with different sizes have been considered, as highlighted in Fig. 2.10, as well as 1 year and 10 years of operating time. For each node, Qcrit and the critical area when the node is driven by either the pull-up or pull-down network are accounted for. The results presented in [18] are depicted in Fig. 2.11. In particular, in Fig. 2.11a we show the generation probability, normalised with respect to the coefficient φγ /σ that is not impacted by ageing: NPgen-pMOS represents the normalised generation probability obtained when the circuit nodes are driven by the pull-up networks, analogously for Pgen-nMOS and the pull-down network. NPgen-TOT represents the cumulative probability. The values of NPgen obtained at the beginning of circuit operating time, as well as after 1 year and 10 years of operating time have been depicted. As can be seen, NPgen-nMOS is always higher than NPgen-pMOS, also when ageing is considered. This is in contrast with the fact that the Qcrit decrease due to NBTI is considerably larger than that due to PBTI, as discussed in Sect. 2.5.2.2. However, in a symmetric gate, the critical area to be considered when the pull-up network is ON is usually smaller or equal than that to be considered when the pull-down network is ON. As a result, in (2.21), the contribution of the terms kj prevails over that of the exponential terms. Therefore, NPgen-nMOS turns out to exceed NPgen-pMOS for the whole circuit operating time.

2 The Effects of Ageing on the Reliability and Performance of Integrated Circuits

Out1 Q2 Q1 Q0

55

L3 L2 L1 L0

x1

x2

x2 x3

x2

x1

x1

x2

x1

x1

x2

x2

x1

x5

x1

x2

x3

x3

In1 x2

x1

x1

x1

Fig. 2.10 Circuit schematic for the ITC’99 b02 benchmark

Fig. 2.11 (a) Alpha-particle-induced voltage glitch generation probability; (b) SE probability relative variation

In Fig. 2.11b, we represent the relative variation of the soft error probabilities PSE = Pgen due to NBTI, PBTI and the total one, after 1 and 10 years of circuit operation, over the respective values at the beginning of circuit lifetime. As can be seen, PSE (TOT) reaches 11% after 1 year and exceeds 17% after 10 years of circuit operation.

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2.5.3 Analysis of the BTI Impact on SER in Storage Elements In Sect. 2.5.2, we he have assessed the effect of BTI ageing on the SER rate in combinational circuits, whose impact on circuit reliability increases with the scaling of technology and the consequent decrease in power supply and increase in operating frequencies. Nevertheless, it has been proven that SETs affecting storage elements (latches and flip-flops) are the major cause of soft SEs affecting sequential circuits [48, 49]. Therefore, it is of utmost importance to study how BTI ageing affects the soft error susceptibility of storage elements. In this section, we will focus on latches, since FFs can be designed by connecting two latches in a master–slave configuration. A comprehensive analysis of the impact of BTI in SER of latches has been presented in [19]. As discussed in [50], the soft error rate (SER) for a latch can be expressed by the sum of several contributions, each referred to a node of the latch. Considering the SET generation probability in (2.21), a simplified expression of the total SER for a latch is [50]: SER =

n

WOVi i=1

TCK

P ki e−β·Qcrit(i) ,

(2.24)

where i = 1 . . . n are the nodes of the latch that may produce an output SE if affected by a SET; WOVi is the window of vulnerability for node i, which is the time interval within a clock period (TCK ) during which a SET hitting node i can propagate till the output of the latch and give rise to a SE [50]; analogously to (2.21), ki is a constant proportional to the susceptible area of the node i (Ai ); P is the flux of hitting particles (P ∼ = 56.5/s·m2 at sea level [51]); and β is a parameter that depends on the considered technology and operating environment [50]. Due to their sensitivity to SEs, extensive research efforts have been devoted to devise novel design approaches for latches that are more robust against SEs. Robust latches can be divided into two categories, depending on adopted methodology to increase their robustness against SEs [19]. One category (hereinafter referred to as type 1) consists in latches that feature an increased capacitance of some of their nodes and/or driving strength of some transistors. This approach usually requires low area overhead, but does not guarantee complete immunity against SEs [19]. Latches proposed in [50, 52–54] belong to type 1. The second category of robust latches (hereinafter referred to as type 2) consists in latches whose robustness relies on proper modifications of their internal structure, which make them robust to SEs regardless of the hitting particle energy. Type 2 latches feature independent feedback loops to control the output, which in some cases is driven by a C-element [55, 56]. This way, a SET affecting one of the loops cannot result in an SE. Therefore, only SETs affecting the input node and satisfying the latch set-up and hold times can generate an SE. An example of type 2 latches are those proposed in [48, 56–59]. In this analysis, we consider the three latches depicted in Fig. 2.12: the standard latch [60] in Fig. 2.12a, the robust latch of type 1 [52] in Fig. 2.12b, and the robust

2 The Effects of Ageing on the Reliability and Performance of Integrated Circuits

57

Fig. 2.12 Schematic representation of the latches considered in our analysis: (a) standard latch, (b) robust latch of type 1 in [52], (c) robust latch of type 2 in [59]

latch of type 2 [59] in Fig. 2.12c. Nevertheless, the considerations that will be made will apply also to different latches of the same type. As shown in Sect. 2.5.2, critical charge Qcrit is affected by BTI ageing and decreases over time. According to (2.24), this makes the latch more susceptible to SEs as it ages. In addition, the WOV of some nodes can also be affected by BTI. Let us consider Table 2.6, which reports the susceptible nodes for the considered latches, that is, nodes that may generate an SE if they are affected by a SET, along with their respective WOVs and area of susceptible nodes. As can be seen, the WOV of all internal and output nodes is equal to half the clock period TCK , which is not affected by BTI. However, for input node D of all latches, WOV is equal to the set-up time tsu that, as will be clarified in the next section, increases over time due to BTI ageing. Therefore, in Sect. 2.5.3.1, impact of BTI ageing on the critical charge and set-up time is assessed in detail.

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Table 2.6 Window of vulnerability (WOV) and parameter k for the latches in Fig. 2.12

Latch Standard

Latch in [7]

Latch in [6]

Node D n1 n2 Q D n1 n2 n3 D

WOV tsu(std) TCK /2 TCK /2 TCK /2 tsu[52] TCK /2 TCK /2 TCK /2 tsu[59]

k AD = 9.22 × 10−15 m2 An1 = 9.22 × 10−15 m2 An2 = 3.07 × 10−15 m2 AQ = 3.07 × 10−15 m2 AD = 9.2 × 10−15 m2 An1 = 9.21 × 10−15 m2 An2 = 3.07 × 10−15 m2 An3 = 3.07 × 10−15 m2 AD = 1.23 × 10−14 m2

Table 2.7 Critical charge Qcrit (fC) for nodes of latches in Fig. 2.12 for different operating times and their relative variation Qcrit (%) over the values at time zero Latch t 0 1 year

Node Qcrit Qcrit Qcrit 3 years Qcrit Qcrit 6 years Qcrit Qcrit

2.5.3.1

Standard D n1 13.68 5.12 12.08 4.54 −11.7 −11.3 11.29 4.35 −17.5 −15.0 11.17 4.29 −18.3 −16.2

n2 8.55 7.93 −7.3 7.86 −8.1 7.81 −8.7

Q 10.53 9.83 −6.7 9.80 −6.9 9.77 −7.3

In [52] D 13.68 12.08 −11.7 11.29 −17.5 11.17 −18.3

n1 6.58 5.75 −12.7 5.59 −15.0 5.48 −16.7

n2 16.67 15.81 −5.1 15.65 −6.0 15.54 −6.7

n3 12.61 11.76 −6.7 11.62 −7.9 11.49 −8.9

In [59] D 14.01 11.97 −14.5 11.50 −17.8 11.34 −19.0

Impact of BTI Ageing on Latch Critical Charge and Set-Up Time

All latches in Fig. 2.12 have been simulated with HSPICE with a 32-nm high-k CMOS technology [29], with 1 V power supply, 1 GHz clock frequency, and with minimum transistor sizes guaranteeing a correct behaviour [19]. BTI degradation has been evaluated with the model in (2.1), considering an input probability of 0.5, with an operating time t ranging between 1, 3 and 6 years. Table 2.7 reports the Qcrit for all susceptible nodes, which has been determined considering their worst-case condition. As discussed in Sect. 2.5.2, this is represented by the case of the affected node driven by the pull-up network. Together with the critical charge values, Table 2.7 also reports (in boldface) the reduction of Qcrit for each node over the value exhibited at time zero [19]. We can see that, for all latches, the Qcrit of all nodes decreases rapidly during the early stage of the operating time. Particularly, it can be observed that, after only 1 year of operation, the Qcrit degradation exceeds 60% of the total degradation experienced after 6 years. It is worth noting that the Qcrit values of the nodes in the standard and robust latch in [52] are in accordance with the results reported in [40], which proved that the critical charge of a circuit node depends much more on the conductance of the

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gate driving the node (driving strength) than on the node capacitance. In fact, for the standard latch and for the robust latch in [52], the Qcrit of the input and output nodes is noticeably higher than that of the considered internal nodes. Indeed, the latter are driven by transfer gates, which exhibit a much lower strength than the gates driving input and output nodes. Moreover, we can also note that the Qcrit of input node D is slightly higher than that of output node Q. This is because although both nodes are driven by gates with the same conductance (minimum-sized inverter), the node capacitance associated with the input node D is slightly higher than that associated with output node Q, which for simulation purposes has been loaded by a minimumsized inverter [19]. As clarified in Sect. 2.5.3, the SER of latches depends linearly on the WOV of their nodes. Since tsu equals the WOV of latches’ input node, tsu variation due to BTI needs to be accounted for to characterise accurately how the SER of latches varies with circuit operating time. Particularly, for latches of type 2 as that in [59], an SE can be generated only as a consequence of a SET affecting their input node during tsu . Therefore, the variation of tsu over time directly influences SER for these latches. On the other hand, in the standard latch and in robust latches of type 1 as that in [52], the WOV of the input node (tsu ) is considerably smaller than the WOVs of all other nodes, which is generally equal to TCK /2, as shown in Table 2.6. As a result, the tsu variation over time will minimally affect the SER of these latches. Nevertheless, in order to avoid timing violations in aged circuits, tsu variation must be taken into account by designers, especially if the latches are connected to critical paths. Table 2.8 reports the tsu values of the considered latches for some representative circuit operating times (t = 0, 1, 3 and 6 years), together with the relative increase (in boldface) of the tsu of each latch over the value at time zero [19]. We can notice that tsu increases at a much higher rate during the first years of circuit operation than during the remaining circuit operating time. In particular, the increase after 1 year of operation approaches 60% of that exhibited after 6 years for the standard latch and the latch in [52]; this variation exceeds 51% for the latch in [59]. Table 2.8 Set-up time (ps) for latches in Fig. 2.12 for different operating times and their relative variation Qcrit (%) over the values at time 0

Latch t 0 1 year 3 years 6 years

Node tsu tsu tsu tsu tsu tsu tsu

Standard D 8.60 9.37 9.0 9.77 13.6 9.93 15.5

In [52] D 22.8 25.1 10.3 26.2 15.2 26.7 17.4

In [59] D 17.3 18.8 8.7 19.6 13.3 20.2 16.8

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Impact of BTI Ageing on Latch SER

We now evaluate the SER of the considered latches as a function of the circuit operating time. As shown in (2.24), the total SER is the sum of the contribution of all nodes that, if affected by an SET, may produce an SE. The expressions of the SER of the three latches analysed are reported in (2.25), (2.26) and (2.27) [19]. 

tsu(std) 1 AD e−β·Qcrit (D) + An1 e−β·Qcrit (n1) TCK 2  1 1 −β·Qcrit (n2) −β·Qcrit (Q) An2 e + + AQ e 2 2 tsu[52] 1 −β·Qcrit (D) = P AD e + An1 e−β·Qcrit (n1) TCK 2  1 1 −β·Qcrit (n2) −β·Qcrit (n3) An2 e + + An3 e 2 2 tsu[59] AD e−β·Qcrit (D) SER[59] = P TCK

SERStd = P

SER [52]

(2.25)

(2.26)

(2.27)

Table 2.6 reports the nodes i contributing to the SER of the considered latches, together with the expressions for the WOVi and parameter ki , which is proportional to the susceptible area of node i (Ai ). As highlighted in Sect. 2.5.3, for the flux of hitting particles, it is P ∼ = 56.5/s·m2 . Finally, for the considered 32-nm CMOS technology, the value of parameter β = 90 × 1012 1/C is derived from [41]. Figure 2.13 shows the trend over time of the SER for all the considered latches, obtained considering 0.5 input probability [19]. As expected, the SER increases with

Fig. 2.13 Values of the SER for the considered latches as a function of circuit operating time, with 0.5 input probability

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the operating time for all latches. During the first 2 years of operation, SER increase rate is much higher than during the remaining operating time. For all considered latches, after only 2 years, SER increase exceeds 90% of the total value exhibited after 6 years of operation. We can also observe that, during the whole circuit lifetime, the SER of the robust latch in [59] (type 2) is approximately one order of magnitude lower than the SER of the standard latch and the robust latches in [52] (type 1). Nonetheless, the SER of the robust latches in [52] and other latches of type 1 are all lower than the standard latch for the whole circuit operating time [19]. Moreover, over the circuit operating time, the SER increase experienced by the latch in [59] is negligible compared to that of the standard latch and the robust latch in [52]. This consideration applies to other latches of the two types, as discussed in detail in [19].

2.6 Conclusion Bias temperature instability (BTI) is recognised as the primary parametric failure mechanism in modern ICs. The main effect of BTI is to increase the threshold voltage of MOS transistors, thus degrading their dynamic characteristics. As a result, circuit performance can degrade noticeably over time, possibly leading to the violation of the circuit timing constraints, with a consequent circuit malfunction and reduced lifetime. Therefore, it is of utmost importance to assess the impact of BTI on circuit performance and reliability. This chapter addresses this important aspect, which has to be considered for the design of reliable ICs. Particularly, the impact of BTI on the propagation delay of logic gates is discussed in detail, and a methodology to embed the effective BTI degradation within a standard electrical-level simulation flow is presented. Since BTI depends critically on the stress ratio of transistors, an approach to accurately estimate this important parameter at design time is presented, which leads to design consideration about the most ageing resilient circuits. Besides BTI, the increase of soft errors generated by energetic particles is generating great concern among designers of nanometre ICs. Since IC susceptibility to soft errors is aggravated by BTI, this chapter also focuses on the estimation of SER increase due to BTI for both combinational circuits and storage elements. It is shown that NAND and NOR gates exhibit a very dissimilar resiliency to BTI ageing, with the NAND being less prone to BTI-induced degradation. Therefore, NAND gates must be favoured when soft error resilience of combinational logic is of concern. In addition, storage elements featuring a high robustness against SEs are demonstrated to degrade over time due to BTI. Consequently, an accurate estimation of BTI ageing is mandatory also when IC designers are targeting applications that need to feature high robustness against soft errors.

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References 1. Kang, K., Park, S. P., Roy, K., & Alam, M. A. (2007). Estimation of statistical variation in temporal NBTI degradation and its impact on lifetime circuit performance. In: 2007 IEEE/ACM international conference on computer-aided design (pp. 730–734). San Jose, CA. 2. Chandra, V.(2014, June). Monitoring reliability in embedded processors – A multilayer view. In: Design automation conference (DAC) (pp. 1–6). 3. Henkel, J., Bauer, L., Zhang, H., Rehman, S. & Shafique, M.(2014). Multi-layer dependability: From microarchitecture to application level. In: 2014 51st ACM/EDAC/IEEE design automation conference (DAC) (pp. 1–6). San Francisco, CA. 4. Alam, M. A., Kufluoglua, H., Varghese, D., & Mahapatra, S. (2007). A comprehensive model for PMOS NBTI degradation: Recent progress. Microelectronics Reliability, 47(6), 853–862. 5. Joshi, K., Mukhopadhyay, S., Goel, N. & Mahapatra, S. (2012). A consistent physical framework for N and P BTI in HKMG MOSFETs. 2012 IEEE international reliability physics symposium (IRPS) (pp. 5A.3.1–5A.3.10). Anaheim, CA. 6. Liu, C., Kochte, M. A., & Wunderlich, H. J.(2015, July). Efficient observation point selection for aging monitoring. In: On-line testing symposium (IOLTS), 2015 IEEE 21st international (pp. 176–181). 7. Agarwal, M., Paul, B. C., Zhang, M., & Mitra, S. Circuit failure prediction and its application to transistor aging. In: Proceedings of IEEE VLSI test symposium (pp. 277–286). 8. Wang, W., Wei, Z., Yang, S., & Cao, Y. An efficient method to identify critical gates under circuit aging. In: Proceedings of IEEE/ACM international conference on computer-aided design (pp. 735–740). 9. Vazquez, J. C., Champac, V., Ziesemer, A. M., Reis, R., Semiao, J., & Teixeira, I. C. Predictive error detection by on-line aging monitoring. In: Proceedings of IEEE international on-line testing symposium (pp. 9–14). 10. Baranowski, R., Firouzi, F., Kiamehr, S., Liu, C., Tahoori, M., & Wunderlich, H. (2015). Online prediction of NBTI-induced aging rates. In 2015 Design, automation & test in Europe conference & exhibition (pp. 589–592). Grenoble: DATE. 11. Chahal, H., Tenentes, V., Rossi, D., & Al-Hashimi, B. M. BTI aware thermal management for reliable DVFS designs. In Proceeding of 29th IEEE symposium on defect and fault tolerance in VLSI and nanotechnology systems (pp. 1–6). Connecticut: The University of Connecticut in Storrs. 12. Baumann, R. C. (2005). Radiation-induced soft-errors in advanced semiconductor technologies. IEEE Transactions on Device and Materials Reliability, 5(3), 305–316. 13. Seifert, N., Gill, B., Zia, V., Zhang, M., & Ambrose, V. (2007). On the scalability of redundancy based SER mitigation schemes. In: Proceedings of international conference on integrated circuit design and technology. 14. Cannon, E. H., Klein Osowski, A., Kanj, R., Reinhardt, D. D., & Joshi, R. V. (2008). The impact of aging effects and manufacturing variation on SRAM soft-error rate. IEEE Transactions on Device and Materials Reliability, 8(1), 145–152. 15. Ramakrishnan, K., Rajaraman, R., Suresh, S., Vijaykrishnan, N., Xie, Y., & Irwin, M. J. Variation impact on SER of combinational circuits. In: Proceedings of international symposium on quality electronic design (pp. 911–916). 16. Rossi, D., Omaña, M., Metra, C., & Paccagnella, A. (2011). Impact of aging phenomena on soft error susceptibility. In: Proceedings of IEEE international symposium on defect and fault tolerance in VLSI and nanotechnology systems (pp. 18–24). 17. Harada, R., Mitsuyama, Y., Hashimoto, M., & Onoye, T. (2013). Impact of NBTI-induced pulse-width modulation on SET pulse-width measurement. IEEE Transactions on Nuclear Science, 60(4), 2630–2634. 18. Rossi, D., Omaña, M., Metra, C., & Paccagnella, A. (2015). Impact of Bias temperature instability on soft error susceptibility. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 23(4), 743–751.

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Part II

Ageing Mitigation Techniques

Chapter 3

Aging Mitigation Techniques for Microprocessors Using Anti-aging Software Haider Muhi Abbas, Mark Zwolinski, and Basel Halak

3.1 Introduction The combinational logic circuits need to be actively relaxed to recover from aging stress, rather than simply doing nothing during idle periods. In recent applications, processors tend to have many short idle periods; thus, simple power gating would not be a good solution for stress optimization [1]. During normal operational periods, the input states of the transistors may be constant, leaving the transistors stressed. NBTI/PBTI could then be reduced by applying balanced stress stimuli to the critical paths at the software level. Running a program on the processor for a non-functional purpose has been used in on-line testing (i.e. software-based self-test (SBST) methods) as this does not require modification of the hardware design [2]. The main objective of this chapter is to design a high-level technologyindependent mitigation technique to balance NBTI/PBTI effects on the combinational part of the processor. This technique brings the circuit into a balanced aging state by changing the nodes that are BTI-stressed to BTI-relaxed.

H. M. Abbas Control and Systems Engineering Department, University of Technology, Baghdad, Iraq e-mail: [email protected] M. Zwolinski · B. Halak The School of Electronics and Computer Science, University of Southampton, Southampton, UK e-mail: [email protected] © Springer Nature Switzerland AG 2020 B. Halak, Ageing of Integrated Circuits, https://doi.org/10.1007/978-3-030-23781-3_3

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3.2 Chapter Overview The organization of this chapter is as follows. In Sect. 3.3, the definition of the stress state according to the NBTI effect has been defined. In Sect. 3.4, the dependency of the data on stressing the processor is discussed. In Sect. 3.5, NBTI/PBTI analysis is presented. The proposed technique for generating and applying the balancing patterns is presented in Sect. 3.6. The evaluation and discussion of running the balancing program are given in Sect. 3.7. Section 3.8 concludes the chapter.

3.3 Signal Probability The signal probability is the ratio of signal node at the gate level being active (ON or “1”) to the total period (ON plus OFF) [3]. Meanwhile, the probability of a signal being zero, SP(0), or the signal probability, reflects the fraction of time spent in the stress state (OFF or “0”, from NBTI perspective). The duty cycle can be defined as [4]: SP(1) =

PW × 100%, T

where SP(1) is the duty cycle in percentage, PW is the pulse width and T is the total period of the cycle (see the Fig. 3.1). The signal probability of the signal being zero (SP(0)) can be defined as: SP(0) = 1 − SP(1) NBTI effects on PMOS transistors

VDD

PW

‘1’

PMOS (ON) NMOS (OFF) NBTI

‘0’

PMOS (OFF) NMOS (ON) PBTI

PMOS IN

OUT

NMOS T

PBTI effects on NMOStransistors

GND

Fig. 3.1 The stress condition on inverter logic gate which if the input signal (IN) is “1”, the pull-up transistor (PMOS) would be stressed with NBTI but if the input signal (IN) is “0”, the pull-down transistor (NMOS) would be stressed with PBTI. These stress periods are defined by the pulse’s width (PW) and the period (T)

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3.4 High-Level Data Control of Aging The data processed by programs determines whether the nodes of the processor are stressed or not. The data includes both opcodes and operands. Firouzi et al. [5] looked at possible NOP instructions in the MIPS processor to reduce aging, as well as the standard NOP instruction (sll r0, r0, 0) considering other instructions that had no result (e.g. adding zero) to minimize stress. They proposed software and hardware techniques to assign the best-input vector for these NOP instructions. This method would only be helpful, however, if the rate of NOP instructions is high with respect to the total number of operational instructions. To test this hypothesis, we ran different benchmarks from the MiBench suite [6] for two different architectures on the GEM5 simulator [7]. Figure 3.2 shows that the number of NOP instructions on the MIPS processor is significant, while on the ARM architecture it is negligible. Data coming from other paths can also stress the critical path. For example, let us assume that the adder is in the critical path, and that during the execution of other operations data is routed to the adder, even though the result is not used. From a BTI perspective the critical path through the adder will be stressed. It has been claimed that the core of a processor can be brought to a failing state by executing a malicious program to age the circuit [8]; however, this does not consider the signal probabilities of intermediate nodes. In practice, it is not possible to put all critical path nodes into a fully relaxed state (i.e. a signal probability of zero, SP(0) = 0%) or a fully stressed state (SP(0) = 100%) as illustrated in Fig. 3.3. On the other hand, it is possible to balance the stress by controlling the signal probabilities during the idle time of the processor.

MIPS

crc32 patricia dijkstra qsort

ARM

crc32 patricia dijkstra qsort 0.00% No_Op

IntAlu

20.00% IntMult

40.00% IntDiv

FloatAdd

60.00% FloatMisc

80.00% MemRead

100.00% MemWrite

Fig. 3.2 Instruction classification percentages of different benchmarks running on MIPS and ARM

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AO22X1

AO221X1 94% 1%

NBUFFX2

Critical Path

99% 94%

(99% ; 0%) 99% 99%

(99% ; 0%)

0% (99% ; 0%)

(93% ; 0%)

A complement signal probabilities of beingzero(SP(0)) inside intermediate nodes of the logic gates

(Normal SP(0) ; Reversed SP(0))

Fig. 3.3 Zero-signal probabilities distribution on the critical path sub-circuit with normal and reversed state

3.5 BTI Stress Analysis 3.5.1 BTI-Critical Path Selection The selection of paths to reverse the stress needs to consider both the initial path delays from the post-synthesis analysis and the gate types in the paths. A noncritical path at time zero could become a critical path after a number of years because paths degrade according to different factors, for example, duty cycle, temperature, frequency and circuit topology. Estimating the path most sensitive to aging depends on model parameters that would not be available until the system has been fabricated and tested in the target environment. Therefore, in this research, we have avoided using an aging model to define the criteria for selecting specific paths that are potentially vulnerable to aging. Instead, we define a threshold (θ ) for the agingcritical path delay. For example, the maximum critical path degradation has been measured by creating aging-aware gate model for different benchmark circuits (ISCAS85) for 10 years and we found that the path delay increases for these circuits are between 12.3% and 19.5% [9]. Thus, we can define aging-sensitive critical paths as those paths that have slack in the range of zero to (δ 0 × θ ), inclusive, or have a path delay between δ 0 and δ 0 (1 − θ ), inclusive, where δ 0 is the slack of the path at time zero that could be found using static timing analysis tools (e.g. Design Compiler). We also consider the effect of process variations on selected paths by defining the worst-case possible path deviation due to the process variations as Δδpv. Then, an aging- and process-sensitive critical path should be selected if its path delay is in the range:   δ0 ≥ Path Delay ≥ δ0 1 − θ − δpv

(3.1)

These paths have nearly balanced path delays, but they could share instances of gates with the first critical path (e.g. in an adder, if the carry chain path is shared

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between nearly critical paths and the first critical path, then any degradation or reversed degradation on the shared part will also affect the aging-sensitive critical paths). Alternatively, if the critical paths have instances that are independent from one path to another, then all the aging-sensitive critical paths need to be analysed individually for aging and possible reversal.

3.5.2 SP(0) Distribution on the Critical Paths of the Processor Combinational logic circuits may show different degradations in each PMOS transistor because different primary input patterns can lead to different inputs to the CMOS transistors. Some PMOS transistors may degrade more because they have SP(0) of 99%, but others may not degrade if they have SP(0) of 1% at their gates. To date, however, there has been no consideration of SP(0) of the intermediate nodes of the complex gates. For example, in [8, 10], the analysis was done only for the input transistors of the gates. In the OR gate of Fig. 3.4, if IN1 is at “1”, Q would be “1” regardless of IN2, but there is a node, QN, inside the OR gate that would be stressed. To measure the delay degradation on each net of the critical path, we need to consider the SP(0) of each input and of the internal nodes of the gate cells. We used the OpenRISC core for this analysis. Firstly, synthesis has been done using Synopsys Design Compiler with the full set of cells available in the 90 nm Synopsys

VDD

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Fig. 3.4 A CMOS circuit for an OR gate

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library, including those cells that have internal nodes. There are 2888 critical paths in the OpenRISC core, but various critical paths pass though the same gate cells. For example, the first 100 critical paths share more than 92% of the cells in the most critical path (see Table 3.1). Thus, if there were any degradation in the shared part, it would affect all these critical paths. Moreover, the average SP (0) for the first 100 critical paths is around 80% when executing a “Hello World” program. This means that the program will stress the critical path. In this example, the nodes are totally NBTI stressed because the probabilities of signals being zero are close to 100%. However, this does not consider the hidden nodes of the compound gates and so the average SP(0) is not correct. These hidden nodes would have complementary values and therefore have no NBTI stress but could have PBTI stress. In other words, a circuit with SP(0) close to 0% could have hidden nodes with SP(0) close to 100%. To calculate a more accurate figure, we ran different instructions on a processor synthesized using only cells that have only one level of transistors, in order to avoid any hidden nodes, as given in Tables 3.2 and 3.3. The SP(0) at each node is generally the complement of the SP(0) of the previous node and the average SP(0) is around 50%. Therefore, the objective should be to reverse these signal probabilities to obtain signal probabilities that are as balanced as possible (around 50%), rather than reducing one signal probability to avoid NBTI stress. This example is only used to show the signal probabilities of the hidden nodes, as this case is not feasible in real synthesis.

3.5.3 Impact of Instruction/Program-Level Workload on the Stress Probabilities To study the effect of different instructions on the stress of the critical or nearly critical paths, we ran two different instructions with four different operands each, to determine whether the opcode or the data have a significant impact. The synthesis is done using only cells that have no hidden nodes. The SP (0) at each node is generally the inverse of that of the previous node in the path. For the 155 nodes in the critical path, the average SP(0) was around 50%, as can be seen from the symmetry of the histograms in Fig. 3.5. The average SP(0) of the paths does not change significantly with the opcodes or operands. However, the signal probability distributions on the critical path do depend on the opcode and operands, as shown in Fig. 3.5(“movhi rD,5555 H”), where the signal probabilities tend to the extremes (10% > SP(0) > 90%) even with symmetrical distributions that stress the critical paths with both NBTI and PBTI. Moreover, when the specific patterns do a change in some limited number of nodes, again that will be inverted in other nodes and the average SP(0) will not be affected. We run different benchmarks from the MiBench benchmarks to illustrate how different programs stress different PMOS transistors in the critical path or nearly critical paths. As can be seen in Tables 3.4 and 3.5, although different benchmarks have been executed, the SP(0)

93 93 93 94 5 94 93 99 99 99 83

AO22X1 OR2X1 AO22X1 XOR3X1 AOI22X1 NAND4X0 AO221X1 NBUFFX2 AO22X1 DFFX1

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Cell type (%) SP(0)Cell type (%) SP(0) (%) 150 DFFX1 50 198 DFFX1 98

1st critical path 2nd critical path 3rd critical path 10th critical path 100th critical path Cell type (%) SP(0) Cell type (%) SP(0) Cell type (%) SP(0) 1 DFFX1 50 DFFX1 50 DFFX1 50 DFFX 2 DFFX1 98 DFFX1 98 DFFX1 98 DFFX

Table 3.1 SP(0) distribution on the critical paths of the OpenRISC processor for Hello World program using compound gates

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.. .

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.. .

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Table 3.2 SP(0) distribution on the 100th critical path of the OpenRISC processor for different instructions

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Cell type 1DFFX1 DFFX1 NAND2X0 NAND2X0 NAND2X0 NAND4X0 NOR2X0 AOBUFX1

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Table 3.3 SP(0) distribution on the first critical path of the OpenRISC processor for different instructions

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addi rD,rA,0000_H

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0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 SP(0) bins

Fig. 3.5 SP(0) distribution on the first critical path of the OpenRISC processor for different instructions

on the specific nodes did not change significantly. Similarly, different MiBench benchmarks show nearly symmetrical average stress, as can be seen in Fig. 3.6. Therefore, it would be desirable to reduce the number of nodes at the extremes of these histograms (e.g. 25% > SP(0)>75%). Hence, we conclude that a single instruction or program will not relax or stress 100% of the critical paths, but that a program-level solution could relax or stress some specific nodes. In other words, if there are some nodes in the processor that could face a continual stress while others are not stressed, it is possible to balance that effect at the application level.

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Table 3.4 SP(0) distribution on the first critical path of the OpenRISC processor for different programs 1 2 3 4 5 6 7 8 9

Cell type DFFX1 DFFX1 NAND2X0 NAND2X0 NAND2X0 NAND4X0 NOR2X0 AOBUFX1 INVX0

Hello World (%) 50 48 22 42 40 30 75 75 24

bit cnts (%) 50 47 24 45 39 29 76 76 23

Basic math (%) 50 41 20 39 34 28 76 76 23

jpeg (%) 50 47 24 45 39 29 76 76 23

..

..

..

..

..

..

36 36 45

28 28 45

25 25 45

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154 NAND2X0 155 DFFX1 Average SP(0)

Table 3.5 SP(0) distribution on the 100th critical path of the OpenRISC processor for different programs 1 2 3 4 5 6 7 8 9

Cell type DFFX1 DFFX1 NAND2X0 NAND2X0 NAND2X0 NAND4X0 NOR2X0 AOBUFX1 INVX0

Hello World (%) 50 48 22 42 40 30 75 75 24

bit cnts (%) 50 47 24 45 39 29 76 76 23

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jpeg (%) 50 47 24 45 39 29 76 76 23

..

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142 NAND2X0 143 NAND4X0 Average SP(0)

3.5.4 Gate-Level Stress Balancing We consider balancing the signal state of basic logic gates (inverter, NAND and NOR) compared with inverting the signal probability. We will examine how inverting the signal probability would affect the aging degradation. We have used HSPICE for simulating path delays and modelled the NBTI using MOSRA Level 3

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SP(0) bins

Fig. 3.6 SP(0) distribution on the first critical path of the OpenRISC processor for different programs

considering two different cases: • CASE A: Unbalanced stressed nodes – the nodes of the critical paths are either significantly NBTI-stressed (SP(0) greater than 75%) or significantly NBTIunstressed (or PBTI-stressed) (SP(0) less than 25%). • CASE B: Balanced stressed nodes – the nodes of the critical path have SP(0) around 50%. For the inverter, we simulated the degradation of a path of two inverters over 6 years using the cases discussed above. The results show an advantage of 23.17% in the path delay and more than 50% in terms of time as shown in Fig. 3.7. For NAND and NOR gates, the same simulation as for the inverter is implemented. However, we consider two additional dependencies: the signal probabilities of the secondary inputs of the gates and the input pin order. The results show that swapping input pins could decrease the advantage obtained from balancing the signal probabilities. In addition, the signal probabilities of the secondary input of the gate will not significantly affect the benefits of balancing the signal probabilities over the critical path (Tables 3.6 and 3.7). We also considered how the balanced stress patterns affect the remaining paths of the circuit. To answer this fundamental question, we examined the proposed technique on a two-bit adder. In this example, there are one target critical path and

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Table 3.6 Path delay degradation advantages for a chain of two NAND2 gates considering balanced and unbalanced signal probabilities SP(0) of degradation path (%) 50 50 99 99 1 1

Swap input order NO YES NO YES NO YES

CASE A degradation (%) 9.27 9.49 7.35 8.50 10.38 10.46

CASE B degradation (%) 7.25 7.62 5.82 6.88 8.34 8.18

Advantage over delay (%) 21.75 19.73 20.80 19.10 19.69 21.82

Advantage over years (years) 6 5 5 5 5 5

Table 3.7 Path delay degradation advantages for a chain of two NOR2 considering balanced and unbalanced signal probabilities SP(0) of the second input (%) 50 50 99 99 1 1

Swap input order NO YES NO YES NO YES

CASE A degradation (%) 8.55 9.10 8.55 9.76 5.83 7.38

CASE B degradation path (%) 6.81 7.57 6.81 8.77 4.54 5.68

Advantage over delay (%) 20.35 16.80 20.35 10.18 22.08 23.08

Advantage over years (years) 5 4 5 3 6 3

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A[1] B[1]

Crical Path 3

SUM[0]

Crical Path 1

SUM[1] Crical Path 2

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Fig. 3.8 The three most critical paths in the two-bit adder

two nearly critical paths as shown in Fig. 3.8. In this example, we extracted the critical paths list after synthesizing the circuit using Design Compiler. Again, we used the MOSRA Level 3 model in HSPICE simulations to model the degradation of the circuit using the two above-mentioned cases. The results show that for all paths, there will be an advantage of up to 50% in the expected lifetime from balancing the signal probabilities in the critical path (see Fig. 3.9). Figure 3.9 also shows that nearly critical paths share more than half of their nodes with the target critical path. Thus, any advantage in balancing the signal probabilities of the critical path will lead to an advantage in the remaining paths. If the nearly critical paths do not share nodes with the critical path, then it is possible to control both the critical and the nearly critical paths in parallel.

3.6 Proposed Technique The proposal consists of two steps technique to mitigate the BTI aging effects. In the first step, anti-aging patterns (the balanced states) are generated, and these patterns are applied in the second step by executing a stress-relief program instead of running a process idle task. The flow of the first phase of the proposed techniques is illustrated in Fig. 3.10. Providing the hardware description of the processor, we can generate the netlist/gate-level design using specific technology node and synthesis

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Reliability time(Years) Fig. 3.9 Path delay degradation of the most three critical paths in the two-bit adder considering unbalanced and balanced signal probabilities over the critical path

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Fig. 3.10 Generating flow of BTI balanced stress patterns

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tool (e.g. Design Compiler). Post-synthesis simulation is required to extract the VCD file by executing program in the simulated processor using, for example, ModelSim simulation tool. The VCD file needs to be parsed and translated into SP(0) file. The static timing analysis tool is needed to extract the timing-critical paths. These paths need to be classified to obtain only potential critical paths as presented in Sect. 3.5.1. After obtaining both the potential critical paths and their signal probability, the stress state could be obtained for the nodes that have unbalanced SP(0). This stress state needs to be reversed to obtain the reverse stress state (balance state). Finally, ATPG (Automatic Test Pattern Generator) Tool is required to obtain patterns that are able to propagate the reverse stress state into the stressed nodes at the gate level. We find the normal states (i.e. the critical path stress states) of the nodes that need to be balanced by running different benchmarks and instructions. We obtain the signal probabilities of the nets being stressed to logic zero (SP(0)) from gate-level simulations of the processor executing benchmarks. We calculate the SP(0) of the critical paths that have slacks less than the predefined maximum path delay degradation. The second phase of the technique is to balance the effect of BTI by reversing the average signal probabilities by applying stress-relaxing patterns to the timingcritical components in the functional unit of the processor during idle states.

3.6.1 Case Study: Application-Level BTI Balancing We synthesized an OpenRISC 1200 processor core using the 90 nm Synopsys technology.1 The VCD file from each post-synthesis simulation contains both the switching activity, which is used to estimate the dynamic power at the design phase, and the signal probability that we used to estimate the BTI effect on performance degradation. From the VCD file, we extracted the SP(0)for all the nets of the processor. To balance the effect of signal probability on the critical path, we need to find input patterns that will invert the signal states. This is effectively the same as generating test patterns for single-stuck faults. We used an ATPG tool (e.g. TetraMAX from Synopsys) to find test patterns for stuck-at-0 faults on nets that have high SP(0) so as to set those nets to “1”. Similarly, we generated patterns for stuck-at-1 faults on the nets that have low SP(0) so as to set those nets to “0”. Thus, these logic-level nodes that are stressed by “0” (NBTI) or “1” (PBTI) could be reversed by applying reversed stress patterns. The critical paths of the OpenRISC 1200 processor are in the adder. Thirty-eight nodes have an SP(0) greater than 75%; 10 nodes have an SP(0) less than 25%. The ATPG tool found eight test patterns to set these nodes to balanced stress conditions.

1 The technology is not important because the technique depends on reversing the SP(0) rather than

estimating the aging. Hence, it is also independent of the BTI model.

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Each pattern will apply balanced stress to one or more nodes, while the full set is needed for every node. As what the results given in Sect. 3.7 have shown, the percentages of stressed nodes will be reduced significantly after applying these patterns. Table 3.8 shows these patterns as they would be applied to inputs A [31. 0] and B [31.0.0] of the adder. The OpenRISC 1200 instruction set architecture has only a 16-bit immediate mode. These balanced stress patterns have 32-bit widths and so are stored in consecutive memory locations starting with address K. The “balancing” program shown in Fig. 3.11 transfers K (immediate value) to register r 1 for use as an offset address. Then, two patterns are loaded from memory to registers 2 and 3. The two patterns are applied to the adder with an ADD operation. The same sequence is applied for the remaining patterns. The program runs in a loop during the idle states of the system. Further optimizations are possible to the above program to reduce the memory access and thus to reduce the power consumption of the running program as shown in Fig. 3.12. Table 3.8 Balanced stress patterns for OpenRISC processor

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

l. movhi r1, K # Stimulate the first pattern l. lws r2, 0(r1) l. lws r3, 1(r1) l. add r4, r2, r3 # Stimulate the second pattern l. lws r2, 2(r1) l. lws r3, 3(r1) l. add r4, r2, r3 . . # Stimulate the eighth pattern l. lws r2, 14(r1) l. lws r3, 15(r1) l. add r4, r2, r3 l. rfe # Return From Exception

Fig. 3.11 The balancing program

A[31:0] 48 CB 24 65 DA F9 25 B7 DE 4F BF 58 67 5B AC 8C

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# Stimulate the first pattern l. movhi r2, 48CB l. ori r2, r2, 3E67 l. movhi r3, D440 l. ori r3, r3, 7A4C l. add r4, r2, r3 # Stimulate the second pattern l. movhi r2, 2465 l. ori r2, r2, 9F2D l. movhi r3, EA20 l. ori r3, r3, 3D3C l. add r4, r2, r3 . . # Stimulate the eighth pattern l. movhi r2, AC8C l. ori r2, r2, 0318 l. movhi r3, A4DC l. ori r3, r3, 938D l. add r4, r2, r3 l. rfe # Return From Exception

Fig. 3.12 Optimized balancing program

Another consideration is that this program may not have the privileges to run while another program is running. Therefore, the scheduler should give the lowest priority to this program and run it when the system is idle. However, if it is decided that this program should run as a routine in response to an interrupt, then the context of interrupted processes needs to be saved. In this case, the program should push the registers onto the stack at the start of the routine and pop them off at the end of the routine to save the context of the interrupted program as shown in Fig. 3.13.

3.7 Evaluation and Discussion To evaluate the effectiveness of running the balancing program, we ran the balancing program along with different benchmarks and varied the percentages of the running time of the balancing from 10% to 50%. To compare results, we calculated the number of stressed nodes as follows: Percentage of stressed nodes =

#stressed nodes , critical path nodes

(3.2)

where the stressed nodes are those critical path nodes that have an SP(0) greater than 75% or less than 25%. As would be expected, to obtain a balanced state for the

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# Push r2, r3, r4 onto the stack push {r2−r4} # Stimulate the first pattern l. movhi r2, 48CB l. ori r2, r2, 3E67 l. movhi r3, D440 l. ori r3, r3, 7A4C l. add r4, r2, r3 # Stimulate the second pattern l. movhi r2, 2465 l. ori r2, r2, 9F2D l. movhi r3, EA20 l. ori r3, r3, 3D3C l. add r4, r2, r3| . . # Stimulate the eighth pattern l. movhi r2, AC8C l. ori r2, r2, 0318 l. movhi r3, A4DC l. ori r3, r3, 938D l. add r4, r2, r3 # Pop r2, r3, r4 and the program counter (pc) from the stack, then branch to the new pc. pop {r2−r4, pc}

Fig. 3.13 Optimized balancing program for saving the context of the interrupted program

stressed nodes requires the balancing program to run for 50% of the time. It is not always possible to have this idle time or to add redundant time for relaxing BTI. Figure 3.14 shows the effect on the stressed nodes of running the BTI-balancing program for different percentages of the overall time. Figure 3.15 shows the effect of running the BTI-balancing program for different times on the percentages of the stressed nodes in critical paths of the OpenRISC processor. The results show that balancing one critical path will balance other nearly critical paths as they share nodes with the first path. On the other hand, if the nearly critical paths do not share many nodes with the targeted critical path, it is possible to apply balancing patterns in the same way for the first critical path independently of the other paths. Although balancing signal probabilities would work with embedded systems that run specific applications, it is also possible to use the technique for a general-purpose processor. Figure 3.16 shows how the percentages of stressed nodes on the first critical path of the OpenRISC processor are reduced when executing the balancing program along with a different program from the MiBench benchmarks. Next, to verify that the balancing program will reduce the degradation in the path delay of the processor, we simulated the adder using HSPICE and modelled NBTI using the MOSRA Level 3. We stimulated the circuit with two cases:

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Redundant time (Time overhead to run anti-aging program along with the functional program) Fig. 3.14 The effect on the stressed node percentage of running the BTI-balancing program along with a “Hello World” program with different run times of the balancing program

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Fig. 3.15 The effect of running the BTI-balancing program along with a “Hello World” program on the stressed node percentage on different critical paths of the OpenRISC processor with various run times of the balancing (anti-aging) program

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Fig. 3.16 The effect of running BTI-balancing program along with a different program from MiBench benchmarks on the stressed node percentage on the first critical path of the OpenRISC processor with different run times of the balancing program

• CASE A (normal stressed mode): Stress patterns with the equivalent signal probabilities of the Hello World program • CASE B (balanced mode): Balanced stressed nodes (i.e. the nodes in the critical path having an SP(0) around 50% by running the anti-aging program along with the normal stressed mode program) The results show that running the balancing program would decrease the path delay by 20.24% compared with the normal operation and will double the expected lifetime as shown in Fig. 3.17.

3.7.1 Discussion In our analysis, we expect, for example, 11% degradation in 6 years as can be seen in Fig. 3.17, so a simple solution could be guard banding. Guard banding is inevitable, not only for aging but also for PVT variations. However, adding more guard banding would negate the advantage of using a smaller technology. So we have to find an active protective approach that will also estimate, sense and react to degradations.

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The idea of this work in this chapter is to utilize the short idle periods in a processor [1] to reverse the BTI stress rather than running empty loops. In our case study of the OpenRISC processor, the critical paths are in the adder and we can propagate patterns simply by loading the patterns into a register and executing an addition operation. This program replaces the idle task and is executed whenever the operating system tries to schedule the idle task. In general, if the timing-critical component is not the adder, then we have to replace the operation accordingly. If the critical paths are not controllable at the instruction level (e.g. in a control unit that may have many flip-flops), then we need an architectural solution rather than a software solution to propagate the patterns. We also need to consider how process variations could affect the critical path ranking. If we get this wrong, we might heal a non-critical path and leave the real critical path unaffected. For this reason, we have to consider not only the critical path but also the nearly critical paths that could become critical with PVT and timedependent variations. In our case study, we have predefined (θ + Δδpv) to be 20% of the maximum path delay at time zero (δ 0 ), as described in Sect. 3.5.1, which covers the first 100 critical paths. However, we found that the first 100 critical paths share more than 92% of the cells with the most critical path. Thus, balancing the most critical path also balances the nearly critical paths. However, if the nearly critical paths do not share a big percentage of their cells with the first path, then we have to consider every single path in our analysis and generate patterns for them to balance signal probabilities in parallel. Therefore, even with process variations, this technique would target the nearly critical paths. If the nearly critical paths do not share cells with the most

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critical path, it is important to define a threshold that considers the process and aging variation contributions and to control these paths in parallel.

3.8 Conclusion An application-specific high-level BTI analysis has been carried out to find a method for CMOS aging mitigation. A cross-layer mitigation technique has been proposed to apply stress-relaxing patterns to the critical paths of a functional unit of a processor during idle times. This chapter presented technique using the processor BTI-balancing programs (anti-aging) to mitigate the BTI aging effects. This technique generates balancing patterns and applies these patterns by executing a program to balance the stress on the critical paths of the combinational part of the processor to alleviate BTI effects instead of running an empty process idle task.

References 1. Arora, M., Manne, S., Paul, I., Jayasena, N., & Tullsen, D. M. (2015). Understanding idle behavior and power gating mechanisms in the context of modern benchmarks on cpu-gpu integrated systems. In 2015 IEEE 21st international symposium on high performance computer architecture (HPCA) (pp. 366–377). IEEE. 2. Di Carlo, S., Gaudesi, M., Sanchez, E., & SonzaReorda, M. (2014. ISSN 1573-0727). A functional approach for testing the reorder buffer memory. Journal of Electronic Testing, 30(4), 469–481. https://doi.org/10.1007/s10836-014-5461-9. 3. Barrett, S. F., & Pack, D. J. (2005). Microcontrollers fundamentals for engineers and scientists. Synthesis Lectures on Digital Circuits and Systems, 1(1), 1–124. 4. James FCox. Fundamentals of linear electronics: Integrated and discrete. Cengage Learning,2002. 5. Firouzi, F., Kiamehr, S., & Tahoori, M. B. NBTI mitigation by optimized NOP assignment and insertion. 2012 Design, Automation&Test in Europe Conference & Exhibition (DATE), 218–223. ISSN 15301591. https://doi.org/10.1109/DATE.2012.6176465. 6. Guthaus, M. R., Ringenberg, J. S., Ernst, D., Austin, T. M., Mudge, T., & Brown, R. B. (2001). Mibench: A free, commercially representative embedded benchmark suite. In Workloadcharacterization, 2001. WWC-4. 2001 IEEE international workshop on (pp. 3–14). IEEE. 7. Binkert, N., Beckmann, B., Black, G., hardt, S. K. R., Saidi, A., Basu, A., Hestness, J., Hower, D. R., Krishna, T., Sardashti, S., et al. (2011). The gem5 simulator. ACM SIGARCH Computer Architecture News, 39(2), 1–7. 8. Karimi, N., Karthik Kanuparthi, A., Wang, X., Sinanoglu, O., & Karri, R. (2015). Magic: Malicious aging in circuits/cores. ACM Transactions on Architecture and Code Optimization (TACO), 12(1), 5. 9. Lorenz, D., Georgakos, G., & Schlichtmann, U. (2009). Aging analysis of circuit timing considering NBTI and HCI. In On-line testing symposium, 2009. IOLTS 2009. 15th IEEE international (pp. 3–8). IEEE. 10. Abella, J., Vera, X., & Gonzalez, A. (2007). Penelope: The NBTI- aware processor. In Proceedings of the 40th annual IEEE/ACM international symposium on microarchitecture (pp. 85–96). IEEE Com- puter Society.

Chapter 4

Ageing Mitigation Techniques for SRAM Memories Mohd Syafiq Mispan, Mark Zwolinski, and Basel Halak

4.1 Introduction Reliability is one of the major design challenges in designing robust MOSFET devices. The reliability issue is exacerbated as the CMOS devices scaled down towards ultra-deep submicron (UDSM) technology. Time-dependent reliability, such as bias temperature instability (BTI), significantly degrades the performance of a circuit during its operation course. Negative-bias temperature instability (NBTI) is shown to be a critical reliability issue for pMOS transistors in a low-k UDSM technology [1]. A pMOS transistor is subjected to NBTI stress in ON state. Although the NBTI stress is relieved when pMOS transistor is in OFF state, over a prolonged time, the threshold voltage (Vth) degradation, which is the manifestation of the NBTI stress, can significantly impact any digital circuit. Static random-access memory (SRAM) is crucially impacted by the NBTI phenomena. The basic structure of an SRAM cell is a cross-couple of two inverters. Therefore, as the value of ‘1’ is stored in an SRAM cell, the value of ‘0’ is also complementarily stored. One of the inverters in an SRAM cell is always susceptible to NBTI stress. NBTI degrades the static noise margin (SNM) which could lead to read stability issues and potentially cause failures [2]. SNM is a critical reliability

M. S. Mispan The School of Electronics and Computer Science, University of Southampton, Southampton, UK Micro & Nano Electronics (MiNE), Centre for Telecommunication Research & Innovation (CeTRI), Fakulti Teknologi Kejuruteraan Elektrik & Elektronik, Universiti Teknikal Malaysia Melaka, Melaka, Malaysia M. Zwolinski · B. Halak () The School of Electronics and Computer Science, University of Southampton, Southampton, UK e-mail: [email protected] © Springer Nature Switzerland AG 2020 B. Halak, Ageing of Integrated Circuits, https://doi.org/10.1007/978-3-030-23781-3_4

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metric for SRAM, which represents the minimum amount of DC noise voltage that could alter the stored value in the SRAM cell. The impact of NBTI on SRAM is not only limited to its usage as a memory. Over a decade ago, SRAM has been proposed [3, 4] as hardware security primitive, namely, SRAM Physical Unclonable Function (SRAM-PUF). When powering up the SRAM, the start-up values (SUVs) across different memory blocks within an SRAM and across multiple SRAMs show device-specific and random patterns, which can be used as a cryptographic key for secure applications. Reusing the existing on-chip SRAM as a PUF has been suggested [5, 6] to achieve costefficiency. However, when the SRAM is used as a memory, the prolonged storage of the same bit patterns can cause asymmetric NBTI stress of the bit cells. Hence, the SUVs may become unreliable [7]. An increase in the bit error rate results in an increase area overhead of error correction code (ECC) which is needed to generate an error-free cryptographic key [8]. Based on the aforementioned issues, the ageing mitigation techniques for SRAM as a memory, such as periodic bit flipping, self-controlled bit flipping (SCF) and cell flipping with distributed refresh (CFDR), are presented in this chapter. These techniques aim to balance the signal probability in the SRAM cells (i.e. a 50% probability of storing a value of ‘1’ or ‘0’), which lead to symmetric NBTI stress. Therefore, the SNM degradation of SRAM cells can be minimized. To mitigate the impact of ageing on SUVs in a dual-function SRAM as memory and PUF, the bit selection technique is used to select only bit cells that have close to a 50% probability of storing a value of ‘1’. This technique can reduce the bit error in SUVs of an SRAM-PUF and significantly reduce the area overhead of ECC which is required to generate error-free cryptographic keys.

4.2 Chapter Overview This chapter is organised as follows: Sect. 4.3 describes the impact of ageing on memory core performance such as SNM degradation and read failure probability. This section also describes the ageing impact on the reliability of SUVs of SRAM used as PUFs. Section 4.4 presents the first case study of ageing mitigation for SRAM as memory. Section 4.5 presents the second case study, a bit selection technique to mitigate the ageing impact on SRAM as memory and PUF. Finally, this chapter is concluded in Sect. 4.6.

4.3 Impact of Ageing on SRAM Memories in General This section describes the data dependence of NBTI on a 6-T SRAM cell and its impact on the performance of SRAM memory. Additionally, the impact of NBTI on SUVs of SRAM-PUF is also discussed.

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4.3.1 Ageing Impact on SRAM as Memories The basic structure of SRAM as memory is consist of rows and columns of bit cells. The number of available bit cells in an SRAM represents its storage size. Each bit cell of SRAM typically consists of two cross-coupled inverters (MP1, MP2, MN1 and MN2) and two access transistors (MN3 and MN4), as illustrated in Fig. 4.1 and known as 6-T SRAM cell. SRAM cells are used to store the value of ‘0’ or ‘1’. When a ‘1’ is stored in the SRAM cell (Q = 1 and QB = 0), the transistor MP1 is subjected to NBTI stress resulting in a slow increase in the Vth. Under the prolonged storage of ‘1’, the Vth of MP1 increases significantly, whereas the Vth of MP2 remains the same (i.e. asymmetric degradation or stress). Figure 4.1 shows the data dependence of NBTI of a 6-T SRAM cell. The similar NBTI stress is experienced for MP2 if the value of ‘0’ is stored in the SRAM cell (Q = 0 and QB = 1). Therefore, the SRAM cells are always susceptible to the NBTI effect regardless of any values stored in the cells. The NBTI effect on the stability and performance of the SRAM cells has been studied in the literature. This effect degrades the HOLD and READ SNM, whereas the READ and WRITE delay are not significantly affected [9–11]. An SNM is a metric which represents the robustness of an SRAM to hold the stored value in bit cells. An SNM is defined as the minimum DC noise voltage necessary to change the state of an SRAM cell. The SNM is computed as the length of the side of the largest square enclosed between the two voltage transfer characteristic (VTC) curves of a bit cell. Figure 4.2 shows the characterizations of HOLD SNM and READ SNM when the word line (WL) is ‘0’ and ‘1’, respectively. Each characterization yields two values, SNM1 and SNM2; hence SNM = min(SNM1,SNM2). Considering the asymmetric NBTI stress due to the prolonged storage of the similar bit patterns shown in Fig. 4.1, its effect could shift one of the VTCs of SRAM

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to balance the signal probabilities of SRAM cells and reduce the impact of ageing on SNM degradation.

4.3.2 Ageing Impact on SRAM as PUFs SRAM has been proposed as a PUF [3, 4], in which SRAM-PUF exploits the intrinsic manufacturing process variations to generate random and unique SUVs. During the power-up process, as the supply voltage increases, the current flowing through MN1 and MN2 will slowly pull up the voltage at nodes Q and QB (see Fig. 4.1). Transistor MP2 has a slightly higher Vth as compared to MP1 due to the random process variations. Therefore, the current that flows through MN1 is slightly higher than through MN2, thus turning ON the MN2 and pulling down node QB to GND. At the same time when node QB is discharging, MP1 is turned ON and pulls up node Q to Vdd. As shown in Fig. 4.4(a), the nodes Q and QB settle at ‘1 and ‘0’, respectively. The power-up or SUV for each bit cell depends on the device mismatches due to random process variations. As a result, the SUVs of SRAM which consists of rows and columns of bit cells show random and devicespecific patterns, which are desired qualities for PUF [3, 4]. Hence, SRAM-PUF presents a promising solution for cryptographic key generation application. To enable the widespread adoption of SRAM-PUFs, particularly in the lightweight secure application, several papers [5, 6, 12, 13] have suggested a dual function of SRAM as memory and PUF to reduce the cost. Nevertheless, the dual-function SRAM has a reliability limitation due to CMOS ageing process, e.g. NBTI. As shown in Fig. 4.1, when the SRAM is used as memory, because of the prolonged storage of the same bit patterns, e.g. Q = 1, both MP1 and MP2 experienced asymmetric NBTI stress. As a result, the Vth of MP1 increases, higher

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than the Vth of MP2. After the power-up process, the node Q is less likely to power up to ‘1’ than it was before the NBTI effect, as illustrated in Fig. 4.4(b). Hence, the SUV becomes unreliable which is manifested as an increase in the bit error rate. Figure 4.5 illustrates the percentage of error in SUVs as a result of asymmetric NBTI stress (i.e. as the average probability of storing ‘1’ close to a value of 0% or 100%, it indicates an asymmetric NBTI stress) experienced by the SRAM cells [7]. As can be seen from Fig. 4.5, when the SRAM cells undergo symmetric NBTI stress (i.e. 50% probability of storing ‘1’), the error in SUVs is minimized. However, the error in SUVs increases as the NBTI stress becomes asymmetric. In order to use an SRAM-PUF for a cryptographic key generation, it must be able to generate error-free keys and this can be achieved by using ECC [14]. Bose–Chaudhuri–Hocquenghem (BCH) is an ECC scheme that has been widely used for correcting errors of PUFs [15, 16]. The BCH scheme is given as [n, k, t] where n raw bits (code word) are required for a k bit message and the scheme can correct up to t bits in error. Figure 4.6 shows the procedure of cryptographic key generation based on SRAM-PUF which consist of two phases: Enrolment and Reconstruction. Enrolment occurs just once when the new key is generated or stored. In the Enrolment phase, the range of the SRAM memory address, given as w, is used as a challenge to the SRAM-PUF and y is the extracted SUVs. The subset of y, k, is encoded using the BCH scheme to generate a code word, n, and the helper data, h, is computed as y ⊕ n. The key is generated by hashing the k. At the end of the Enrolment phase, the memory address range, w, and the helper data, h, are stored in the non-volatile memory (NVM). In the Reconstruction phase, the same PUF is measured again, and the noisy SUVs, yt , which contain errors due to the environmental variations and ageing, is extracted. The helper data, h, is recalled to compute the noisy code word, nt = yt ⊕ h. The BCH scheme is used to correct the errors and recover the k. Finally, the key is reconstructed by hashing the k.

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Although the procedure as shown in Fig. 4.6 can be used to generate an errorfree cryptographic key, the ECC implementations require significant area overheads which increase as the error in the SUVs increases [16]. This can be seen as a disadvantage for the SRAM-PUF to be used in lightweight cryptographic key generation. In Sect. 4.5, the bit selection technique is introduced to mitigate the impact of ageing in a dual-function SRAM.

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4.4 Case Study 1: Ageing Mitigation for Cache Memories (Bit Flipping) One of the most significant applications for SRAM is as a cache memory in a computing system designed to reduce the access latency of the main memory, by storing the most frequently used instruction or data in the cache. As the most frequently used instruction or data will be retained in the cache, it is susceptible to asymmetric NBTI stress due to the prolonged storage of the same bit patterns as explained in Sect. 4.3.1. A 50% probability of storing a value of ‘1’ or ‘0’ is required to balance the NBTI stress on pMOS transistors, MP1 and MP2, in a 6-T SRAM cell (see Fig. 4.1). For ageing mitigation on instruction cache (i-cache) and data cache (d-cache) memories, Kumar et al. [18] introduced a periodic bit flipping which flips the contents of the entire cache periodically for every predefined period. When the flipping process is activated, the first memory address is accessed and the bit lines are read, inverted and written back to the same address. This process is continued until all addresses are accessed and the entire data inside the cache is flipped. The periodic bit-flipping interface is illustrated in Fig. 4.7. This technique can be implemented by a software approach using a subroutine, which is written in the system to access each address, read the cell contents, store into the processor registers, inverted and written back to the same address. Nevertheless, the software approach introduced huge access time overhead. Hence, the hardware approach is preferred as the data is flipped locally, which is much faster compared to the software approach. The cache with a periodic bit-flipping technique has been implemented using 100nm and 70-nm predictive technology model (PTM) technology [18]. The circuit has been subjected to ageing for 108 seconds, which is equivalent to ≈3.17 years. Table 4.1 shows the SNM degradation experienced by the SRAM cells due to the Fig. 4.7 A periodic bit-flipping circuitry [18]

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NBTI, with and without a periodic bit-flipping technique. The periodic bit-flipping technique recovers the SNM degradation by ≈30% for both 100-nm and 70-nm technologies as compared to that without a periodic bit-flipping technique. The results in Table 4.1 indicate that the periodic bit-flipping technique can reduce the impact of ageing on SNM degradation of SRAM cells. However, a periodic bit flipping has a disadvantage where it interrupts the normal operation of cache memories. Gebregiorgis et al. [2] proposed a self-controlled bit-flipping (SCF) technique which uses a flip-on-access (FOA) mechanism to avoid an interruption of normal cache operations. The SCF technique has been applied on i-cache and d-cache of LEON2 processor. The SCF technique started with the selection of a flag bit used to control the bit-flipping sequence. A flag bit is implicitly selected out of the data inputs of cache array (e.g. 1 bit out of 32 bits) through an offline selection algorithm. Ideally, the flag bit should be the bit position which has a 50% probability of storing a value of ‘1’ or ‘0’. When the flag bit is ‘1’, the value of all other bits is flipped before the write operation and flipped back during the read operation. When the flag bit is ‘0’, the value of all other bits remained the same during write and read operations. Once the flag bit is selected, it is connected to the Flipin and Flipout inputs of the FOA circuitry as illustrated in Fig. 4.8.

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The SRAM cells with an SCF technique has been implemented using a 45-nm PTM technology. The circuit has been subjected to ageing for 3 years. The ageing stress patterns are based on the signal probability distribution of i-cache and d-cache of LEON2 processor, running 12 programs which were chosen from Powerstone and MiBench benchmarks suites [2]. Based on the findings in [2], the SCF technique reduces the average SNM degradation by about 35.4%. Also reported in [2] is the periodic bit-flipping technique that reduces the average SNM degradation by about 33.1%. These results show that the SCF and the periodic bit flipping achieve almost the same level of reliability. As the SCF technique is using the FOA mechanism, this technique has the advantage of avoiding the interruption of normal cache operations. Nevertheless, the FOA mechanism requires that the write access to be uniformly distributed to achieve balanced ageing stress over the entire cache. As mentioned earlier in this section, the most frequently used instruction or data is stored in the cache. As the low cache miss rate is always desired to reduce the data access latency from the main memory, only a certain address location in the cache is replaced with the new data (i.e. the cache miss occurs). This means that the write access is non-uniformly distributed and an FOA mechanism is less frequently activated. The average probability of storing a value of ‘1’ for a 32-bit i-cache for ARMv8 architecture has been studied in [7, 19]. The average probability has been computed over 16 benchmark programs which were chosen from the MiBench and LLVM benchmark suites, using GEM5, covering a number of different functions [19]. The average probability without an FOA (i.e. no bit-flipping technique applied for the ageing mitigation) is illustrated in Fig. 4.9. It can be seen that some bits preserve the same values in most locations which leads to the NBTI stress due to the prolonged storage of the same bit patterns. This is because some types of instruction are used more frequently than the others. For example, the four most significant bits of instruction sets of an ARM processor are the condition field and

Fig. 4.9 Average probability of storing a ‘1’ in i-cache ARMv8 architecture over 16 benchmarks for direct mapped associativity [19]

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‘1110’ is used for unconditional instructions. Duan et al. [20] presented that the number of unconditional instructions is much bigger and frequently used than that of conditional instructions in any program. As a consequence, these four bits have a high probability of being ‘1110’ as depicted in Fig. 4.9. It is also important to note that the probability distribution is generally independent of the running programs. Furthermore, the bit-flipping technique which uses an FOA scheme is applied in the i-cache and the optimized stress pattern is compared with that of the icache without the FOA. The average probability of storing a value of ‘1’ for both with and without the FOA scheme is depicted in Fig. 4.9. As can be seen, the probabilities are becoming closer to a 50% probability. However, the probabilities are not fully equalized by the FOA scheme as the write access is not uniformly distributed across the entire i-cache. Following this, Duan et al. [19] introduced a cell flipping technique with distributed refresh phases (CFDR) to further mitigate the NBTI effect in an i-cache. The CFDR method flips and refreshes one cache block at a time in an order from a lower to a higher index, at a certain refresh rate. As the cache lifetime improvements are in a timescale of years, the refresh rate can be a relatively long (e.g. several days or weeks). Hence, each cache block is refreshed uniformly and the interruption time of the normal cache operation is minimized. Figure 4.10 shows the CFDR circuitry which consists of a control unit and a flipping interface. The control unit is used to activate the refresh phase and to check/restore the data in the refreshed cache block (i.e. storing the complementary/true values) if it needs to be accessed during the normal operation.

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A similar set of 16 benchmark programs from MiBench and LLVM benchmark suites is used to evaluate the effectiveness of CFDR technique. Fig. 4.11 depicts the average probability of storing a value of ‘1’ for a 32-bit direct mapped i-cache with a CFDR technique. As can be seen, the probabilities of all bits are close to 50%. The CFDR technique successfully distributes the write access uniformly over the entire cache, hence leads to a symmetrical NBTI stress and is expected to reduce the impact of ageing on SNM degradation of the SRAM cells. To evaluate the effectiveness of the CFDR technique in mitigating the ageing impact, Duan et al. [19] injected the noise voltage of 0.12 V into the SRAM cells. If the ageing degrades the SNM below the noise voltage, the SRAM cells are no longer able to hold the stored value which causes the bit error to occur. Table 4.2 listed the number of bit errors experienced by the normal cache (i.e. without ageing mitigation technique) and the comparison of error reductions when the FOA and CFDR techniques were applied. In average, the CFDR and FOA techniques can reduce about 63.41% and 49.82% of errors, respectively. The CFDR technique performs better in minimizing the errors due to ageing as compared to FOA technique by about 13.59%. Note that the application of CFDR technique is not only limited to i-cache memories as reported in [19] but this technique can also be applied on d-cache memories. All of the aforementioned discussed some of the ageing mitigation techniques for SRAM reported in the literature, focusing on the usage of SRAM as instruction and/or data cache memories.

4 Ageing Mitigation Techniques for SRAM Memories Table 4.2 Error reductions of using FOA and CFDR techniques [19]

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103 Error reduction (%) FOA CFDR 100 100 42.53 63.22 32.88 58.90 23.86 31.53 49.82 63.41

4.5 Case Study 2: Ageing Mitigation for Instruction Cache-Based PUF Recently, another usage of SRAM has been explored in which SRAM has been proposed as PUF [4]. The random SUVs of SRAM-PUF can be used as a cryptographic key in secure application. Previous studies [5, 6] show that the dual use of SRAM as memory and PUF is feasible and implementable on the embedded system and system-on-chip (SoC) platforms. Hence, the dual use of SRAM is cost-efficient and can enable the widespread adoption of SRAM-PUFs in secure lightweight applications. Nevertheless, as mentioned in Sect. 4.3.2, the asymmetric NBTI stress due to the prolonged storage of the similar bit patterns when the SRAM is used as memory may cause errors in SUVs when the SRAM is used as a PUF. As the errors in SUVs increases, the area overhead of ECC increases. Fig. 4.12 depicts the relationship of error, t, the estimated gate equivalent (GE) or area of the BCH scheme and the code word, n. For code word, n = 127, as t increases from 1 to 7, the area increases ≈5.6 times. Mispan et al. [7] proposed a bit selection technique to mitigate the impact of NBTI in a dual-function SRAM as memory and PUF. The on-chip memory, particularly the i-cache in 32-bit ARMv8 architecture, is used as a case study [7]. The signal probability patterns of the i-cache are analysed and the bit selection is used as a pre-processing technique to only select bit cells that have close to a 50% probability of storing a value of ‘1’ or ‘0’. These bit cells experience a balanced NBTI stress and are able to retain the intrinsic mismatch of the inverters in the cell. Hence, increase the SUV reliability for PUF usage. The average signal probability patterns for an i-cache of ARMv8 architecture are shown earlier in Fig. 4.9. Figure 4.13 re-illustrated the i-cache signal probabilities with the mean and standard deviation values. As can be seen from Fig. 4.13, some of the bits have close to a 50% probability of storing ‘1’ such as bits 12, 13, 16, 20, 23 and 25. This indicates that those bits will experience symmetric NBTI stress, and thus are more reliable over time. On the other hand, bits 31:29 have a high probability of storing ‘1’, while bit 28 as well as bits 11:9 have a high probability of storing ‘0’. The prolonged storage of the same bit value over time causes asymmetric NBTI stress, and thus those bits are likely to have reliability issues.

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2

·104 t=1 t=2 t=3 t=4 t=5 t=6 t=7

Area (GE)

1.5

1

0.5

0 32

64

128 256 512 Codeword, n = 2m −1

1,024 2,048

Overall Probability of Storing 1 (%)

Fig. 4.12 Area (GE) of the BCH scheme [17]

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80 60 40 20 0

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Fig. 4.13 Mean and standard deviation values for the probability of storing a ‘1’ in i-cache ARMv8 architecture over 16 benchmarks for direct mapped associativity [7, 19]

The earlier analysis has also been conducted for d-cache memories running four benchmark programs such as bubblesort, basicmath, queens and susan. Figure 4.14 illustrates the mean values for the probability of storing ‘1’ in d-cache running the aforementioned benchmarks. As can be seen from Fig. 4.14, the distributions are highly dependent on applications and they are less than 50% probability of storing a ‘1’, indicating asymmetric NBTI stress. It is possible that other benchmarks may produce different distributions with bit probabilities equal to or higher than 50%. However, the high dependency on applications make the d-cache strongly

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Fig. 4.14 Mean values for probability of storing ‘1’ in d-cache running four benchmarks [17]

unpredictable, hence, not suitable for the bit selection implementation to enable dual function of SRAM as memory and PUF. For a proof of concept, the i-cache has been implemented with a configuration of 32 bits × 64 rows using a TSMC 65-nm technology [7]. Monte Carlo simulation is used to model the intrinsic manufacturing process variations of i-cache as PUF. A Monte Carlo simulation was performed for 100 i-cache instances. To determine the ageing due to NBTI, the duty cycle for the SRAM cells was defined according to the signal probabilities in Fig. 4.13. Figure 4.15 shows the randomness of SUVs for 100 instances at fabrication time and after 5 years of ageing. Prior to the NBTI effect, the SRAM cells have an even distribution of ‘1’ and ‘0’ as shown in Fig. 4.15, and therefore, they are random. However, when the SRAM cells undergo the NBTI stress, the distribution of ‘1’s and ‘0’s become uneven which indicates the occurrence of bit errors. The Hamming Distance (HD) is used to compute the bit error before and after ageing. Figure 4.16 depicts the errors in SUVs after 5 years of ageing. As expected, because of the symmetric stress experienced by bits 12, 13, 16, 20, 23 and 25, the bit error count in those positions is much less than for the other bits. The idea of bit selection technique is to only select bits for the PUF that have close to a 50% probability of storing ‘1’ values which yield the lowest bit error due to the symmetric NBTI stress. Hence, the SUVs extracted from these bit positions are reliable and the error due to ageing can be minimized. The bit selection technique can be performed by taking the hamming weight (HW) from Fig. 4.15b and the mean probability of storing ‘1’ from Fig. 4.13; the relationship between these two parameters for all 32 bits can be seen in Fig. 4.17.

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Fig. 4.17 The relationship between the HW and the mean probability of storing ‘1’ for all 32 bits [7] Table 4.3 Bit error (%) of bit selection combination based on mean probability of storing ‘1’ [7] Selection set S1 S2 S3 S4 S5 S6 S7

LB 0.40 0.35 0.30 0.25 0.20 0.15 0.10

UB 0.60 0.65 0.70 0.75 0.80 0.85 0.90

Selected bits 12,13,16,20,23,25 S1 + 2,17,18,19,21 S2 + 0,3,24,26 S3 + 1,4,5,14,22,27 S4 + 6,15,30 S5 + 7,8,9,10,11,29,31 S6 + 28

Error (%) 3.30 4.98 6.28 8.01 8.93 10.83 11.13

The initial selection window (i.e. the lower [LB] and upper boundaries [UB]) for a bit selection process is set such that the bits that have the lowest bit error rate are within this window. These bits are 12, 13, 16, 20, 23 and 25, represented as an S1 selection set. Therefore, the LB and UB are set at 0.4 and 0.6, respectively, as highlighted by the two dashed lines. Next, the margin of the selection window is widened by ±0.05. The aim is to maximize the number of bits while keeping the error below the maximum error tolerance value. As can be seen in Table 4.3, as the margin of bit selection increases, the total bit error rate increases. Set S7 represents all 32 bits and has the highest bit error rate of 11.13%.

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Selection set S1 S2 S3 S4 S5 S6 S7

Error (%) Mean −3σ 3.30 5.58 4.98 8.39 6.28 9.39 8.01 11.43 8.93 12.14 10.83 13.77 11.13 14.18

+3σ 2.02 2.23 3.58 4.88 5.98 8.12 8.35

All of the aforementioned show the procedure of bit selection using the mean probability of storing a value of ‘1’. To determine which selection set is the most suitable for NBTI mitigation while still fulfilling the maximum error tolerance value, it is important also to consider the ±3σ spread of the probability of storing a ‘1’. Hence, the earlier procedure is re-applied to calculate the average bit error for every bit position based on the ±3σ probability of storing a ‘1’ as in Fig. 4.13. Table 4.4 shows the computed bit error rate for selection sets S1–S7. The overall bit error rate is worst at −3σ as all the bits would be shifted to the left in Fig. 4.17, away from the 50% probability of storing ‘1’. Conversely, at +3σ , all the bits are shifted to the right, closer to the 50% probability of storing ‘1’, making the overall bit error rate better than the mean. With a bit selection technique, the bit error rate varies depending on the selection window. For a proof of concept, the maximum error tolerance due to NBTI is set to be at 6%. Therefore, the selection set S1 is chosen and it is expected to reduce the area overhead of the ECC since the bit error rate is much smaller than without a bit selection technique (i.e. using all 32 bits). Nevertheless, other sources of variations that could cause errors in SUVs, in particular, temperature and supply voltage fluctuations must be considered in determining the complexity of ECC. According to [7], the maximum bit error is ≈6.2% for both selection sets, S1 and S7, caused by the temperature variations, in a range of −40 ◦ C to 85 ◦ C, and the supply voltage fluctuations of 1.2 V ± 10%. To be conservative, the maximum error tolerance is adjusted to be at 6.5% considering the ageing, temperature and supply voltage variations for S1 selection set. The bit selection can be implemented using a multiplexer in which the select signals are preconfigured depending on the target error rate and bit select configuration. A 32-to-1 multiplexer is required to select 1 bit out of 32 bits from the output bus of the i-cache. Thus, the bit select block can be constructed using a 6 × 32-to-1 multiplexer for selecting the S1 bits: 16, 13, 25, 20, 12 and 23. In the procedure for cryptographic key generation shown in Fig. 4.6, the bit select block is inserted before the SUVs, and y^ are input into the evaluation block (or can be inserted within the evaluation block). 280 GEs are required for a 6 × 32-to-1 multiplexer, estimated using Synopsys Design Compiler. As discussed in Sect. 4.3.2, the BCH scheme is used as an ECC to generate errorfree cryptographic keys. According to [3, 6], to ensure a sufficient entropy, an input

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Table 4.5 Area comparison [7] Technique Without bit selection Bit selection

BCH (GE) 226,224 37,050

Bit selection (GE) NA 280

Total (GE) 226,224 37,330

to the hash function must be larger than the generated key. Therefore, the BCH scheme has to generate at least 171 error-free bits before being used as the input to the hash function to produce a 128-bit cryptographic key (Fig. 4.6). With the bit error rate of 6.5% and the target failure rate of ≤10−6 , 1524 raw bits are required for the S1 selection set using a [127, 15, 27]-BCH [7]. Hence, the suggested minimum size of an i-cache to be used with the S1 selection is 1kB. Without using a bit selection technique would require more area for the BCH scheme because of an increase in the bit error rates. Considering the bit error rates due to ageing and environmental variations, using all 32 bits would yield a maximum error of 14.18%. This requires 4599 raw bits using the BCH scheme of [511, 19, 119] for a target failure rate of ≤10−6 and a minimum i-cache size of 1 kB. The area for both BCH schemes earlier is estimated based on the extrapolated data of Fig. 4.12. Table 4.5 listed the comparison of area overhead with and without a bit selection technique. By using a bit selection technique, the total area overhead is about 6× smaller compared to that without a bit selection technique. Notice that the area overhead of the multiplexer (3rd column in Table 4.5) to perform a bit selection technique is almost negligible. This comparison proves that the bit selection technique helps in reducing the area overhead of the ECC.

4.6 Conclusion The impact of NBTI on SRAM as memory is crucial as it degrades the HOLD and READ SNM, which has the potential to cause read access failure. Besides, the NBTI stress causes the reliability issues for dual-function SRAM as memory and PUF. An increase in the bit error rate of SRAM-PUF increases the area overhead of the ECC. In this chapter, two case studies of ageing mitigation techniques are presented. The first case study reviewed the ageing mitigation techniques for SRAM as memory. The periodic bit-flipping and the SCF techniques are proposed to mitigate the ageing impact on memories. The results show that these techniques achieved almost the same level of reliability, about 30–35% recovery of SNM degradation in 3 years. Nevertheless, the SCF technique has an advantage as it uses the FOA mechanism; hence, the normal operation of the cache memories is not interrupted. Recently, the CFDR technique is proposed to improve the efficiency of the FOA mechanism by uniformly distributing the write access (i.e. the refresh phase) over the entire cache. To minimize the impact on the interruption of normal cache operation, the CFDR technique flips and refreshes one cache block at a time in an order from a lower to a

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higher index, at a certain refresh rate (e.g. several days or week). The results show that the CFDR technique can recover the bit error due to SNM degradation by about 13.59% as compared to the FOA technique. Additionally, the ageing mitigation technique for SRAM as memory and PUF is presented as a second case study. The bit selection technique is proposed to only select the bit cells that have close to a 50% probability of storing a value of ‘1’ or ‘0’. These bit cells experience symmetric NBTI stress. Hence, the SUVs extracted from these bit positions, for PUF usage, are more reliable and the error due to ageing can be reduced from 14.18% to 5.58% in 5 years. As a result, by using a bit selection technique, the area overhead of ECC is about 6× smaller compared to that without a bit selection technique.

References 1. Mispan, M. S., Halak, B., & Zwolinski, M. (2016). NBTI aging evaluation of PUF- based differential architectures. In: IEEE international symposium on on-line testing and robust system design (pp. 103–108). 2. Gebregiorgis, A., Ebrahimi, M., Kiamehr, S., Oboril, F., Hamdioui, S., & Tahoori, M. B. (2015). Aging mitigation in memory arrays using self-controlled bit-flipping technique. In: Asia and South Pacific design automation conference (pp. 231–236). 3. Guajardo, J., Kumar, S. S., Schrijen, G. J., & Tuyls, P. (2007). FPGA intrinsic PUFs and their use for IP protection. In: International conference on cryptographic hardware and embedded systems (pp. 63–80). 4. Holcomb, D. E., Burleson, W. P., & Fu, K. (2009). Power-Up SRAM state as an identifying fingerprint and source of true random numbers. IEEE Transactions on Computers, 58(9), 1198– 1210. 5. Kohnhäuser, F., Schaller, A., & Katzenbeisser, S. (2015). PUF-based software protection for low-end embedded devices. In M. Conti, M. Schunter, & I. Askoxylakis (Eds.), Trust and trustworthy computing (pp. 3–21). Berlin, Germany: Springer International Publishing. 6. Schaller, A., Arul, T., Van Der Leest, V., & Katzenbeisser, S. (2014). Lightweight anticounterfeiting solution for low-end commodity hardware using inherent PUFs. In Trust and trustworthy computing (pp. 83–100). Heidelberg: Springer International Publishing. 7. Mispan, M. S., Duan, S., Zwolinski, M., & Halak, B. (2018). A reliable PUF in a dual function SRAM. In: International symposium on power and timing modeling, optimization and simulation (pp. 76–81). 8. Simons, P., Van Der Sluis, E., & Van Der Leest, V.. (2012). Buskeeper PUFs, a promising alternative to D Flip-Flop PUFs. In: IEEE international symposium on hardware-oriented security and trust (pp. 7–12). 9. Calimera, A., Macii, E., & Poncino, M. (2010). Analysis of NBTI-induced SNM degradation in power-gated SRAM cells. In: IEEE international symposium on circuits and systems (pp. 785–788). 10. Mostafa, H., Anis, M., & Elmasry, M. (2011). Adaptive body bias for reducing the impacts of NBTI and process variations on 6T SRAM cells. IEEE Transactions on Circuits and Systems I: Regular Papers, 58(12), 2859–2871. 11. Faraji, R., & Naji, H. R. (2014). Adaptive technique for overcoming performance degradation due to aging on 6T SRAM Cells. IEEE Transactions on Device and Materials Reliability, 14(4), 1031–1040. 12. Hoffman, C., Cortes, M., Aranha, D. F., & Araujo, G. (2015). Computer security by hardwareintrinsic authentication. In: International conference on hardware/-software codesign and system synthesis (pp. 143–152).

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13. Bacha, A., & Teodorescu, R. (2015). Authenticache: Harnessing cache ECC for system authentication. In: International symposium on microarchitecture (pp. 128–140). 14. Leest, V. V. D., Maes, R., Pim, G. J. S., & Tuyls, P. (2014). Hardware intrinsic security to protect value in the mobile market. In: Information security solutions Europe (pp. 188–198). 15. Rahman, M. T., Rahman, F., Forte, D., & Tehranipoor, M. (2016). An aging-resistant RO-PUF for reliable key generation. IEEE Transactions on Emerging Topics in Computing, 4(3), 335– 348. 16. Lao, Y., Yuan, B., Kim, C. H., & Parhi, K. K. (2017). Reliable PUF-based local authenti- cation with self-correction. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 36(2), 201–213. 17. Mispan, M. S. (2018). Towards reliable and secure physical unclonable functions. Ph.D. thesis, University of Southampton. 18. Kumar, S. V., Kim, C. H., & Sapatnekar, S. S. (2006). Impact of NBTI on SRAM read stability and design for reliability. In: International symposium on quality electronic design (pp. 210– 218). 19. Duan, S., Halak, B., & Zwolinski, M. (2018). Cell flipping with distributed refresh for cache ageing minimization. In: IEEE Asian test symposium (pp. 1–6). 20. Duan, S., Halak, B., Wong, R., & Zwolinski, M. (2016). NBTI lifetime evaluation and extension in instruction caches. In: Workshop on early reliability modeling for aging and variability in silicon systems (pp. 9–12).

Chapter 5

Ageing-Aware Logic Synthesis Shengyu Duan, Mark Zwolinski, and Basel Halak

5.1 Introduction The increasingly improved functionality of logic circuits results in considerably increased circuit density and design complexity. In order to accommodate the demand for efficient design process, logic synthesis has become a significant EDA process, enabling the design of circuits with many millions of transistor [1]. Modern logic synthesis not only produces a circuit based on the behavioural description, but also attempts to find a design satisfying the given specifications like delay, area and power; yet the lifetime reliability is barely considered. The continuous downscaling of transistor dimensions has posed a growing concern about CMOS lifetime reliability, which is affected by multiple wearout mechanisms, causing time-dependent variations and performance loss. Bias Temperature Instability (BTI) is one of the dominant ageing effects, increasing CMOS threshold voltage (Vth ), when a transistor is at the on state. The Vth shift cannot be fully recovered, when the transistor is turned off. The BTI effect degrades NMOS and PMOS transistors in the form of positive BTI (PBTI) and negative BTI (NBTI), respectively. BTI is currently believed to be the most lifetime-limiting mechanism for logic circuits, because of their long static time, putting a great many transistors at the stress state for a long time [2]. The BTI-induced Vth shift increases circuit delay, and thus the lifetime reliability of BTI is given by the post-ageing delay. The BTI effect shortens the circuit lifetime by causing timing violations (e.g. setup time violations) after a certain period. In order to maintain a reliable operation during the expected lifetime of a circuit, it is important to incorporate BTI analysis and optimizations into a synthesis process.

S. Duan · M. Zwolinski · B. Halak () The School of Electronics and Computer Science, University of Southampton, Southampton, UK e-mail: [email protected] © Springer Nature Switzerland AG 2020 B. Halak, Ageing of Integrated Circuits, https://doi.org/10.1007/978-3-030-23781-3_5

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5.2 Chapter Overview This chapter will offer some perspective on how lifetime optimization techniques can be applied in the modern synthesis process. The rest of the chapter is organized as follows. Section 5.3 describes standard synthesis flow and the optimization phases in the process. Section 5.4 presents case studies for different lifetime optimization techniques, based on their incorporated areas of a synthesis process. The techniques discussed in Sect. 5.4 are compared, considering the lifetime improvement, cost and complexity. This chapter is concluded in the final section, Sect. 5.5.

5.3 Modern Logic Synthesis 5.3.1 Basic Flow During synthesis, an abstract form of circuit description (i.e. a behavioural model) is implemented by a circuit netlist (i.e. a gate-level model) mapped to a specific cell library. A standard synthesis process is performed by the flow shown in Fig. 5.1. It includes a technology-independent transformation and a technologyspecific transformation. During the technology-independent transformation, a behavioural model circuit description is converted into a logic-level form, represented by Boolean expressions. Modern synthesis process produces a circuit structure based on the functionality

Abstract form (behavioural) Technologyindependent

Design constraints Boolean expressions (logic-level)

Technologyspecific

Fig. 5.1 A basic synthesis flow

Cell library Circuit netlist (gate-level)

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rise delay (ns)

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and some design requirements, such as timing, area and power. Thus, the design constraints are considered during the technology-independent transformation. The Boolean expressions produced by the technology-independent transformation is then mapped by gates of a cell library, to give a gate-level circuit netlist, during the technology-specific transformation. Each cell of the library is precharacterized based on its function, timing, area, etc. Some attributes like delay and power of a cell are dependent on input transition time (tin ) and output capacitance (Cout ). The values of these attributes are often determined by searching a twodimensional look-up table (LUT) of different tin and Cout . Figure 5.2 shows a LUT for the rise delay of an inverter of a 65-nm technology node, as an example. The LUTs are used to measure the overall delay and power of a circuit and decide whether the design specifications are met. In this way, the technology-specific transformation produces a gate-level circuit based on both circuit function and design constraints.

5.3.2 Optimization Process Logic synthesis is constraint driven. The design constraints are satisfied by applying optimization techniques at each phase of a synthesis process. Figure 5.3 shows a typical optimization flow of logic synthesis process [3]. The optimization process includes a logic-level optimization for the technology-independent transformation and a gate-level optimization, after the logic is mapped, for the technology-specific transformation. The process ends when the design constraints are met or no further improvements can be made.

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Fig. 5.3 Optimization process for logic synthesis

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The optimization process considers multiple circuit parameters if they are specified in the given design constraints. Optimization for one parameter may sometimes be contradictory to the optimizations for other parameters. For instance, upsizing a logic gate may reduce the circuit delay but leads to more area cost. Thus, the ultimate aim of the optimization process is often to find a good tradeoff between timing, area and more lately power. Current optimization process in the commercial synthesis tools does not consider reliability, including the lifetime reliability. In practice, designers can only overdesign a circuit and put in pessimistic timing margins to compensate for the BTI-induced delay shifts, namely, guardbanding. This method will be discussed in more detail and will be compared with another two types of lifetime optimization techniques, in Sect. 5.4.

5.4 Synthesis for Lifetime Reliability Section 5.3.1 has described a basic synthesis flow. Ageing-aware analysis and optimizations need be incorporated in current synthesis process to ensure reliable operation in the presence of BTI. An ageing-aware synthesis process optimizes the post-ageing delay, rather than the intrinsic circuit delay, while also considering other parameters like area and power. The post-ageing delay of a signal path is given by the sum of the intrinsic delay and BTI-induced delay shift, and the path having the largest post-ageing delay determines the lifetime of the circuit. Thus, the goal of ageing-aware logic synthesis can be formulated as follows, in Eq. 5.2, for a circuit with N signal paths. Di and Di are the intrinsic delay and delay shift, respectively, for path i. Therefore, the sum of Di and Di represents the post-ageing delay of

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path i. Minimize

max (Di + Di )

1≤i≤N

(5.1)

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(5.2)

Based on the strategies and the incorporated areas of logic synthesis, BTI-aware optimization techniques can be categorized into three groups: • Guard-banding: this type of method targets to reduce the intrinsic circuit delay Di by applying a smaller timing constraint. • Library re-characterization: this type of method considers Di + Di as a whole and reduces the post-ageing delay. A re-characterized cell library with post-ageing information for each cell is used to synthesize a design. • Ageing-aware transformation: this type of method is incorporated in the optimization process. The logic structure or gates of a circuit are replaced by those suffering from less BTI stress, aggressively reducing the amount of delay shift Di . The rest of this section will describe the three types of methods in more detail. A simplified BTI model (Eq. 5.3) [4], derived from a Reaction-Diffusion mechanism, will be used to compute degradation for a transistor, allowing us to compare the effectiveness of all discussed techniques. Dbti (t) = K.D0 .α n .t n

(5.3)

where K is a constant parameter dependent on the technology node, temperature and supply voltage. It equals 0.3 and 0.03 year−n for NBTI and PBTI, respectively, for a 65 nm CMOS technology at 25 ◦ C temperature and 1.2 V supply voltage; D0 is the delay at time-zero; α is the stress duty cycle, indicating the ratio of the stress time to the total; t represents the operational time; and n is a time exponential constant equal to 0.16. The lifetime of a circuit is defined as the point when the degraded combinational delay can no longer meet the given clock period. Here, the sequential timing characteristics (e.g. clock-to-Q delay and setup time) are not considered, as they are much smaller compared with the combinational delay. The lifetime is computed by the maximum operational time for a circuit to run with a clock period tclk , as given in Eq. 5.4. Lifetime = max(J ) where J = {j | max (Di + Di ) ≤ tclk } 1≤i≤N

(5.4)

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Delay

Time-zero Post-ageing

tclk

Guardbanding

Area Fig. 5.4 Guard-banding method to maintain lifetime reliability

5.4.1 Guard-Banding In practice, the guard-banding method has been used to overcome many unreliability sources, including the BTI effect. It is realized by giving a smaller timing constraint during the synthesis and adding a pessimistic timing margin to prevent the circuit from timing errors. In this way, the circuit timing can still be maintained within the design specifications, even if the transistor parameters have been changed due to ageing, as shown in Fig. 5.4. Gate resizing is currently the most commonly used technique to ensure an optimized circuit satisfying the smaller timing constraint, but other techniques (e.g. gate splitting, logic restructuring) are also feasible [5]. These techniques are mostly employed by the commercial synthesis tools, and thus the guard-banding method is easy to implement. In order to specifically guard-band a circuit for lifetime reliability, the extra timing margin is set based on an ageing prediction. For example, a circuit of 65-nm CMOS technology suffers from 20% around delay degradation within the first 10 years1 [5]. In such a case, a timing constraint, leading to a 20% around guard-band, should be applied to ensure a circuit working properly within a 10-year lifetime. Note that the amount of BTI-induced delay shift may vary for different circuits, workloads or operating environments. Thus, the timing margin based on an ageing prediction may not lead to the exact lifetime as expected. The predicted degradation should only be used as a guideline to potentially realize a target lifetime. An example of circuit guard-banding is shown in Fig. 5.5, where the c432 circuit of ISCAS’85

1 The

degradation is caused by the coaction of NBTI and PBTI but is mostly contributed by NBTI for the 65-nm technology, which uses silicon dioxide-based transistors. PBTI is only considered to be crucial for the transistors with high-k materials, mostly applied for sub-40-nm technologies.

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a

b U3 U1

a

U2 b

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critical

critical

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Fig. 5.6 Critical path optimization by load splitting. (a) Original. (b) Optimized

benchmark is synthesized, putting in 10% and 20% guard-bands, respectively, for a 1.8 ns clock period. As can be seen, a 10% timing margin gives the circuit less than 1-year lifetime. The lifetime is dramatically increased to 8.119 years by using a 20% guard-band, in this example. The guard-banding method focuses on the reduction of the intrinsic circuit delay, regardless of the change of the degradation. Thus, the lifetime improvement is not always promised, because the amount of degradation may still be large or become even larger on a guard-banded circuit, compared with the original design. This is because a transformation that reduces the delay of a gate or a sub-circuit may increase the delay of other parts of the circuit, or cause more circuit degradation if the other parts are more sensitive to ageing. To illustrate this circumstance, a load splitting technique is applied as a simple example to optimize a circuit critical path, shown in Fig. 5.6. Load splitting is one of the commonly used optimization techniques in commercial synthesis tools, to decrease a path delay by reducing the fan-out of some internal nodes. The intrinsic delay and degradation after 10 years of each gate and the critical path are computed, in Table 5.1, assuming node a equals

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“0" all the time. As can be seen, the load splitting technique reduces the intrinsic delay of the critical path and provides a larger timing guard-band, but the optimized circuit suffers from more severe BTI degradation, compared with the original one. This is because load splitting increases the fan-out and therefore the delay of gate U1. As node a has a high probability to be logic 0, the gate U1 is sensitive to ageing. The increased propagation delay largely increases the degradation of U1, causing a greater delay shift for the critical path, according to Table 5.1. The results of this example indicate the guard-banding method fails to optimize the more ageingsensitive part of a circuit, and thus the amount of degradation may still be great on an optimized circuit, limiting the lifetime and causing more area cost. This problem may also occur when applying other techniques to guard-band a circuit. We guard-banded the c499 circuit of ISCAS’85 benchmark by using a commercial synthesis tool, Synopsys Design Compiler, and giving a smaller timing constraint during synthesis, in an attempt to have a 10-year lifetime. Figure 5.7 shows the post-ageing delay of both the original and guard-banded circuits. As can be seen, the guard-banded circuit has a smaller intrinsic delay and larger area, compared with the original circuit, but both designs fail to ensure a 10-year lifetime, as the delays become larger than tclk after 9 years. Comparing the post-ageing delays Table 5.1 Intrinsic delays and degradations of circuits in Fig. 5.6 U1 U2 U3 Path

Intrinsic delay (ps) Orig. Opt. 21.79 33.28 57.21 48.57 32.21 23.13 111.22 104.98

Degradation (ps) Orig. Opt. 9.45 14.43 2.48 2.11 13.97 10.03 25.9 26.57

Post-ageing delay (ns)

tclk=1.63 ns 1.6 1.5 1.4 1.3 0

3

6 Time (year)

Original design

9

Guard-banded design

Fig. 5.7 Post-ageing delays for the c499 circuit given different timing guard-bands (Areaorig = 770.64 μ m2 , Areaguard = 795.6 μ m2 )

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after 9 years, the guard-banded design exhibits an even larger delay than the original one, indicating worse lifetime reliability. The above case studies reveal the guard-banding approach may not be effective to overcome ageing-induced delay degradation, because it does not consider the sensitivity of each sub-circuit or gate regarding the BTI effect. In order to promise an improved lifetime reliability, one can select the guard-band based on the worst-case degradation, considering different circuit workloads and operational environments, although this would cause larger-than-necessary overheads [6]. The costs could be greater for sub-40-nm CMOS technologies, where larger guard-bands are needed to compensate for the delay shift caused by the coaction of NBTI and PBTI, due to the adoption of high-k materials [7]. Therefore, it is necessary to develop alternative or complementary approaches for the guard-banding method, to realize greater lifetime improvements with less overheads. Due to the simplicity of the guard-banding technique, it is suggested any other approaches should be compared with guardbanding to validate the effectiveness [8].

5.4.2 Library Re-characterization In Sect. 5.3.1, we have described a basic synthesis flow, where two-dimensional look-up tables (LUTs) about input transition time (tin ) and output capacitance (Cout ) are typically used to characterize a cell of the library for technology mapping. Because some parameters of a cell, such as delay and power, are affected by the process, voltage and temperature (PVT) variations, cell library designers often characterize a library under different PVT corners and provide multiple library files, in practice. A variation-aware synthesis process can therefore be performed by applying the re-characterized library, and the cell delay (or power) can be measured by searching a new LUT. The BTI effect causes time-dependent variations and varies cell propagation delay. Thus, the idea of library re-characterization is possibly used to prevent BTI-induced timing violations at synthesis stage. Ageing-aware library characterization replaces the intrinsic delay of each cell with the post-ageing delay. Hence, a circuit is synthesized by searching the design space of post-ageing delay rather than the delay at time-zero, as shown in Fig. 5.8. In this way, the timing constraint can be satisfied, even for an aged circuit, guaranteeing the lifetime reliability. Additionally, the re-characterized library can also be used to estimate the post-ageing delay after a certain amount of time for a circuit. In order to characterize a cell library considering BTI, the post-ageing delay for each cell has to be predicted first. This can be done by using a BTI analytical model, such as Eq. 5.3. Nevertheless, the BTI effect is workload-dependent, and different devices of a circuit may thereby suffer from different stress and degradations. For example, considering a buffer made by connecting two identical inverters in series, only one can be under the NBTI or PBTI stress at any time, giving different stress duty cycles for the two devices. In such a case, multiple LUTs are required to measure the post-ageing delay for one cell, considering all possible workloads. This

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Delay Time-zero Post-ageing tclk Target design

Area Fig. 5.8 Synthesis by using a re-characterized library for ageing

a = 0 a = 0.5 0.5 rise delay (ns)

0.6 0.3 0.4 0.1 0.2 4 0 2

0.2 tin (ns)

0.4

0

·10−2

Cout (pf)

Fig. 5.9 Post-ageing rise delay LUTs for different stress duty cycles of an inverter

gives an additional dimension about BTI stress duty cycle α to the original LUTs, performing a three-dimensional LUT to compute the aged propagation delay Daged , as given in Eq. 5.5. Daged = f (tin , Cout , α)

(5.5)

To generate three-dimensional LUTs and re-characterize a library, aged cell delay needs to be measured for multiple values of α. In Fig. 5.9, the post-ageing rise delays of a 65-nm CMOS inverter after 10 years are computed to generate the new LUTs for two different α, 0 and 0.5. For the case of α=0, it can be considered that this

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1.5

15

1.4 10

Percentage error (%)

Delay measured by LUTs (ns) Delay computed by model (ns)

inverter does not suffer from the NBTI stress, and thus the same LUT as the one of time-zero (Fig. 5.2) is used to measure the rise delay. If α increases, a new LUT that considers the BTI-induced delay shifts can be applied, as shown in Fig. 5.9. The library re-characterization technique gives extra entries about α to search for the aged delay. Thus, one significant question is to determine a suitable discretization resolution or an appropriate number of entries for α in other words, considering the trade-off between accuracy and library size [9]. For the value of α falling between or outside of the table data, the corresponding post-ageing delay can only be estimated by interpolation or extrapolation, which may not be accurate. Hence, more entries of α are required to maintain a higher accuracy. However, more sampling points significantly increase the size of the LUTs, which may make this approach infeasible for industrial-scale libraries with thousands of cells [9]. To demonstrate this circumstance, the c1355 circuit is synthesized by applying a recharacterized library, given different discretization resolutions. For each case, we estimated the circuit delay after 10 years by searching the three-dimensional LUT and compared it with the delay calculated by the BTI model (Eq. 5.3). Figure 5.10 presents the post-ageing delays measured by the three-dimensional LUTs and the percentage errors for different numbers of entries. As can be seen, the post-ageing delay is underestimated by searching the ageing-aware LUTs, compared with that computed by the BTI model, but the error can be reduced by using more entries for α. In this example, the error can be reduced to 5.79% with seven entries for α, which causes a seven times bigger table size than the original one. Therefore, it is important to determine a reasonable number of entries for α considering the accuracy and library size. In addition, different interpolation methods to estimate the intermediate delay between two table entries may also affect the accuracy. The workloadbased library re-characterization technique has been studied in several previous

1.3 2

3

4 5 6 Number of entries for α

7

5

Fig. 5.10 Post-ageing delay and percentage error by using the three-dimensional LUT library for different discretization resolutions: we give the entries evenly spaced between 0 and 1 and used nearest-neighbour interpolation to estimate the delay for the α falling between two adjacent entries.

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works [10–12], but none of these works has discussed how the discretization resolution or the interpolation method is determined. In order to apply the library re-characterization method in practice, further exploration and study about these problems may be needed to maintain a good accuracy in an acceptable library size. To combat the BTI effect and obtain the smallest library size, the cell library can be characterized only considering the worst-case degradation. Therefore, the intrinsic cell delay of the original library is replaced by the worst case postageing delay. The worst case post-ageing delay is computed assuming that all PMOS/NMOS devices suffer from NBTI/PBTI stress all the time (α = 1), given in Eq. 5.6. In this way, the aged delay can be measured by searching a two-dimensional LUT of tin and Cout , and the new library therefore has the same size as the original one of time-zero. worst Daged = f (tin , Cout , α)|α=1

(5.6)

In order to evaluate the efficiency of the library re-characterization technique, we compared the circuits synthesized by using the re-characterized library with those guard-banded for ageing, in Table 5.2. All cells of the library were characterized considering the worst case BTI degradation for 10 years. For guard-banding, the timing margin was added based on the worst case percentage degradation for 10 years. Both techniques were applied to ensure the circuits are working properly with the target delays in 10 years. As can be seen from Table 5.2, both techniques lead to the very similar area and power, to realize the same lifetime for a circuit. The library re-characterization can save a small amount of area/power for some circuits, compared with the guard-banding method, but it causes more area/power for the rest. These results indicate the ageing-aware library characterization is not more efficient than the guard-banding approach. This can be explained as follows. According to Figs. 5.4 and 5.8, the design with the expected lifetime is found by searching the area-delay and area-post-ageing delay curves, for the guard-banding and library re-characterization methods, respectively. These two curves represent the trade-offs between delay and area at the different time, for the design space provided by the synthesis process. In fact, both techniques locate the target design in the same design space. As shown in Eq. 5.4, the lifetime of a circuit is determined by the post-ageing delay. Accordingly, to realize the same lifetime reliability, the designs optimized by the guard-banding and library re-characterization techniques would generally have the same post-ageing delay. As these two techniques work in the same design space, other parameters produced by these techniques, including area and power, are thereby similar. The above results show the library re-characterization technique is not more efficient than the guard-banding method regarding the lifetime improvement. In addition, it requires changes to a cell library and therefore is more complicated. For these reasons, the library re-characterization cannot be used as an alternative approach to guard-banding. However, the re-characterized library may be feasible to provide a fast gate-level ageing estimation and therefore is still useful. To characterize a library for ageing estimation, it is important to determine a reasonable

Target delay (ns)

1.92 1.65 1.7 1.53 2.03 1.93 2.76 2.19 11.61 2.85

Circuit

c432 c499 c880 c1355 c1908 c2670 c3540 c5315 c6288 c7552

Guard-banding Area (μ m2 ) 292.24 843.44 561.60 800.28 692.64 921.44 1435.72 2253.16 4083.56 3047.72 Power (mW) 0.073 0.463 0.165 0.440 0.321 0.353 0.511 1.019 2.865 1.499

Re-characterization Area (μ m2 ) Area sav (%) 277.16 5.16 874.64 −3.70 560.04 0.28 806.00 −0.71 694.72 −0.30 923 −0.17 1431.04 0.33 2252.64 0.02 4090.84 −0.18 3045.12 0.09 Power (mW) 0.07 0.481 0.165 0.443 0.315 0.359 0.504 1.029 3.010 1.484

Table 5.2 Comparison of circuit area and power by guard-banding and library re-characterization techniques for ISCAS’85 benchmark Power sav (%) 4.74 −3.89 0.36 −0.71 1.96 −1.64 1.29 −0.96 −5.03 1.01

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discretization resolution for BTI stress duty cycle to trade-off between accuracy and library size, as has been discussed in this section. Further exploration is needed to resolve this problem.

5.4.3 Ageing-Aware Transformation As has been defined in Eq. 5.2, the post-ageing delay of a signal path is given by the sum of the intrinsic path delay Di and the delay degradation Di . Thus, the lifetime can be increased by aggressively reducing Di , if Di can keep the same. This can be realized by transforming the original circuit into an equivalent circuit that has the structure or gates less sensitive to the BTI effect. As the degradation reduction transformations are not provided by current synthesis tools, new optimization techniques are required to be incorporated. This leads to a new design space that suffers from smaller degradations, compared with the one produced by the existing synthesis process, as shown in Fig. 5.11. The ageing-aware transformations can be incorporated in different optimization phases of a synthesis process, shown in Fig. 5.3. Based on the step that the transformation is performed at, these methods can be categorized into logic restructuring, ageing-aware technology mapping and gate-level optimization.

5.4.3.1

Logic Restructuring

At the logic-level phase of a standard synthesis process, a circuit is represented by a set of logic expressions. By definition, a function can be performed by different

Delay

Time-zero Post-ageing (Original) Post-ageing (Optimized)

tclk Degradation reduction

Transformations

Area Fig. 5.11 Logic and gate transformation for BTI mitigation

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logic structures, which may have different BTI stress duty cycles at some internal nodes. Motivated by this, the original logic structure of a circuit may be changed to an equivalent structure that suffers from less BTI degradation. According to Eq. 5.3, the amount of BTI degradation is related to the stress duty cycle α, which represents the ratio of the stress time to the total. For the NBTI/PBTI effect, a PMOS/NMOS device is stressed during the on state. Thus, α can be determined by the signal probability (SP) of 0 and 1, for NBTI and PBTI, respectively. A PMOS/NMOS transistor that has a smaller SP of 0/1 may potentially suffer from less BTI stress, causing a smaller degradation. For this reason, simultaneously mitigating NBTI and PBTI at the logic level is not possible, because a structure reducing the SPs of 0 and the NBTI stress at some nodes would amplify the SPs of 1 at the same nodes, causing more severe PBTI stress. Thus, one can only optimize a circuit for the more critical ageing effect. We first analyse the output SP produced by three basic logic operations – NAND, NOR and NOT – as these operations can be used to construct any complex Boolean expression. Assume a signal A is connected to the input of a NOT gate or to one of the inputs of a two-input NAND/NOR gate. The second input of the NAND/NOR gate is driven by a signal, B. Table 5.3 gives the output probabilities for all three logic operations. At this step, we can assume input SPs of 0.5, allowing us to quantify and sort the output SPs, as shown. NAND logic produces the smallest/largest SP of 0/1 at the output; NOR gives the opposite result, while the output SP of NOT is in the middle. In fact, the relationship is independent of the input SPs: consider SPout,0 produced by NAND and NOT operations is equal to SPA,1 .SPB,1 and SPA,1 , respectively, as shown. SPA,1 .SPB,1 is smaller than (or at most equal to) SPA,1 , as the signal probability cannot be greater than 1. Similarly, the output probabilities of any two of the three operations can be compared in this way, and the relationship shown in Table 5.3 will still hold. Therefore, a PMOS/NMOS transistor driven by a NOR/NAND gate is more likely to have a higher probability of NBTI/PBTI stress, assuming the same input SPs for the NOR/NAND gate. To more clearly demonstrate the fact discussed above, several ISCAS’85 circuits were implemented by different cells: a NAND-INV structure indicates the circuit is constructed from NAND gates and inverters only, and a NOR-INV structure means it only consists of NOR gates and inverters. The percentage degradations after 10 years for both implementations of a circuit are evaluated, in Fig. 5.12.

Table 5.3 Output SPs for different logic operations SPout,0 Sorted (SPA/B =0.5) SPout,1 Sorted (SPA/B =0.5)

NAND SPA,1 .SPB,1

NOT SPA,1

Smallest (0.25) SPA,0 + SPB,0 −SPA,0 .SPB,0 Largest (0.75)

Mid (0.5)

NOR SPA,1 + SPB,1 −SPA,1 .SPB,1 Largest (0.75)

SPA,0

SPA,0 .SPB,0

Mid (0.5)

Smallest (0.25)

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Percentage degradation (%)

a 24

NAND-INV NOR-INV

23.09

22.94

22

20.09

19.71

20 18.26

18.35

17.84

18

17.26

16 c432

c499

c880

c1355

Circuit

Percentage degradation (%)

b 2.5

2.37

NAND-INV NOR-INV

2.26 2.08

2

1.83 1.64

1.77 1.65

1.72

1.5 1 c432

c499

c880

c1355

Circuit Fig. 5.12 10-year percentage degradations for NAND-INV and NOR-INV structures. (a) NBTI effect. (b) PBTI effect

The percentage degradation is given by the amount of degradation divided by the intrinsic circuit delay. As can be seen, a NAND-INV structure exhibits less percentage delay shift for NBTI but greater delay shift for PBTI, compared with the NOR-INV implementation of each circuit. The results support the theory shown in Table 5.3 that NOR/NAND operation leads to higher stress probabilities of NBTI/PBTI, and thereby produces more NBTI/PBTI degradation. The above observation indicates NAND/NOR operations are less sensitive to the NBTI/PBTI effect. Therefore, NBTI and PBTI can be mitigated by removing the NOR and NAND operations, respectively. This strategy is also applicable to more complex logic expressions. For NBTI mitigation, the Boolean expression of a BTI-critical node (BCN) can be represented in the form of an inverted sumof-products (SOP) (ISOP), shown in Eq. 5.7a, assuming the logic of the node is given by the sum of p products and each product contains qi elements. A node is considered to be BTI-critical, if the path it is located on may become critical and

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cause timing violations during the target lifetime due to BTI. Restructuring the logic of a certain node would affect all logic that is driven by this node. Thus, to keep the function unchanged, all logic driven by nin , shown in Eq. 5.7b, also needs to be restructured afterward. Only the logic of the BCNs would affect the circuit lifetime and is necessary to be restructured. Thus, the product terms in the inverted SOP are divided into two groups, if possible: one contains the BTI-critical nodes (ncrit ), and the other includes all non-critical nodes (nncrit ). Each group is then formed into a new inverted SOP, shown in Eqs. 5.8a and 5.8b. The output node of the new inverted SOP that contains the BCNs is then added into the set of BCNs. To maintain the logic function, the two restructured inverted SOPs are connected by an additional AND operation, which can be merged with the driving logic, given in Eq. 5.8c. As the original NOR operation between the two groups of product terms is removed, each restructured inverted SOP logic will have a smaller output SP of 0, potentially reducing the NBTI stress duty cycle for the driving transistor. Original logic representation (NBTI mitigation): ⎧ p  qi ⎪

⎪ ⎨ n =¬ ( node(i, j )) in i=1 j =1 ⎪ ⎪ ⎩ nout = f (nin )

(5.7a) (5.7b)

Restructured logic representation (NBTI mitigation): ⎧ q1i p1  ⎪ ⎪

⎪ ⎪ ⎪ ncrit = ¬ ( node1 (i, j )), ⎪ ⎪ ⎪ ⎪ i=1 j =1 ⎪ ⎨

where {node1 } ∩ BCN s = ∅ (5.8a)

i

q2 p2 

⎪ ⎪ ⎪ nncrit = ¬ ( node2 (i, j )), ⎪ ⎪ ⎪ ⎪ ⎪ i=1 j =1 ⎪ ⎪ ⎩ nout = f (ncrit .nncrit )

where {node2 } ∩ BCN s = ∅ (5.8b) (5.8c)

An example is given by using the above logic restructuring method: an original circuit is shown in Fig. 5.13, which includes three BCNs – n1, n4 and n6. Equation 5.9 gives the logic expressions of the example circuit, which can be restructured for NBTI mitigation, shown in Fig. 5.14 and Eq. 5.11. As can be seen, the Or-AndInvert (OAI) logic is split into two NAND operations, one of which contains the BCN, n1, and the other is not BCN related. The optimized root logic, merging the original NOR expression with an AND operation, is performed as an And-OrInvert (AOI) logic gate. More NAND gates are used in the restructured circuit, as the NAND operation produces a smaller probability of logic zero. Assuming 0.5 SP on each of the circuit input (n1, n2 and n3), the SPs of node n4 and n41 are computed in Eqs. 5.10 and 5.12, respectively. As can be seen, SPn4,0 is reduced from 0.375 to 0.25 at node n41 .

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BTI-critical path

OAI NOR

n1

n4

n2

n6 n5

n3 Fig. 5.13 Example circuit for logic restructuring Fig. 5.14 Restructured design for the example circuit of Fig. 5.13 (NBTI mitigation)

BTI-critical path

NAND

n1 n3

AOI

n41 NAND n42

n5

n6

n2

Original logic of the example circuit (NBTI mitigation): ⎧ ⎪ ⎪ ⎨n4 = n1.n3 + n2.n3 n6 = n4 + n5 ⎪ ⎪ ⎩n1, n4, n6 ∈ BCN s SPn4,0 = SPn3,1 .(SPn1,1 + SPn2,1 − SPn1,1 .SPn2,1 ) = 0.375

(5.9)

(5.10)

Restructured logic of the example circuit (NBTI mitigation): ⎧ ⎪ n41 = n1.n3 ⎪ ⎪ ⎪ ⎨n4 = n2.n3 2 ⎪ n6 = n41 .n42 + n5 ⎪ ⎪ ⎪ ⎩ n1, n41 , n6 ∈ BCN s

(5.11)

SPn71 ,0 = SPn1,1 .SPn3,1 = 0.25

(5.12)

The restructuring process is similar for mitigating PBTI, but the logic of each BCN is represented by an inverted product-of-sums (POS), instead of an inverted SOP. The inverted POS is split into two inverted POS expressions based on the BCNs, shown in Eqs. 5.13a, 5.14a, and 5.14b. An OR operation is merged with the root logic, to ensure the correct function, given in Eq. 5.14c. Again, the example circuit of Fig. 5.13 is optimized to mitigate the PBTI effect, and the logic expressions are given in Eq. 5.15. The restructure circuit and the Boolean expressions can be seen in Fig. 5.15 and Eq. 5.17, respectively, where more NOR operations are used

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131

NOR

NOR

n41

n2

n6

n42 INV

n5

n3

Fig. 5.15 Restructured design for the example circuit of Fig. 5.13 (PBTI mitigation)

and SPn4,1 is reduced from 0.625 to 0.25 at node n41 , assuming 0.5 SP for all inputs of the circuit, according to Eqs. 5.16 and 5.18. Original logic representation (PBTI mitigation): ⎧ ⎪ ⎪ ⎨ ⎪ ⎪ ⎩

i

p q  nin = ¬ ( node(i, j ))

(5.13a)

i=1 j =1

nout = f (nin )

(5.13b)

Restructured logic representation (PBTI mitigation): ⎧ q1i p1 ⎪ ⎪  ⎪ ⎪ ⎪ ncrit = ¬ ( node1 (i, j )), ⎪ ⎪ ⎪ ⎪ i=1 j =1 ⎪ ⎨

where {node1 } ∩ BCN s = ∅

(5.14a)

i

q2 p2  ⎪ ⎪ ⎪ node2 (i, j )), nncrit = ¬ ( ⎪ ⎪ ⎪ ⎪ ⎪ i=1 j =1 ⎪ ⎪ ⎩ nout = f (ncrit + nncrit )

where {node2 } ∩ BCN s = ∅ (5.14b) (5.14c)

Original logic of the example circuit (PBTI mitigation): ⎧ ⎪ ⎪ ⎨n4 = (n1 + n2).n3

n6 = n4 + n5 ⎪ ⎪ ⎩n1, n4, n6 ∈ BCN s SPn4,1 = SPn1,0 .SPn2,0 + SPn3,0 − SPn1,0 .SPn2,0 .SPn3,0 = 0.625

(5.15)

(5.16)

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Restructured logic of P CST2 (PBTI mode): ⎧  ⎪ ⎪ ⎪n41 = n1 + n2 ⎪ ⎨n4 = n3 2 ⎪ n6 = n41 + n42 + n5 ⎪ ⎪ ⎪ ⎩ n1, n41 , n6 ∈ BCN s SPn41 ,1 = SPn1,0 .SPn2,0 = 0.25 5.4.3.2

(5.17)

(5.18)

Ageing-Aware Technology Mapping

The technology mapping of a synthesis process selects proper cells from a cell library to implement a logic structure. Following the previous section about the logic-level BTI mitigation, the restructured logic expressions need to be mapped by specific logic gates to perform the circuit. In order to combat the BTI effect at the circuit level, the gates that suffer from smaller degradations have to be identified during the mapping phase. In Sect. 5.4.3.2, it has been described that a NAND/NOR operation can produce a smaller SP of 0/1, potentially reducing the NBTI/PBTI stress. However, the stress duty cycle α is determined by not only the SP but also the transistor-level schematic of a logic gate. Specifically, considering multiple stacking transistors connected in series in a logic gate, the one closest to the output is stressed only if all the ones further from the output are in an on state and therefore has a smaller α [13]. For example, Fig. 5.16 shows α for each of the transistors in a 2-1 OAI cell. As can be seen, α of the transistor MP2 is determined by the SPs of the two inputs, A and B, while α of the transistor MN3 is given by an expression related the SPs of all the inputs, because of the stacking effect. Therefore, Eq. 5.3 can be rewritten considering the stacking effect, to quantify the BTI-induced delay shift for a gate, given in Eq. 5.19. D(t) = K.D0 .α n .t n

(5.19)

where α = f (SPi : i ∈ all inputs), Due to the stacking effect, the stress duty cycle of a specific transistor may also be affected by the gate that the transistor belongs to. This might mean that the susceptibility of a restructured logic to BTI stress might not be reduced, after the logic expressions are mapped. For example, consider two Boolean expressions, OR and AND, with two inputs, A and B, and assume these expressions are implemented by NAND, NOR and NOT gates. Table 5.4 shows different implementations for each logic expression and compares the NBTI stress duty cycles of the internal node X (αX,nbti ). In order to sort by αX,nbti , we assume 0.5 SP for the input A and give two

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Vdd

A

NBTI (pull-up network):

MP1

αP1 = SPA,0 C

αP2 = SPB,0.SPA,0

MP3

αP3 = SPC,0 B

MP2 Out C

PBTI (pull-down network):

MN3

αN1 = SPA,1 αN2 = SPB,1 αN3 = SPC,1.(1 − SPA,0.SPB,0) A

MN1

B

MN2

Fig. 5.16 Transistor stress duty cycles for a 2-1 OAI cell Table 5.4 Internal node stress duty cycle for different implementations OR

AND

Implementation SPX,0 Stacking effect at node X? a X,nbti

Sorted a X,nbti SPB,1 =0.4 (SPA =0.5) SPB,1 =0.6

SPA,1 + SPB,1 −SPA,1 .SPB,1 No SPA,1 + SPB,1 −SPA,1 .SPB,1 Larger (0.7) Larger (0.8)

SPA,1

SPA,1 .SPB,1

No

No

No

Yes

SPA,1 .SPB,1

SPA,1

SPA,1 .SPB,0

SPA,1 Smaller (0.5) Smaller (0.5)

SPA,1

Smallest (0.2) Largest (0.5) Mid (0.3) Mid (0.3) Largest (0.5) Smallest (0.2)

different values (0.4 and 0.6) for SPB,1 . As can be seen, αX,nbti is equal to SPX,0 if there is no stacking effect. In these cases, a NOT gate produces less NBTI stress than a NOR (in the case of OR logic), while a NAND gate leads to less stress than a NOT (in the case of AND logic). These values are independent of the input SPs and are consistent with those in Table 5.3. However, the rank is determined by the input SPs if there is a stacking effect on the internal node. Thus, although removing the NOR operation helps to reduce SPX,0 , reduction of the NBTI stress may also depend on the circuit structure and the SPs for the entire circuit, which are unknown at the logic level. For this reason, we refer the logic structure produced by the logic

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restructuring process of Sect. 5.4.3.1 as a Candidate structure, which needs to be validated during the technology mapping phase. As has been mentioned at the beginning of Sect. 5.4.3, the intrinsic delay of an optimized circuit has to be close to that of the original circuit, when the BTI degradation is reduced, because the lifetime is determined by the sum of the intrinsic delay and the delay shift. Mapping a restructured logic expression may change the intrinsic circuit delay, but it is possible to eliminate any negative slacks during the following gate-level optimization step, shown in Fig. 5.3. Nevertheless, if a large delay increase is caused at the mapping phase, a great area will be costed to remove the negative slack. In such a case, a two-pass procedure may be used to realize a good trade-off between circuit timing, area and lifetime. The two-pass procedure was initially proposed for the low power-driven technology mapping [14]. It includes a forward pass to optimize circuit power or area in topological order from the inputs to the output, and a backward pass performed in a reversed topological order, to check circuit timing and reject some decisions that may cause timing violations. Due to some similar characteristics between power consumption and BTI degradation (for instance, both depend on circuit workload), many BTI mitigation techniques have been borrowed from power reduction techniques [15]. Therefore, a two-pass procedure may be applicable when lifetime, area and timing are considered together during the mapping phase. For an ageing-aware technology mapping, the forward pass would find the candidate circuit structure for all sub-circuits of a BTI-critical path. In order to minimize the BTI degradation, a signal path should be divided into as many subcircuits as possible, so that more sub-circuits can be optimized. In such a case, each sub-circuit would have the minimum number of transistors/gates. For this reason, each sub-circuit should have a circuit depth equalling to 2. This is because changing a gate consequently implies the need to restructure the one that is driven by this gate. Note here the circuit depth is defined by the maximum number of transistors, instead of the maximum number of gates, of all paths in a sub-circuit, because the input signals of some complex gates may be delivered through multiple transistors to the output nodes. For instance, the circuit depth of an AND gate is considered to be 2, if it is made by following a NAND gate with an inverter. In Fig. 5.17, an example is given, where two sub-circuits in a path overlap with each other. These

Sub-circuit1

Sub-circuit2

BTI-critical path NAND OAI

Fig. 5.17 Sub-circuits of a signal path

NOR

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Start

Find candidate structure for current sub-circuit

Same circuit depth?

no

Next subcircuit (forward)

yes a reduced?

no

yes Update current sub-circuit structure

Entire circuit remapped?

no

End Fig. 5.18 Forward pass of the ageing-aware technology mapping

sub-circuits will be optimized in topological order from the inputs to the output, during the forward pass. An algorithm for the forward pass of the ageing-aware technology mapping is given in Fig. 5.18. During each iteration, the candidate structure for a sub-circuit is first found by using the logic restructuring technique of Sect. 5.4.3.1, and is then implemented from the cells of a library. The candidate circuit structure is validated and is considered to be lifetime optimal if it satisfies the following two conditions: (1) The candidate structure for a sub-circuit has the same circuit depth as the original, which is equal to 2, as mentioned before. This avoids the risk that extra logic gates are added to a BTI-critical path, resulting in an increased path delay and degradation. Although the increased delay and degradation can be eliminated at the following backward pass and gate-level optimization steps, a large area cost will be incurred if many extra gates are put in to the BTIcritical paths. In addition, the amount of degradation for a gate is dependent on the input/output transition, because the pull-up and pull-down networks are affected by NBTI and PBTI, respectively, which causes different degradations. Putting in additional gates to a path may change the transitions for the rest gates

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of a signal path. In such a case, BTI stress or degradation for an entire path needs to be evaluated during each iteration, largely increasing the computational complexity. (2) The stress duty cycle α of the internal node of the sub-circuit is reduced. As has been mentioned in this section, the logic restructuring lowers the SP on a certain node, while the stress duty cycle may or may not be reduced, depending on the transistor structure of the gate. Thus, α of the node needs to be computed after remapping to verify the effectiveness. If the above conditions are met, the original sub-circuit is replaced by the remapped candidate circuit structure for the minimal degradation design. Otherwise, it should be considered that the mapping phase has failed to find an improved circuit structure for the sub-circuit in terms of lifetime reliability. The above steps are repeated until the sub-circuits of all BTI-critical paths are mapped, or not. After the forward pass, we have two versions of a circuit: one has the original structure, and the other has an optimized structure to minimize NBTI or PBTI degradation. As the forward pass only determines the circuit structure, rather than the size of each device, the sizes of all gates in the remapped circuit structure need then to be determined. Because the original circuit is produced by commercial synthesis tools, it can be considered that the original circuit can satisfy the given timing and area constraints. Therefore, the remapped gates can be sized based on the timing or area of the original circuit. For example, the area of all original sub-circuits can be recorded first. Each remapped sub-circuit is then sized to have a similar area to the original. This can be done by using a standard synthesis tool and setting the area constraint equal to the area of the original sub-circuit. The restructuring process may add additional gates to the non-critical paths, as some logic, such as at node n4 in Fig. 5.13, is split into two operations at n41 and n42 in Fig. 5.14. In other words, the total gate count of a remapped sub-circuit is higher than that of the original subcircuit. Thus, by giving a similar area to the remapped circuit, an increased delay can be expected, because of smaller transistors, compared with the original circuit, which may produce increased delay or even negative slacks. The negative slack or increased delay can be used to decide if a remapped sub-circuit can finally replace the original one during the backward pass, as follows. The algorithm for the backward pass is shown in Fig. 5.19. Because eliminating a greater negative slack would cause a bigger area overhead during the following gate-level optimization stage, the backward pass ensures the overall negative slack induced by the mapping phase in an acceptable range. In specific, the signal arrival time at the output of each remapped sub-circuit (tremap ) is examined and compared with that of the original sub-circuit (torig ). A constant t is used to restrict the delay increases produced by the remapped sub-circuits in a reasonable range. In this way, any remapped sub-circuit, in which tremap is not t higher than torig , is selected to construct the circuit. Otherwise, the original sub-circuit is chosen. The above steps are repeated until all remapped sub-circuits are validated. Finally, the remaining negative slacks can be eliminated, and the circuit delay can be restored by using a

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Start Check torig and tremap for current sub-circuit

tremap ≤

no

torig + Δt?

Next subcircuit (backward)

yes Use remapped sub-circuit for final design

Entire circuit checked?

no

yes Restore circuit timing (Gate-level optimization)

End Fig. 5.19 Backward pass of the ageing-aware technology mapping

gate-level optimization in a commercial synthesis tool, such as gate resizing. In this way, the restructured logic structure would not be altered. The above technology mapping technique was applied to the ISCAS’85 benchmark circuits, to evaluate the effectiveness. Specifically, each circuit was initially synthesized with Synopsys Design Compiler and was then restructured and remapped to combat the BTI effect. Considering the delay increase caused by the ageing-aware technology mapping, the incremental mapping of Design Compiler was finally used to ensure the intrinsic delay of an optimized circuit is similar to that of the original design. For each circuit, the clock period tclk is set to cause a 10-year lifetime, as an example, for the original design, allowing us to compute the lifetime improvement for the optimized design. Table 5.5 gives the area overheads and lifetime improvements by using the above technology mapping method. The constant t is set to be 0.1 and 0.5 ns, to study how different value of t would affect the performances. For the case of t equal to 0.1 ns, 35.58% lifetime improvement on average is realized with a cost of 0.69% area overhead. For several circuits (c1908, c2670, c3540 and c5315), no transformation has been made, because all possible changes performed on these circuits cause more than 0.1 ns delay increase and are thereby rejected during the backward pass. By giving

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Table 5.5 Circuit area and lifetime by the ageing-aware technology mapping

Circuit c432 c499 c880 c1355 c1908 c2670 c3540 c5315 c6288 c7552 Average

tclk (ns) 2.02 1.75 1.8 1.63 2.13 2.08 2.86 2.29 11.71 2.95

Original area (μ m2 ) 280.8 770.64 561.6 744.64 682.24 1193.92 1428.96 2264.6 4013.36 3136.12

Optimized (t = 0.1 ns) Area o/h Lifetime (%) inc (%) 0.37 0 1.75 4.75 1.11 152.19 1.82 −27.02 0 0 0 0 0 0 0 0 0.66 21.86 1.14 203.99 0.69 35.58

Optimized (t = 0.5 ns) Area o/h Lifetime (%) inc (%) 12.59 60.2 1.75 4.75 1.11 152.19 1.82 −27.02 1.75 54.12 0.61 −36.12 0.95 16.73 1.17 −2.92 0.66 21.86 1.14 203.99 2.36 44.78

a larger number for t (i.e. 0.5 ns), more transformations are accepted, leading to a greater lifetime improvement on average (44.78%), compared with the case of t = 0.1 ns. In such a case, the ageing-aware technology mapping may cause greater delay increases for some circuits, and thus a larger area overhead on average (2.36%) is added to restore the circuit timing. Thus, one needs to consider the design specifications and properly adjust the value of t. It is noticeable from Table 5.5 that three circuits, c1355, c2670 and c5315, exhibit even worse lifetimes for the optimized design, compared with the original circuits. This can be explained as follows. As has been mentioned, the delay increase or negative slack produced in the mapping stage is removed by using Design Compiler, which optimizes a circuit without considering the BTI effect. Hence, the intrinsic circuit delay is reduced, but the degradation may even be larger than the original design. The same circumstance may occur for the guard-banding technique and has been explained in Sect. 5.4.1. Therefore, to reduce circuit delay and also promise an improved lifetime reliability, ageing-aware gate-level optimization is necessary, as will be described in Sect. 5.4.3.3.

5.4.3.3

Gate-Level Optimization

Gate-level optimization in a synthesis process is performed as the final optimization phase following logic-level optimization and technology mapping. It attempts to meet the exact timing/area constraint by applying proper gate-level transformations, like gate resizing, gate splitting, etc. An ageing-aware gate-level optimization not only ensures the given area/timing constraint can be met but also aims to minimize the BTI degradation.

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Traditional gate-level optimization often employs a sensitivity-based approach to identify the more effective transformations for constraint satisfaction. Delayarea sensitivity (SD ), represented by the fraction of delay reduction over area increase for a gate-level transformation, is used as a standard metric for the trade-off between circuit area and timing [16]. The transformation with the biggest delay-area sensitivity is applied in turn until the timing constraints are met. The optimization aims to add as small as possible an area to satisfy the timing specifications. While this technique does not account for the impact of BTI, degradation-area sensitivity (SD ) was proposed to identify the transformation that can give the greatest degradation improvement per unit area increase, in a previous paper [17]. Since the degradation is proportional to the intrinsic delay according to Eq. 5.3, the gate-level transformation with the highest SD would also favour circuit delay reduction. Thus the timing constraint would be met eventually, at the cost of more area. However, the degradation-area sensitivity may not be feasible, if the budget for the area is limited. In order to simultaneously reduce the intrinsic delay and BTI-induced degradation with a reasonable area cost, a sensitivity metric that combines both SD and SD may be used. A new metric related to both sensitivities to realize any customized area/timing constraints is given in Eq. 5.20, where Ccons is a constraintrelated coefficient, determined by the intrinsic circuit delay D, delay constraint Dcons , area A and area constraint Acons . w is a weight, indicating the influence of SD on the combined sensitivity, Scomb . The value of w is adjustable to satisfy any given constraints, as will be described later. Scomb = Ccons .w.SD + SD

(5.20)

where Ccons = max(0,

Acons A

1−

−1 Dcons D

)

For a better understanding of Eq. 5.20, consider the characteristics of Scomb under three scenarios: Scenario 1: A circuit has an area A very close to or bigger than Acons , while the delay D is much greater than Dcons . In this case, Scomb is dependent mainly on SD , since Ccons tends to zero. This situation can be interpreted as follows: if little area is left to accomplish a relatively big delay decrease, the optimization should be dedicated to reducing the delay with as small an area increase as possible; Scenario 2: At the other extreme, D is nearly equal to Dcons , but the difference between A and Acons is big. Ccons tends to infinity, and Scomb is thereby determined by SD . In this case, the remaining area should be used to mitigate the degradation, if the timing constraint has been met; Scenario 3: If neither of the above holds, Ccons is a finite number. Thus Scomb is determined by both SD and SD , indicating both delay and degradation are considered in the transformation.

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Start Initialize w Identify critical and BTI-critical paths

Compute Scomb for all transformations Find transformation with the greatest Scomb no

D≤ Dcons? yes Acons ≥ A?

Decrease w, and restore the circuit

no

yes End

yes

Acons A≤ e?

Increase w, and restore the circuit

no

Fig. 5.20 Gate-level optimization to minimize BTI effect under given constraints

In summary, Eq. 5.20 can be rewritten as follows:

Scomb

⎧ ⎪ ⎪ ⎨SD , = Ccons .w.SD , ⎪ ⎪ ⎩C .w.S cons D + SD ,

Acons Dcons A −11− D Acons Dcons A −11− D

(5.21)

otherwise

Figure 5.20 shows an optimization algorithm using the above sensitivity metric. Firstly, the weight w from Eq. 5.20 is initialized to a finite number. The initial value of w does not matter, since it can be adjusted in the remaining steps. However, a greater w indicates SD has a stronger influence on Scomb , and the gate-level transformation with the biggest SD is more likely to be applied. In such a case, the overall optimization would bring about less degradation but more area. Secondly, the critical path, where the path delay is D, needs to be identified. Additionally, because Scomb can be determined by both SD and SD , the path that may become critical due to BTI after a certain time, or the most BTI-critical path, is identified as well,

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if it is different from the critical path at time-zero. Afterward, Scomb for all possible transformations for the critical/BTI-critical path is computed, and the transformation with the highest Scomb is applied. The above steps are repeated until Dcons is met. Finally, the circuit area needs to be measured to see whether Acons is satisfied. A predefined constant  is used to restrict the acceptable range of area: if the actual area does not lie in [Acons − , Acons ], w would increase or decrease, depending on the exact value of A, and the design is restored to the initial state, where any gatelevel transformations have not yet been applied. A maximum iteration count can be set to give a reasonable runtime, if necessary. The gate-level optimization technique described above is used to further improve the lifetimes, for the circuits that have been optimized at the logic-level and mapping phases, shown in Sect. 5.4.3.2. As the gate-level optimization approach can mitigate BTI under given constraints, two upper limits of area are given: (1) Acons = 0, indicating to use the least possible area to satisfy the timing constraint and optimize the lifetime reliability, if possible, and (2) Acons = +5%, where the optimized circuit is required to be no more than 5% larger in area than the original. According to our observations, a 5% area increase is more than sufficient to remove all negative slacks, for these circuits. Thus, the remaining area can be used to further increase the lifetime. Table 5.6 presents the area overheads and lifetime improvements by applying BTI mitigation techniques at all optimization steps of a synthesis process. As can be seen, given the least possible area (Acons = 0), the BTI mitigation techniques realizes a 29.68% lifetime improvement on average, with only a 1.03% area increase. However, the lifetimes are worsen or unchanged after the optimizations for some circuits (c432, c1355, c1908 and c5315). Therefore, the optimization methods fail to improve the lifetimes of these circuits, as the given budget for area is small.

Table 5.6 Circuit area and lifetime by applying BTI mitigation techniques at all logic-level, mapping and gate-level optimization phases

Circuit

tclk (ns)

c432 2.02 c499 1.75 c880 1.8 c1355 1.63 c1908 2.13 c2670 2.08 c3540 2.86 c5315 2.29 c6288 11.71 c7552 2.95 Average

Original area (μ m2 ) 280.8 770.64 561.6 744.64 682.24 1193.92 1428.96 2264.6 4013.36 3136.12

Optimized (Acons = 0) Area o/h Lifetime μ m2 (%) inc (%) 12.21 4.34 −13.5 5.2 0.67 17.56 2.08 0.37 64.98 3.12 0.42 −15.37 9.36 0.78 71.62 5.2 0.76 −66.1 3.64 0.25 72.94 24.96 1.1 0 16.12 0.4 8.09 37.44 1.19 156.58 1.03 29.68

Optimized (Acons = +5%) Area o/h Lifetime μ m2 (%) inc (%) 13.52 4.81 78.02 5.2 0.67 22.25 2.08 0.37 64.98 6.76 0.91 13.32 9.36 0.78 71.62 5.72 0.84 182.17 3.64 0.25 74.1 26 1.15 71 17.16 0.43 20.72 37.44 1.19 156.58 1.14 75.48

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This can be explained as follows: according to Eqs. 5.20 and 5.21, by giving the least possible area (Acons = 0), Ccons would be zero, and Scomb is determined by SD and is independent of SD . Therefore, the gate-level optimization is performed to specifically reduce the intrinsic delay, regardless of the change of the degradation. In such a case, the BTI effect is not really considered, and the degradation may even be larger for an optimized circuit. For the case of Acons = +5%, the lifetimes of all circuits are improved, and a larger lifetime increase on average (75.48%) is realized, since more area is provided to mitigate the BTI effect. The average area overhead is 1.14%, less than the area increase limit(5%). Therefore, these techniques manage to mitigate the BTI effect within the given timing and area constraints. In Table 5.7, the circuit lifetimes optimized by ageing-aware transformations at all optimization phases are compared with those by guard-banding method. Synopsys Design Compiler is used to guard-band a circuit, leaving an extra timing margin. Each circuit is optimized via both techniques, given the same area constraint. As can be seen, the ageing-aware transformations causes a smaller percentage degradation over 10 years for all circuits, compared with guard-banding. Thus, these approaches mitigate the BTI effect by aggressively reducing the amount of degradation. The ageing-aware transformations give greater lifetime improvements, compared with guard-banding, with two exceptions on c432 and c5315. This is because the problem of finding the global optimal implementation during a constraint-driven synthesis process has been proven to be NP-hard [18]. Therefore, any heuristic methods to solve this problem in an affordable computational time would result in a local optimum. The ageing-aware transformations discussed in this section are based on heuristics, and thus, they may fail to provide the global optimal solution. In such a case, a conventional guard-banding technique may sometimes realize a better trade-off in terms of circuit lifetime and area, for instance, for c432 and c5315. However, the ageing-aware transformation techniques result in longer lifetimes for most of the circuits and are generally more effective than guard-banding. These

Table 5.7 Lifetime reliability of guard-banding and ageing-aware transformations Guard-banding 10 years degradation Circuit (%) c432 21.16 c499 19.1 c880 21.83 c1355 19.2 c1908 20.06 c2670 20.13 c3540 23.2 c5315 22.2 c6288 22.45 c7552 22

Ageing-aware transformations 10 years degradation Lifetime (years) (%) Lifetime (yrs) Lifetime inc (%) 19.485 7.824 12.89 11.059 14.156 16.724 13.057 19.183 7.214 11.477

19.2 18.7 20.22 18.85 19.27 17.23 21.32 20.23 21.57 17.61

17.801 12.225 14.908 11.332 28.217 17.162 17.410 17.100 12.072 25.658

−8.64 56.25 15.66 2.47 21.23 68.72 33.34 −10.86 67.40 123.56

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results would be expected, because the ageing-aware transformations are performed by selectively mitigating the BTI effect on the more sensitive devices. In practice, one can apply both the ageing-aware transformation and guard-banding techniques to optimize a circuit and select the more robust design. Thus, the ageing-aware transformations can be used as complementary techniques for conventional guardbanding during synthesis, to explore the best trade-off between the circuit lifetime and other parameters.

5.5 Conclusions Logic synthesis has become a significant EDA process for digital circuit design. Traditional synthesis process does not consider the CMOS lifetime reliability, which may be affected by the BTI effect. The BTI effect is believed to be the most lifetimelimiting mechanism for digital circuits. It shortens the circuit lifetime by increasing the circuit delay and eventually causing a timing violation. In this chapter, we have discussed how an ageing-aware synthesis process may be performed to combat the BTI degradation. Based on the strategies and the incorporated areas of logic synthesis, BTI-aware optimization techniques are categorized into three groups: guard-banding, library re-characterization and ageing-aware transformation. The guard-banding method improves circuit lifetime by putting in a pessimistic timing margin to compensate for BTI-induced delay increase. It can be realized by giving a smaller timing constraint during synthesis. The guard-banding method employs the existing optimization techniques of commercial synthesis tools to leave the timing margin and thus is easy to implement. However, this method focuses on the reduction of the intrinsic circuit delay, regardless of the change of the degradation. Therefore, the degradation may still be big, limiting the lifetime. The library re-characterization technique replaces the intrinsic delay of all cells of a library with the post-ageing delay, so that the timing constraint can be met, even for an aged circuit. Nevertheless, this technique does not change the design space provided by the traditional synthesis process, and the area and power costs are thereby similar to those of guard-banding. Due to its higher complexity compared with guard-banding, this technique is not suggested to be used as an alternative approach to guard-banding. The ageing-aware transformation replaces the logic structure or gates of a circuit with those suffer from less BTI stress, aggressively reducing the amount of BTI degradation. The transformations are incorporated in different optimization phases of a synthesis process. During the logic-level optimization, NBTI and PBTI stress can be reduced by removing the NAND and NOR operations, respectively. At technology mapping stage, a two-pass procedure may be used to select the gates causing less degradation and keep the timing/area overhead in an acceptable range. At the gate-level optimization phase, a sensitivity metric combined both delayarea and degradation-area sensitivities may be used to identify the most favourable transformation in terms of timing, lifetime or both. By giving enough budget for

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circuit area, the ageing-aware transformation can promise an improved lifetime for a circuit. Compared with guard-banding, the ageing-aware transformation can generally realize a larger lifetime improvement, but a conventional guard-banding technique may sometimes realize a better trade-off in terms of circuit lifetime and area, because finding the global optimum during a constraint-driven synthesis process is an NP-hard problem. Thus, it is suggested to apply the ageing-aware transformation as a complementary technique to guard-banding, by using both techniques and finding the more robust design.

References 1. Micheli, G. D. (2010). Chip challenge. IEEE Solid-State Circuits Magazine, 2, 22–26. 2. Schlunder, C., Aresu, S., Georgakos, G., Kanert, W., Reisinger, H., Hofmann, K., & Gustin, W. (2012). HCI vs. BTI?-Neither one’s out. In Reliability Physics Symposium (IRPS), 2012 IEEE International (pp. 2F–4). IEEE. 3. Micheli, G. D. (1994). Synthesis and optimization of digital circuits. Berkshire: McGrawHill Higher Education. 4. Duan, S., Halak, B., & Zwolinski, M. (2017). An ageing-aware digital synthesis approach. In 2017 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) (pp. 1–4). 5. Ebrahimi, M., Oboril, F., Kiamehr, S., & Tahoori, M. B. (2013). Aging-aware logic synthesis. In Proceedings of the International Conference on Computer-Aided Design (pp. 61–68). 6. Kang, K., Gangwal, S., Park, S. P., & Roy, K. (2008). NBTI induced performance degradation in logic and memory circuits: How effectively can we approach a reliability solution? In Proceedings of the 2008 Asia and South Pacific Design Automation Conference (pp. 726–731). 7. Kim, T. T. H., Lu, P. F., Jenkins, K. A., & Kim, C. H. (2015). A ring-oscillator-based reliability monitor for isolated measurement of NBTI and PBTI in high-k/metal gate technology. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 23(7), 1360–1364. 8. Afacan, E., Yelten, M. B., & Dündar G. (2017). Analog design methodologies for reliability in nanoscale CMOS circuits. In 2017 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) (pp. 1–4). 9. Kiamehr, S., Firouzi, F., Ebrahimi, M., & Tahoori, M. B. (2014). Aging-aware standard cell library design. In Proceedings of the Conference on Design, Automation & Test in Europe. European Design and Automation Association (p. 261). 10. Kiamehr, S., Firouzi, F., & Tahoor, M. B. (2013). Aging-aware timing analysis considering combined effects of NBTI and PBTI. In 2013 14th International Symposium on Quality Electronic Design (ISQED) (pp. 53–59). IEEE. 11. Kumar, S. V., Kim, C. H., & Sapatnekar, S. S. (2007). NBTI-aware synthesis of digital circuits. In Proceedings of the 44th Annual Design Automation Conference (pp. 370–375). ACM. 12. Abbas, H., Zwolinski, M., & Halak, B. (2016). Static aging analysis using 3-dimensional delay library. In ERMAVSS@DATE (pp. 34–37). 13. Wu, K. C., & Marculescu, D. (2009). Joint logic restructuring and pin reordering against NBTIinduced performance degradation. In Proceedings of the Conference on Design, Automation and Test in Europe (pp. 75–80). 14. Lin, B., & De Man, H. (1993) Low-power driven technology mapping under timing constraints In 1993 IEEE International Conference on Computer Design: VLSI in Computers and Processors (pp. 421–427). 15. Chen, X., Wang, Y., Yang, H., Xie, Y., & Cao, Y. (2013). Assessment of circuit optimization techniques under NBTI. IEEE Design & Test, 30(6), 40–49.

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16. Chinnery, D. G., & Keutzer, K. (2005). Linear programming for sizing, Vth and Vdd assignment. In Proceedings of the 2005 International Symposium on Low Power Electronics and Design (pp. 149–154). ACM. 17. Gomez, A., & Champac, V. (2015). A new sizing approach for lifetime improvement of nanoscale digital circuits due to BTI aging. In 2015 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) (pp. 297–302). IEEE. 18. Chaudhary, K., & Pedram, M. (1992). A near optimal algorithm for technology mapping minimizing area under delay constraints. In Proceedings of the 29th ACM/IEEE Design Automation Conference (pp. 492–498). IEEE Computer Society Press.

Part III

Ageing Monitoring and Adaptation Techniques

Chapter 6

On-Chip Ageing Monitoring and System Adaptation Lorena Anghel, Florian Cacho, and Riddhi Jitendrakumar Shah

6.1 Introduction In modern, sophisticated electronic system on chip, system crashes, failing operations, data or state loss, degraded functionalities and silent data corruption are some of the typical failures that may occur. Depending on the type of system, some of these failures can induce catastrophic consequences, such as huge economical loss, impeach credibility, etc. Assessing reliability of systems and eventually entire products became mandatory, especially for harsh environment products, safetycritical real-time ones or health care, where the expected high performances have to be accompanied by very low failure rates (and higher availability, reliability and maintainability). On the other side, commercial mobile applications following Moore’s law continuation towards smaller and smaller size technologies are facing the energy wall issues. As a matter of fact, in the last 4 years, battery capacitances have been improved by a rough 7% while the processing performance has increased by 300% [1]. To sustain miniaturization and keep the pace with 200 billion connected devices in 2020, announced in [2], it is obvious that the energy efficiency of electronic systems has to be improved. As both dynamic and static power consumption depend on the supply voltage (VDD ), the main approaches to achieve power efficiency focus on reducing the supply voltage of scaling down technologies. One of the most prominent solutions for low-power circuits is near-threshold voltage (NTV) operation, where the operation voltage is brought close to the transistor threshold.

L. Anghel () · R. J. Shah University Grenoble Alpes, CNRS, TIMA Laboratory, Grenoble, France F. Cacho · R. J. Shah STMicroelectronics Crolles, Grenoble, France e-mail: [email protected]; [email protected] © Springer Nature Switzerland AG 2020 B. Halak, Ageing of Integrated Circuits, https://doi.org/10.1007/978-3-030-23781-3_6

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The reduced CMOS transistor’ sizes getting closer to the atomic size exacerbate the impact of variability, transient and intermittent faults. Static variability also called process variations, dynamic variability due to VDD and temperature fluctuations (PVT) and temporal variability – due to ageing – are already reported for several technologies [3]. The impact of the variability is even higher when operating near-transistor thresholds supply voltages. In advanced technology nodes, ageing has become an important source of variability, inducing an increasing degradation over time of the performances of a given circuit, leading the circuit to an irreversible unreliable condition, potentially resulting in timing and even functional failures. This degradation highly depends on how the circuit has been used during its lifetime, the history of the operation environment represented by the VDD , current levels, temperature and the applications running on the circuit (aka workload). A conventional method to compensate for such problems is to provide more safety margins (called guard bands) during circuit design steps to ensure circuit operation face to all above-mentioned variations. Adding pessimistic timing margins (or equivalent voltage margins) to guarantee all operating points under worst-case conditions is not acceptable anymore due to the huge impact on design costs, with an upward trend as technology moves further. Therefore, the usage of performance violation monitors becomes a must, as they allow decreasing the performance and voltages constraints imposed on the overall design. In addition to the reduction of design margin, adaptive voltage scaling (AVS) technique or dynamic voltage frequency scaling (DVFS) triggered by the delay violation monitors may be used to adapt dynamically the frequency and the voltage according to the operating conditions and the application needs [4]. Adaptive body bias (ABB) voltage operation is also seen as a possible solution to compensate for the variations, especially as they do not affect the power consumption of the circuit. Different approaches such as embedded performance monitors combined with adaptive voltages and/or frequency schemes became popular recently [5]. Thus, the performance degradation can be compensated and the circuit’s lifetime can be extended.

6.2 Chapter Overview The chapter is organized in four main parts. After an introduction of new aspects of main ageing mechanisms and their impacts on circuit and system delays, stateof-the-art monitors but also up-to-date optimized in situ and replica path monitors are presented in Sect. 6.3. Gains, limitations and challenges of each architecture are widely discussed in Sect. 6.4. The classic strategy of monitor insertion in digital designs is presented in Sect. 6.5. The integration of results obtained from test chips fabricated by ST microelectronics in advanced technology leads to modified insertion methodology where different sources of static and dynamic variability as well as ageing-induced effects are taken into account. Finally, state-of-the-art supply

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and bias voltage and frequency adapting techniques are presented in Sect. 6.6 and test chip results on the adaptation of system parameters triggered by monitors are illustrating the approach.

6.3 Ageing Phenomena Wear-out mechanisms in VLSI circuit are an important concern, especially with recent development of critical mission applications like automotive, avionic or space applications. Ageing effect can be observed at different hierarchical levels, i.e. system level, SoC, IP level and transistor level. One of the most critical, impacting directly the functionality of the system, is the abrupt, sudden wear-out mechanisms such as electromigration (EMG) or time-dependent dielectric breakdown (TDDB) of transistors or intermetallic oxide breakdown leading to hard failure. However, some mechanisms at device level can have a monotonous degradation; it is the case for bias temperature instability (BTI) and hot carrier injection (HCI) phenomena. These two last mechanisms play an important role and impact on performance of systems and are usually observed in the field. Although the oxide breakdown TDDB and EMG can be mitigated with adequate VDDmax/Tmax limitations and design layout restriction, BTI and HCI are impacting the digital library cell performance. Therefore, the degradation induced by ageing needs to be considered at early design stages. As a matter of fact, ageing effects cause the threshold voltage of the transistors to increase and the mobility of electrons to degrade, and hence the switching delay of gates built with these transistors increases, eventually leading to parametric timing failures when they are used in circuit complex designs. Indeed, when the delay of the circuit does not meet the timing constraints, timing errors contaminate the whole system, provoking functional failures, eventually. In order to deal with these issues, traditional approaches consist in improving the technology process trade-off between yield, performance and reliability as much as possible, by adding guard bands, as a common approach. In the guardbanding approach, timing margins are added to the combinational logic path in order to guarantee correct operation of the circuit during the operational lifetime. A pessimistic guard banding leads to performance loss, and optimistic guard banding results in a low yield and reliability of the chip. Therefore, the required timing margin needs to be accurately predicted. Figure 6.1 shows a sketch of the components of the required timing margin for IBM Power7+ processor [6]. As shown in this figure, the main components of the timing margin are uncertainty (e.g. global and local process variation), wear-out (transistor ageing) and voltage and temperature variations. The weight of the different contributors on delay is depicted in Fig. 6.2. In this figure, an example of 300 selected data paths from a reference PVT condition is shown with the contribution of different process, voltage, temperature and ageing (PVTA) conditions. Interestingly, all contributors together may affect by more than 50% the initial timing. Further to that, the path ranking is changing because the path delay is also sensitive to specific gates [7].

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6.3.1 NBTI and HCI Phenomena Transistor ageing due to bias temperature instability (BTI) and hot carrier injection (HCI) is one of the major sources of reliability loss in current technologies. BTI may occur in a similar way in PMOS and NMOS transistors (respectively named NBTI and PBTI), when an electrical vertical field appears in the channel (the gate is in strong inversion with small VDS ). In SiO2–SiON gate stack technology process, NBTI was considered as being the most important reliability issue for a long time, and PBTI was neglected due to its small effect on NMOS transistors. However, by the introduction of high-κ metal-gate technologies, PBTI becomes more significant [8]. NBTI degradation manifests as a degradation of

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linear/saturation electrical parameters of a MOS transistor, under a negative VGS (for PMOS transistor) with a high-temperature dependence. The dynamic of this phenomenon has usually a time power dependence, leading to a degradation that is monotonous over time. This degradation gets worse when increasing the temperature, but depends on the type of oxide (SiO2, SiON, HfO2, HfSiON) and its thickness [9, 10]. At device level, it is usual to quantify this degradation as an important increase of the threshold voltage and a current reduction. In general, there are two different models describing this phenomenon: (i) reaction-diffusion (RD) model [10] and (ii) trapping-detrapping (TD) model [11– 13]. Experimentally, it is usually admitted that two typical behaviours of degradation are observed: a permanent degradation occurs, attributed to interface defect due to Si-H de-bonding, and a recoverable contribution, attributed to TD or RD mechanisms. The recoverable part of the phenomenon is challenging to model. In fact, an accurate estimation of the system failure requires a very good assessment of workload pattern conditions (e.g. temperature and stress) [14]. In addition, by further down-scaling of the transistor dimensions into deca-nanometre range, the number of defects per device decreases leading to a drastic increase in the timedependent variability of BTI [15, 16]. Hot carriers (HCI) are referred to carriers which have a temperature much higher than the silicon lattice temperature. When the transistor is in saturation mode, some of the carriers become hot due to the high lateral field and they gain enough energy to overcome channel/gate oxide potential barrier (channel hot carriers) [17]. These channel hot carriers may collide with the silicon atoms in the pinch-off region and generate electron-hole pairs due to the impact ionization. In turn, interface states are generated, and as a result, threshold voltage increases, and the subthreshold slope change, the electron mobility is degraded and the saturation velocity is affected. NBTI and HCI degradation are usually assessed independently one from the other. Their respective degradations are assumed to be additive in models provided by foundries. However, in [18] it is shown that these two phenomena are interacting and their contributions should be correlated. In fact, as the degradation rate is depending on the total number of interface state sites, defects created during the two mechanisms are the same; only their respective localizations are different. It is shown through experiments that the average total (BTI + HCI) degradation is largely overestimated up to a factor of 2 if a simple additive model is used. For illustration purpose, Fig. 6.3 shows the VTH drift due to BTI and HCI coupled and decoupled effect along with simulated and measured ring oscillator (RO) frequency drift which explains the importance of combining BTI + HCI effect. The comparison between a standard approach (additive degradation of BTI and HCI) and coupled model shows that this last approach is less pessimistic and gives better prediction because PMOS HCI contribution is effectively strongly decreased. Thus, correlated BTI and HCI models should be used during the evaluation of the degradation for a better accuracy. Furthermore, wear-out-induced degradation on performance depends on the gate type. Figure 6.4 shows analysis of frequency drift of different types of ring oscillator (RO) made with different variety of logic cells. As it can be observed, variations

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Fig. 6.3 BTI and HCI coupled degradation model vs. standard additive model of VTH drift difference. The resulting RO frequency drift is compared between simulation and measurement [18]

Fig. 6.4 RO frequency drift due to ageing for different process corners and different gate cells at 125 ◦ C [19]

of RO delays due to PVT are important, and it is also noticeable that RO timing degradation is dependent on gate types used for RO design. In Fig. 6.4, ring oscillators are made of logic cells with different VTH and gate length (LL and LR mean different VTH cells and P0, P4, P10 and P16 stand for different gate length). As reported in Fig. 6.4, the relative degradation is more important for P16 gate length and higher VTH -cells implementation [19]. When assessing ageing impact at circuit level, the performance degradation is reported through VDDmin or Fmax measurements or predictions. These two parameters give the minimal supply voltage or the maximal operating frequency in absence of variations or ageing. They are usually driven by the limiting worst case extracted from data path collection with the minimal slack. A dedicated test chip (sample design) has been designed and fabricated, and VDDmin was measured before and after the ageing process performed with different temperatures and in different

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Fig. 6.5 VDDmin variation increases in a 100,000 data path circuit due to ageing in different technology corners [18]

Fig. 6.6 Variation of the contribution of data path, launch clock path and capture clock path with ageing [19]

process corners. The test vehicle is composed of roughly 100 K sample paths. Figure 6.5 shows that the correlation between the VDDmin variation and the process corner is not straightforward and is almost independent to the reference VDDmin [18]. Moreover, an important VDDmin spread is measured, while mean degradation is 25 mV, and the VDDmin shift can reach 40 mV for 200 paths sampling. This spread feature is important and needs to be considered when guard-banding design. This spread seems to be proportional to the number of worst path slack. Indeed, for a given path, sizing the worst path slack has to consider the contribution of path delay, clock launch path and clock capture path delay of a particular endpoint. All these contributions can change with ageing. Figure 6.6 [19] reports the variation of data path, clock launch and capture path with ageing, for 100 paths design. Although

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data path delay has higher contribution in slack variation, the clock skew (captureto-launch path) may change its sign in function of activity scenario or clock gating strategy and play a role for hold violations in addition to setup violations. These experimental observations underlined the importance of accurately assessing PVTA impacts on the path delays, in order to decide the type of monitor that can be used in a design, and the strategy of monitor insertion that will be developed later in the chapter.

6.4 Performance and Reliability Monitors As stated in the introductory part, timing errors induced by variability and ageinginduced phenomena can be compensated by imposing strong timing margins or the corresponding voltage supply margins. Adding pessimistic safety margins to guarantee all operating points under worst-case PVT and ageing conditions is not acceptable in many designs since it will consume all the gains of scaling with respect to performance, area and design cost. Moreover, due to the fact that the final area of the circuit can be unacceptably larger, the design flow closure can be drastically affected. To get around this limitation and further reduce the voltage margins, adaptive voltage scaling (AVS) or adaptive frequency scaling AFS [4] triggered by delay monitors is usually done. Consequently, the circuit lifetime is extended under wear-out mechanism, and the power management is more accurately handled. Various classes of monitors have been proposed in the literature. They can be split into two major classes: first of all, monitors for maximum performance violation error or pre-error detection and, second, monitors for measuring the extra-delay induced by variability or ageing.

6.4.1 Monitors for Detecting Performance Violations The first class of monitors is divided into two parts: • Monitors such as ring oscillator [20], path replica [21], tunable replica circuits [22]. These monitors are not embedded within the design; they are usually situated in specific parts of the layout, external to the design. • Embedded monitors such as Razor-I,II [23, 24], TDTB monitors [25], double sampling with time borrowing monitors (DSTB), in situ monitors (ISM) [26]. These monitors are usually inserted at identified critical endpoints in the design, such as flip-flops and latches. In the following sections, the external and embedded monitors are explained with more details.

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Ring oscillator [20] or replica path [21] aims to replicate the timing behaviour of the original circuit longest delay. Self-oscillating paths using various combinations of standard cells are made to mimic critical path frequency as shown in Fig. 6.7. After fabrication of a given chip, these paths are calibrated to match the maximum operating frequency of the target design. When delays of cells increase due to ageing or to other variations, the frequency of these self-oscillating paths changes leading to timing violations that can be detected. Tunable replica path (TRC) [22] is an advanced version of replica path circuits. Different paths are built up with different kinds of cells. Their outputs are multiplexed and one particular branch is selected to mimic critical path frequency as shown in Fig. 6.8 [22]. Degradations can be detected more accurately with respect to generic replica paths, as various cells have different effects under the same stress. Tunable replica path allows careful calibration of the circuit frequency after fabrication to match reference design’s maximum operating frequency. The output of this monitor is usually connected to time-to-digital converter (TDC) which converts timing margin into digital code. This digital code is then used by the

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controller included into a self-adapting compensation technique such as AVFS or ABB (see more details in Sect. 6.6). Critical path sensor (CPS) architecture is a combination of classic replica path monitor and double sampling technique. The timing critical paths of target design are replicated outside of design. Double sampling monitor is added at the end of the path to allow timing violation detections; see Fig. 6.9 [19]. The double sampling monitor principle has been first introduced by M. Nicolaidis [27] in 1999, and since then it has been massively used for timing error detection on combinational circuit paths. As a matter of fact, transient faults, PVT and/or ageing degradations inducing timing errors can be captured by the shadow flip-flop if the total path delay is exceeding the nominal value. The capture flip-flop will capture the correct data due to additional delay element that is specifically calibrated to cover for the typical delay degradation of a given circuit and application, PVT and ageing conditions (see Fig. 6.9). The delay degradation is detected by comparing the output of capture flip-flop with the shadow flip-flop. Mimicked critical paths show better correlation than generic replica path monitor made of various combinations of cells, because they are identical to the critical paths of design, thus having better correlations in terms of delay with target chip. One major drawback of all external monitors is related to the fact that their activity is uncorrelated from the system workload and they do not mimic the real ageing experience as the original critical path. Moreover, they do not capture the impact of the local variability neither. Therefore, internally situated monitors were proposed in the literature to overcome the above-mentioned drawback and they are preferred in designs where the sensitivity to workload and local variation is important.

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Embedded monitors coping with previous monitoring drawbacks explained above are implemented within the design and are directly linked to the circuit path delays. They are inserted in specific endpoints of the designs, usually at the end of critical and subcritical paths. Among a large choice of embedded monitors (also called ISM), it is worth mentioning the well-known error-detection monitors called Razor [23, 24]. Razor uses a special shadow latch or shadow flip-flop (FF) to detect timing failures due to setup violations on the logic stage paths. As shown in Fig. 6.10, the timing error is detected by comparing the main flip-flop data and shadow flipflop data at the output of the monitored endpoint. When the delay increases due to ageing, the shadow latch and the slave latch have different outputs as shown in timing diagram. When delay is increased, slave latch fails to capture the correct data and shadow latch captures the right data. By comparing these two signals, an error signal is activated. A meta-stability checker is set after the slave latch that solves any timing issue related to signal timing skews. When error signal is generated, the correct data from shadow latch is restored to flip-flop. In the Razor-II [24], flip-flop is replaced with level-sensitive latch which reduces area overhead. Also, only error detection is performed in the flip-flop unlike Razor-I where both error detection and correction are performed in the flip-flop. Error correction in Razor-II is done through architectural rollbacks. Another error-detection monitor was introduced in [25] and is called double sampling with time borrowing (DSTB). This approach mixes in the same design different redundant storage elements latches and/or flip-flops (see Fig. 6.11). When the path delay increases due to ageing phenomena and violates the path slack, the

Fig. 6.10 Razor-I structure and timing diagram [24]

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Fig. 6.11 Double sampling with time borrowing monitor [25]

Fig. 6.12 Transition detector with time borrowing monitor [25]

flip-flop captures a wrong value although the latch will capture the delayed correct output on its active clock level. Thus, the correct output is passed on the subsequent stages of the circuit, and at the same time, the error flag is generated and triggers correction strategies, such as voltage adaptation. This monitor implementation generates huge design effort due to the clock signal routing complexity as sometimes, timing closure can be an issue. At the same time, the latches and flip-flop strategy mixing can be considered as non-safe for critical application. Transition detector with time borrowing (TDTB) [25] uses time borrowing concept for error detection. Figure 6.12 shows the architecture. A small pulse is generated by the XOR gate whenever data transitions are occurring on the monitored path connected at D. If this pulse occurs when the latch is not transparent, the error signal does not raise. However, when D-input data arrives late due to delay degradations on the monitored path, the pulse occurs during the active phase of the

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clock (the latch is transparent), and the error signal becomes high. TDTB monitor removes metastability from data path to the error generation path which is a benefit of using TDTB, but design complexity of TDTB is high compared to other EDS circuits. The issues related to error recovery scheme implementations (i.e. error correction or rollback) can be avoided by preferring circuit failure prediction monitors [4], i.e. predicting the occurrence of the pre-error before the appearance of any error in system data and state. In this approach, the monitors raise a warning signal when late transition occurs, but the outputs are still error-free. In line with this approach, in [4] stability checker circuit was proposed which detects transitions close to the clock edge, thanks to additional delay element in the clock path. One error-prediction monitor called Canary FF [5] is shown in Fig. 6.13. It consists in sensing a given propagation path delay violation, thanks to a well-sized delay element at the input of the shadow flip-flop. A pre-error signal is raised when the value at the endpoint capture flip-flops differs from the value in the shadow flip-flop, as the resulting timing slack becomes shorter than the signed-off one. This pre-error signal is the indicator of the capture flip-flop setup timing violation. Canary FF design is easy to implement, and adding it to a certain design can be done through automation. This scheme is well suited for compensation scheme as indicator of degradation because the added delay element gives enough time to protect design from ageing and variation without failures.

6.4.2 Delay Measurement Monitors The second class of monitors includes ageing-induced delay measurement monitors [28–30]. Based on different architectures, their purpose is to detect and measure on-chip transient pulses generated by different sources of noise, such as radiationinduced pulses. They generally use a Vernier delay line for pulse width evaluation followed by a capturing circuit with edge trigger [31]. Figure 6.14 shows the principle of setting up a delay line used to measure timing difference between two transitions. It is composed of two buffer chains and D latch gates. Two-step signals

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Fig. 6.14 Circuit configuration of Vernier delay line [31]

(START and STOP) are given to the circuit, and the time difference will be measured by the Vernier delay line. Usually t1 is larger than t2, START signal is feed as clock signals to all N latches, and STOP will be connected to D input of latches. START and STOP signals race and finally STOP signal overtakes START signal. When these signals propagate through a single stage, the time difference between them, which was initially T at the input, is reduced by tr = (t1 − t2). Latches, where the time difference becomes 0 or below, store 1 and the others latch 0. Letting N denote the number of latches storing 1 and ts being the setup time of latches, the time difference T is estimated by (N − 1) tr ≤ T + ts < N t r This principle can be used to measure also the time difference between two paths, one of them being the reference path and the other one the aged path.

6.4.3 Discussions The trade-off between different kinds of monitors is explained in this section. Externally placed sensors in the intended design are suitable for easy implementation and detection of global process centring and average ageing, while internally situated monitors are better for fine-grained detection of global as well as local variation and more accurate ageing. Also, monitor failure prediction approach is better as they generate warnings prior to timing failures, giving the system enough time for correction through compensation strategies. Note that external monitors are mainly used without correlations to the real activity of the circuit (e.g. vectorless) while still trying to mimic somehow the activity of the circuit intended to be monitored, while in situ monitor alarm activation is related to the real activity of the endpoint register. This last feature can be circumvented by using large number of external monitors located both at high activity and close to timing critical hot spots. Externally situated monitors are easy to implement, they do not change the reference design netlist so the timing closure is very fast and verification steps take

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less time. Their usage is very well suited for global variation detection and is not accurate to capture local variations such as within-die, random manufacturing and circuit ageing. For illustration purpose, external critical path replicas (CPR) and CPS monitors are implemented in one of the STMicroelectronics-fabricated test chip. The reference design is considered here as being composed of three ARM microprocessor A53 with four CPR placed at strategic points within the design and one CPS. Figure 6.15 shows distribution of the three ARM frequency measurements and their correlations with CPS measurements of frequencies. The figure illustrates also the difference between CPR/CPS measures underlining the difficulties to correlate external monitors CPR with local variability and workload. As discussed earlier, internally situated monitors are more accurate in terms of global and local variation detection compared to externally situated monitors due to their localization within the design. The drawback for the in situ monitor insertion is the difficulty to close the timing and fix the critical path rankings. Indeed some initial selected set of endpoints at early physical synthesis steps or at place and route steps can become subcritical after the detailed routing steps, and at the same time, subcritical endpoints can become critical at the final steps. In that last situation, ECO loop is carried out to fulfill this new critical path monitoring. The activation of in situ monitor inserted on critical paths is another very important issue, because if the path is not activated during the workload execution, the in situ monitor cannot raise pre-error signal. In a complex SoC where multiple functional modes are available, all in situ monitors inserted on the critical paths may not be activated in a particular functional mode. This limitation can be overcome by using a combination of scan design and specific ATPG vectors that are periodically

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applied to the circuit. Therefore ISM inserted on critical paths can be activated and potential degradations can be detected. The situation of ageing monitoring by using internally situated monitors is now presented. Another test chip has been used for this purpose, consisting in a large arithmetic block composed of 2000 endpoints. This block has been characterized at design time (e.g. fresh) and also in different aged states. Figure 6.16 reports the functional Fmax and the frequency sweep with the number of rising monitor flags. It is clear that during the ageing operation, the Fmax measured for the first ISM flag occurrence decreases with stress time. Moreover, for all critical and subcritical paths, a clear Fmax reduction with the ageing operation is measured. Therefore, for ageing monitoring, internally placed monitors are a better option than externally situated monitors. Effectiveness of monitors also depends on the insertion flow as it helps decide the selection of critical paths where monitors need to be inserted. The flow needs to be weakly intrusive with respect to the initial performance.

6.5 Methodology to Insert In Situ Monitors in a Design In a complex digital design, the number of monitors to be inserted can become rapidly huge, and the decision to detect global and local variations as well as ageing has to be taken at design time. Complex designs have hundreds of thousands of flipflops, where each endpoint is the destination of a path or multiple paths converging to the same endpoints. Therefore, careful consideration of the overall timing of the critical and subcritical paths in a complex digital design is mandatory and has to include the impact of all mentioned variations.

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Fig. 6.17 Monitor insertion methodology flow in digital design

6.5.1 Conventional Monitor Insertion Methodology The conventional method to insert performance violation monitors is to find a list of timing critical paths from an initial static timing analysis, performed after the synthesis or after physical synthesis steps. The selection of the critical paths and subcritical paths is used to extract the endpoint where monitors will be inserted, especially for the in situ monitors. The generic approach is illustrated in Fig. 6.17. The classical front-end steps are executed with logic synthesis. The gate netlist is feed into the back-end flow starting with the floor plan step. After that, placement of macro blocks and gates, clock tree synthesis (CTS) and clock tree optimization for setup and hold constraints are performed, followed by detailed timing analysis (TA). This step is crucial as it considers not only gate delay, but also it considers delays of the global wires. As a matter of fact, for a given functional corner, a decision is made on a collection of endpoints where to insert monitors. Further to that, detailed routing is performed followed by another TA on a subset of critical paths before physically inserting the monitors. The back-end flow is finalized with a new gate netlist, new timing and power figures are checked again towards the targets, and eventually more optimization is performed. Further to that, the flow is normally executed towards the GDSII with detailed routing and optimization steps including timing, power, IR drop and signal integrity evaluation steps. Note that the insertion of in situ monitors (ISMs) can be done at any level of back-end implementation, for example, during the post-synthesis, post-placement,

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post-clock tree synthesis, post-route, etc. However, designers need to be aware of advantages and drawbacks of each solution. For example: • Post-synthesis and post-placement ISM insertion is easier but in post-synthesis it misses the effect of location of cells and also the interconnects delay consideration. In the post-placement steps, ISM insertion is not accurate as at this point, the effect of interconnect parasitic are not included. • Post-clock tree synthesis ISM insertion includes the effect of clock tree, but the effect on the delay of the interconnects between all the other cells is not taken into account. • Post-route ISM insertion is the most accurate method as it includes the delay effect of all interconnects, but the drawback is in the fact that timing closure usually needs to be done again, potentially several times. In high-frequency designs, this task may lead to serious difficulties to close the design flow. • The best way for the ISM insertion can be hybrid insertion. For example, ISMs are inserted at post-synthesis with static timing analysis and during the postrouting, based on the new timing elements, some of ISMs are discarded and some ISMs are added to the new worst critical paths. This way, the timing closure is fast and leads to better accuracy too.

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Fig. 6.19 Example of percentage of paths to be monitored in nominal corner and in different PVT corners (fast-fast and slow-slow)

As mentioned before, delay of a given path may degrade depending on the environmental conditions (PVT corners), the time and the application running on the circuit: (a) Path delay degradation due to ageing has a logarithmic relationship with time, being more important at the beginning of the utilization time and saturating after that. Paper [32] points out this dependency. (b) The dependence of process and environmental factors on delay is important as it may influence critical path ranking. Paper [33] shows the influence of PVT variations on path ranking. Figure 6.19 left shows that the selected set of critical paths in the nominal corner changes with temperature and the process. In the first figure, we observe a loss of 30% of paths in the nominal corner at 0.6 V and 15% drop when temperature is increased. Obviously the most important degradation is observed in the slow-slow corner for low voltages and temperatures, where up to 70% of the selected paths are not critical anymore. These estimations have been done for a given digital circuit fabricated in 28 nm STMicroelectronics FDSOI technology. Roughly 80% of the initial paths are still meaningful over different corners, but important drops are observed in the worst case. At the same time, some other subcritical paths became important and need to be monitored. So, it is important to consider all these parameters early in the design flow. (c) Another factor has to be estimated as well: the workload influence on timing degradations has also to be evaluated at design time. Papers [33, 34] show for a given circuit, the ranking of critical paths depends on workload execution. Two different workloads (here called pattern A and pattern B) degrade the delay of a set of critical paths in completely different ways, and as a result, the higherranked paths at design time may be different than the critical path after execution of specific workloads. Figure 6.20 shows for a given circuit, how the ranking of critical paths changes due to the workload. Assuming N workloads are available and can be used to extract the activity profiles of gates and paths in the circuit, paths that are more sensitive to ageinginduced degradation delay can be identified. It is essential to estimate if there is one near-critical path that may become critical at a given moment during the execution.

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Fig. 6.20 Pattern dependence of critical path ranking for two different workloads, here called pattern A and pattern B [33]

Figure 6.21 shows different path activations during different workloads that one circuit may experience. Different workloads lead to different activities at endpoint level; thus in function of the coverage of endpoints flip-flops by an ISM, the global failure rate can vary. Figure 6.22 shows different workloads failing rates of one circuit fabricated on different dies. This figure captures the process variation influence and the pattern dependence on the timing failure rate as die #26 has been measured with two different patterns. Paper [34] discusses about the necessity to perform accurate RTL simulation followed by endpoint signal probability extraction that has to be taken into account in the monitor insertion flow. Thus, the ageing-induced delay shifts of the critical paths can be estimated for each workload by using with BTI-aware static timing analysis. Therefore, the global ageing model is built with signal probabilities of the selected endpoints.

6.5.2 Monitor Insertion Based on Ageing-Aware Gate Characterization Methodology To be able to incorporate the corner and workload influence on circuit delay degradation, the following modified hybrid insertion flow is used: • First, an average activity of outputs of all the gates in a design is extracted by using gate-level logic simulation of a specific workload. This is usually performed after the logic synthesis step.

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a

Endpoint 1

StartPoint 1 ARC 2

ARC 1

ARC 3 StartPoint 2 StartPoint 3

b

StartPoint 1 Endpoint 2 Arc 1 Arc 2 StartPoint 2

Arc 3

StartPoint 3 Fig. 6.21 Different path activation scenarios for two different pattern executions

Fig. 6.22 Different profiles of ISM activation on the same circuit implemented with two different patterns and fabricated on different dies [33]

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• A list of all design gates is generated with their average activity. • The delay degradation of all logic gates for the average activity is estimated for each of the standard logic cells of the library. This step is possible if the standard cell library has been characterized with respect to input activities. Paper [34] discusses about this characterization more in details. • The full delay degradation of each gate can be projected at the targeted end-oflife time. Different estimations can be done depending also on the application profile used for the circuit, if this is known. • A second static timing analysis is performed with new delay degradation data, and the first collection of critical and near-critical paths is obtained. • Fan-in cone analysis is performed to identify all the endpoints that cover all paths identified previously. • Back-end steps of the flow can be performed towards the inserted monitors at the endpoints as explained in Sect. 6.5.1, to incorporate precise timing related to the wire and gate fanout contribution. Once the in situ monitors have been inserted in the design, they can be used to trigger adaptive architectures either to reach lower VDD levels (for lowpower applications) or to boost up performance through higher VDD in case high performance is needed or in case the delay degradation is detected.

6.6 Adaptive Architectures Adaptive voltage and frequency scaling (AVFS) and adaptive body biasing (ABB) are two attractive possibilities to overcome the reliability and energy walls of modern CMOS systems. By adapting to the workload and environmental conditions like temperature and variations, total power consumption reduction can be achieved, or performance boosts can be attained. Thus, battery lifetime could be increased in autonomous systems, and hardware ageing process is decelerated and system life is prolonged. In the very basic implementation, an adaptive scheme includes at least two actuators: one to dynamically change circuit supply voltage (VDD ), or the body bias voltage (VBB ), and the second one being used for the frequency (fCLK ) changes, depending on expected performances and power supply modes. To adapt to new requirements, the adaptive scheme uses massively embedded instruments called also in situ local sensors to track process variability or operating conditions (T, VDD droops) as shown in Fig. 6.23. In Fig. 6.23 in situ local sensor pre-error signal collection can be done either by using OR-gates tree when sensor locations are closed one to the other on the circuit floorplan and the OR-tree can be kept to minimum size in terms of area and latency. In case of sparse distribution of sensors over the chip, solutions based on scan design are more adapted for alarm data collection [35].

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Fig. 6.23 Principle of DVFS architecture including a VDD and clock-controlled blocks based on local and global sensors

6.6.1 Adaptive Voltage and Frequency Scaling By implementing a closed-loop control, voltage supply and frequency can be periodically or continuously changed to adapt to system requirements in terms of power and frequency. The general architecture is shown in Fig. 6.23. It shows local sensors monitoring continuously the systems against performance violations induced, for example, either by local variations or by ageing, global sensors such as temperature sensors to account for important power dissipation or VDD drop sensors for other potential reliability or security threats identification. Monitors provide their information to the controller after necessary conditioning, and then the controller checks if the circuit operates at safe and energy-efficient point and takes decisions to change circuit parameters either to avoid timing faults (therefore boosting system performances) or to reduce power consumption. The controller manages the new parameters and the corresponding actuators based also on the information delivered by the upper-layer control (OS, Software task), based on the application requirements. The final objective is to stay as close as possible to the required maximum clock frequency (fCLK). The controller maintains a table with physical configurations that will be indexed according to the upper-layer requirements. For each operating target point, the controller will adapt to the most appropriate combination of system parameters. In AVFS approach, monitoring error-detection signals of sensors can be used for calibrating the operating parameters of the circuit (clock frequency and voltage) to reduce power and optimally comply to the application requirements such as performance. Usually only one actuator is triggered at a given time for the adaptation purpose, and the other one remains constant or is set to satisfy performance constraints. The basic reason is the need to ensure a strong stability of the control

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Fig. 6.24 Typical DC/DC architecture of voltage regulators. PWM is the pulse width modulator controlling transistors by an internal ramp, based on Vref and Vout voltages

loop. It is worth to note that when compensating for P, T and A, there is an inherent impact on the power consumption and on reliability, which usually degrade.

6.6.1.1

Supply Voltage Adaptation

Among some of the first works concerning voltage actuators, it is worth citing contributions going back to 1990 [20, 21, 36–38]. They use dynamic changes of the voltage to the minimum voltage value based on information available from the variability monitoring. In general, they use a DC/DC buck converter as voltage actuator, which converts VDD to a lower-output voltage (see Fig. 6.24). In recent works [39, 40], the VDD hoping technique is used to lower the impact of the LC filter in terms of space. This technique is also called voltage dithering and consists in switching the voltage between several predefined VDD levels to achieve an output voltage that can be applied to the circuit. This technique has a discreet number of voltage levels and is well particularly adapted to lower the power dissipation than to compensate variations. One of the main drawbacks of the supply voltage regulator resides in the design and implementation cost and the difficult reusability over different chips and technologies.

6.6.1.2

Frequency Adaptation

Frequency adaptation is much easier to implement than voltage adaptation, as it does not impact the power distribution. Frequency changes circuitry are much simpler and of a smaller size in area, allowing a faster adaptation to dynamic variations. In this type of adaptation, the clock frequency is set at the maximum value FMAX, by a phase-locked loop circuit (PLL). Digital PLL use a combination of phase detector circuits to compare the output frequency with a reference signal, a normalized voltage-controlled oscillator (VCO) to generate the oscillating signal and a looped filter to ensure signal stability and robustness to variability while providing a low

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jitter clock. Few optimizations have been reported in the literature [41] to get to smaller implementations.

6.6.1.3

Adaptive Voltage Scaling Implementations

By combining pre-error in situ monitor insertion with adaptive scaling architectures, self-calibrating and self-adaptation purposes can be very easily achieved. To evaluate experimentally the proposed monitoring system and supply voltage adaptation, several circuits have been implemented in advanced node 40 nm bulk technology using STMicroelectronics modified insertion flow presented before. The circuits contain a flag, namely, Autotest_OK, which rises when the circuit proceeds without failure. This flag combines the error flags from all monitors [42] (Fig. 6.25). In situ monitors can be used for several applications. One application consists in using ISMs as “speed indicator” monitoring whether the current operation is close to an eventual failure. The principle of the regulation consists in adjusting dynamically the voltage as follows: Starting from a reference voltage (as given by voltage stack), the voltage is dynamically decreased until the first flag alarms rise. Further to that the voltage regulation is performed by increasing the voltage by a step. A control loop does the dynamical regulation at each millisecond. Flags are counted and tracked thanks to an internal flag counter with the possibility to determine which ISM has flagged. The result of the regulation is depicted in Fig. 6.26. Shmoo plot exhibits the flag number when varying operating frequency and voltage. For example, at a given frequency and voltage (e.g. Fmax = 450 MHz, VDD = 1.2 V), the Autotest_OK signal is raised. When the voltage decreases, the first flag appears at a voltage of about ~0.85 V, but at this point the functionality is still correct. If the voltage is decreased even more, many more flag alarms occur until the failure, which in this case is reported at a VDD of about ~0.83 V. Dynamical voltage frequency scaling can also be calibrated by using the voltage regulator loop and monitor alarms. In this case, digital block design has to

Fig. 6.25 In situ monitor implementation and AVS regulation [42]

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Fig. 6.26 Shmoo plot of flag count in function of supply and operating frequency. The gradient is strong at low VDD and frequency [42]

incorporate several operating performance points (OPP) which are represented by voltage-frequency pairs. In case multiple points are implemented, the verification effort is much more important, as the sign-off must be done for a large amount of operating conditions, multi-voltage and frequency modes and multi-PVT, and this is a very tedious validation effort. By using in situ monitors, this effort can be reduced as follows. To mimic different OPP modes, different clock frequencies are applied to the block from 2.3 GHz to 0.27 GHz and for each frequency the supply voltage is decreased until a first flag occurs. The regulation is performed towards the minimal voltage supply without any monitor flags. Then, the mode changes (moving to the next frequency), and the voltage supply is again adjusted to the lower voltage. The waveform of OPP modes is repeated in increasing and decreasing order for several thousands of clock cycles to incorporate also the effect of ageing. The orange line represents the boundary provided by the pre-error flag. The red boundary corresponds to the functional failure. As it is reported in Fig. 6.27. the benefit is lower at lower frequency than at higher frequency. By performing the caracterization of OPP in terms of Vnominal, Vmin and frequency, design margins due to PVTA could be eliminated, resulting in energy and design effort savings.

6.6.2 Adaptive Body Bias The ABB technique is the classic approach used to compensate for process variations by applying different positive or negative bias voltages on the backside

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Fig. 6.27 Support of 8 OPP modes using voltage regulation scheme. Use time of each mode is 75 ms. Each mode is carried out at one condition of frequency, and voltage is automatically adjusted according to flag warning output [42]

Fig. 6.28 Back body bias concept and application

of the transistor substrate, which in turn will shift the threshold transistor voltage (VTH) towards higher or lower values. This feature of the bulk-biased transistors making them operate at a different level of currents can lead to higher performance of the transistor, when applying positive bias, as an example. Indeed, forward body bias (FBB) configuration boosts performances of gates, which in turn lead to an increased leakage current. The reverse is also a possibility, wherein the application of a reverse body bias (RBB) decreases the leakage current at a reduced transistor performance, thus decreasing power dissipation accordingly (see Fig. 6.28). By using this approach statically, product engineers dispose of a new “knob” to modulate the speed for a given power budget or the opposite. In mass production, individual product can be adapted by ABB, to fulfill speed requirement (or power

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Fig. 6.29 Fmax distribution and binning for a typical product

constraint). In that case, it is very important to have accurate speed binning to sustain the highest yield. In addition, in a perspective to increase the yield of a power-speed performance, designing close to nominal sign-off conditions and adapting slower part is an alternative. This approach is used dynamically when the design specifications allow. That is to say, a voltage regulation scheme has to be implemented at design time and operating points are known and validated at design time. Dynamic compensation of performance degradation or the power optimization can be done by using in situ monitors to trigger new circuit operating points. Basic example is given in Fig. 6.29, where the Fmax distribution of a digital block is depicted. Assuming a frequency target at 1 (normalized), all slower parts can be boosted with FBB. This resulting distribution of FBB is given in the inset of Fig. 6.29. The main challenge of ABB in product engineering is the accuracy of speed sensor. Using a classic tunable critical path monitor results in moderate correlation with Fmax capability. In situ monitors can provide here much finer-grained outcome. At electrical wafer sorting phase, path delay ATPG pattern can be used to characterize all in situ monitors, and thus very accurate compensation settings can be given.

6.6.3 ABB vs. AVFS Adaptive body bias (ABB) technique has been widely used for variation compensation and performance regulation of a circuit after the fabrication steps. The dynamic of the body biasing technique for circuits based on classic bulk silicon technology is lower as compared to that of circuits fabricated using the FDSOI

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process. Dynamic (or adaptive) voltage and frequency scaling (A-DVFS) scheme provides a similar result with ABB strategy, that is, an increase of performance or control of leakage current, but it plays with VDD or clock frequency, allowing thus to move between several modes of much high performance and lower power. For circuits based on transistors with higher threshold voltages (VTH) that operate at higher supply voltages (VDD), supply voltage adaptation scheme could be a much better option to reduce the overall power consumption as compared to body biasing, as the power consumption has a quadratic dependence on the VDD. And this has been the case with circuits of the older technological nodes with most of them implementing DVFS strategies to account for the various variations or achieve an optimal operational frequency for a reasonable power consumption envelope. The scaling down of transistor dimensions can be considered to be one of the most highly motivating factors to move towards the adoption of adaptive body biasing methodology for compensation. As a matter of fact, in more advanced technologies, VDD is decreasing since the transistors of the newer technological nodes function at lower voltage values. This means that the DVFS strategy would be less efficient as compared to a body biasing-based compensation scheme. The impact of variations resulting from the silicon manufacturing process on circuits is also on the rise with scaling down in transistor dimensions and adaptive body biasing scheme will be a preferred method to nullify these effects. In addition, the circuitry required for adaptive body biasing is far less complex in implementation as compared to regulation of supply voltages by DVFS that requires expensive and high-quality isolation cells, also level shifters for multiple VDD domains integration, in addition to high complexity voltage regulators. The current consumption of body biasing regulation circuits is far less than supply voltage variation-based compensation circuits. ABB technique can also be implemented differently on different sections of the circuit using multiple bias voltage generators with each one being allocated to a section.

6.7 Conclusion This chapter discusses the context and the motivation of using performance and reliability monitors within the most up-to-date digital designs fabricated in nanometric technologies. After presenting up-to-date monitor architectures, the chapter addresses the impact on their insertion on the classic front-end/back-end design flow. Further to that, the following section deals with monitor signal utilization to drive supply voltage and frequency adaptation or body bias adaptations.

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Chapter 7

Aging Monitors for SRAM Memory Cells and Sense Amplifiers Helen-Maria Dounavi, Yiorgos Sfikas, and Yiorgos Tsiatouhas

7.1 Introduction SRAM occupies a large portion of silicon area in today’s integrated circuits and plays a major role in their performance characteristics [1]. Thus, SRAM’s reliability is a key issue for the reliable operation of modern systems. In nanometre technologies the SRAM’s reliability is seriously threatened by the increased process variations as well as bias temperature instability (BTI) [2] and hot carrier injection (HCI) [3] phenomena. More specifically, process variations may set transistors’ performance away from the expected level (this effect can be seen as a premature aging), while BTI or HCI may lead to a significant increase of the absolute value of transistors’ threshold voltage (Vt ) decreasing this way their performance over time (these effects can be seen as gradual aging). Aging due to BTI or HCI is accelerated when the transistors are under excessive stress conditions (high gateto-source voltage levels and high temperatures of operation). However, it should be noted that when a transistor faces DC (permanent) BTI stress, its Vt degradation tends to become much higher with respect to AC BTI stress, since the latter involves recovery cycles that alleviate the influence on Vt . Thus, in BTI the switching activity determines the transistors’ aging rate. The performance of an SRAM memory cell is affected by BTI and HCI since these phenomena influence both the memory speed and the noise margins [1]–[4]. Moreover, recent research indicates that transistor aging in SRAM sense amplifiers also results in gradual speed performance degradation [1] and input offset voltage development [5, 6]. Thus, as the performance of SRAM memory cells and sense amplifiers is continuously degraded, failures are expected to occur during the SRAM

H.-M. Dounavi · Y. Sfikas · Y. Tsiatouhas () Department of Computer Science and Engineering, University of Ioannina, Ioannina, Greece e-mail: [email protected] © Springer Nature Switzerland AG 2020 B. Halak, Ageing of Integrated Circuits, https://doi.org/10.1007/978-3-030-23781-3_7

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operation. According to the above, it is mandatory to develop aging monitoring techniques for these blocks in order to obtain the ability to predict failures that may occur during memory lifetime and repair the circuit accordingly to ensure aging tolerance and consequently its reliable operation. Various techniques have been presented in the open literature for the monitoring of aging-related performance degradation in SRAMs. However, some of the cons related to these techniques stem from the fact that they cannot locate the defective parts; thus, repairing operations are not feasible, or they require a lot of additional circuitry leading to an excessive cost in the silicon area and design complexity. The IDDQ current has been used in [7] for the characterization of NBTI-induced SRAM performance degradation. Under NBTI influence, the leakage current of the memory cells is reduced exponentially due to the Vt degradation. The presence of a power-gating scheme is assumed, and a current mirror-based IDDQ monitor is exploited. This approach measures the accumulative leakage current of the whole memory array and thus the location of aged cells is not feasible. Special structures that are based on analog blocks (voltage comparators, phase comparators, etc.) are exploited in [8] for the stability characterization of an SRAM under the influence of NBTI (among other sources of vulnerability). However, the design complexity is too high. In [9] an on-chip NBTI aging sensor is proposed for the off-line monitoring of the writing operations into the SRAM memory cells in order to detect degradation. A dedicated sensor (which is based on a sense amplifier topology) exists for every column in the SRAM array. The technique assumes the use of power gating schemes and the existence of a non-aged reference column of memory cells. Off-line write operations are performed to the memory cells and the corresponding reference cells. After each write operation, the virtual VDD voltage levels of the memory cell under monitoring as well as the reference cell are compared in order to detect aged memory cells. A main drawback of this approach is the requirement of non-aged reference cells. Aging monitoring solutions based on embedded ring oscillators [10, 11] and voltage-controlled oscillators [10] have been proposed. In addition, in that case, the degradation of the whole SRAM is inspected and repair operations are not feasible. A write margin degradation monitoring technique for SRAMs is presented in [12]. According to this technique, a sequence of read/write operations is performed on a cell while the word-line voltage is successively lowered. The maximum tolerated word-line voltage drop by the memory cell is related to the transistors’ threshold voltage and it is exploited for degradation detection. This solution requires the generation of multiple voltage levels for the application of the aging monitoring procedure. Error-correcting codes (ECCs) can be used to avoid aging-related failures during the SRAM operation [13, 14]. However, in large memories and as the number of aged cells increases in time, it is necessary to exploit redundancy in order to maintain reliability. Thus, ECC alone is not always a sufficient solution and monitoring schemes for the location of aged cells near failure are necessary.

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In [15], the frequency of a local ring oscillator is exploited for BTI-induced aging monitoring in SRAM memory cells. However, this frequency is also prone to process and temperature variations. An interesting memory cell BTI degradation estimation method is presented in [16]. Each bit-line slice in the memory array is modified as it is shown in Fig. 7.1. According to this method, in NBTI testing the current strength of the pMOS transistors in the cell is used for the detection of aged devices. Sequences of successive pseudo write operations are applied on a selected memory cell, where unlike the normal situation both bit lines are forced to the ground through the modified write circuitry. Once the bit lines are pulled down, the voltage sensing circuit deactivates the write circuitry, and the pMOS transistors start to charge the bit lines. Obviously, the charging current is a function of the threshold voltage and it is influenced by NBTI so that NBTI aging affects the charging time. When the bit-line voltage exceeds a certain level, the write circuit is reactivated forcing again the bit lines to the ground. Consequently, an oscillation is generated which is related to the cell pMOS transistor strength. Transistor degradation results in oscillation frequency degradation. The generated oscillation frequency is digitized for evaluation.

TEi Pre

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Data In

Frequency divider

Tei_fd

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TEi

Fig. 7.1 Bit-line slice modifications for the support of the BTI monitoring technique in [16]

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Similarly, in PBTI testing the current strength of the nMOS transistors in the cell is used for the detection of aged devices. This time sequences of pseudo read operations are performed on a selected memory cell, where unlike the normal mode both bit lines are forced to VDD through the modified pre-charge circuitry. After the charging of the bit lines, the pre-charge circuitry is deactivated. Thus, the cell’s nMOS transistors start to discharge the bit lines. When the bit-line voltage turns lower than a certain level, the pre-charge circuit is reactivated forcing again the bit lines to VDD . As earlier, an oscillation is generated, where the frequency depends on the strength of the discharging nMOS transistors. Once again, transistor degradation results to oscillation frequency degradation. The above BTI monitoring method is periodically applied in the field of operation, and detected overaged memory cells (near failure) are replaced by spare cells using the embedded repair mechanisms in the memory. However, this approach is seriously affected by process and temperature variations. Moreover, note that the memory control logic must be redesigned in order to be able to support the measurement process. From the above analysis, it is obvious that many researchers have focused their work on the aging monitoring of SRAM memory cells but the aging monitoring of SRAM sense amplifiers has not been extensively investigated. A technique for the characterization of SRAM sense amplifier input offset voltage, for yield prediction, is presented in [17]. In this work, two resistor string 6-bit digital-toanalog converters (R-DACs) are used to drive the inputs of the sense amplifiers in a memory array. These R-DACs generate various bit-line voltage differences that are necessary for the sense amplifier input offset voltage estimation. Each sense amplifier is selected for test after the other with the help of a counter, while a second counter is exploited for the final yield evaluation. The silicon area cost and the design effort related to this characterization technique are quite high. Finally, an approach for possible mitigation of BTI aging relies on the recovery property of this mechanism. In the case of the memory cell, proper circuitry is included in the memory to flip periodically the stored data in it in order to reduce transistor degradation [18]. In the case of the sense amplifier, the input switching sense amplifier is proposed [5] in order to attain a balanced workload and consequently reduced transistor degradation. Due to the statistical nature of these solutions, BTI aging effects are alleviated but not eliminated. Consequently, aging prediction and repair schemes are mandatory for the long-term and reliable memory operation.

7.2 Chapter Overview This chapter deals with aging mechanisms in SRAMs and their influence on the memory’s reliable operation. The effect of transistor aging on the performance characteristics of the SRAM memory cells and sense amplifiers performance degradation is discussed. A generic technique is presented that focuses on SRAM

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aging prediction for the early diagnosis of the memory status in order to react and maintain its reliable operation. A periodic aging monitoring scheme is illustrated along with a repair methodology for the case where excess performance degradation is detected. This scheme provides the ability to locate overaged – near failure – modules (memory cells or sense amplifiers) and properly react in order to tolerate aging-induced errors during the memory lifetime.

7.3 Aging Effects on the SRAM Operation The influence of transistor aging on the SRAM memory cells’ and sense amplifiers’ operation is a serious concern in nanometre technologies. The HCI and BTI transistor aging mechanisms are of major importance in nanometre SRAMs. The HCI mechanism is characterized by its permanent impact on the affected transistors. On the other hand, the effects of BTI phenomena depend on the frequency of the stress and recovery time intervals. The DC (continuous) BTI stress on a transistor will result to a much higher Vt degradation due to the absence of recovery cycles that are observed in AC stress. Thus, the BTI influence on SRAM memory cells and sense amplifiers is related to their switching activity, and in case of reduced switching activity (higher DC stress), increased performance degradation is expected.

7.3.1 Aging Influence on the SRAM Memory Cell Operation The vulnerability of a memory cell to transistor aging has been extensively studied in literature [7, 8, 16, 19–23]. According to these studies, aging substantially affects the operation of a memory cell and consequently influences the SRAM performance characteristics, like the read and hold (retention) static noise margins (SNMs), the write margin, the access time and the minimum operating voltage. The SNMs are defined as the minimum noise voltage level that is capable to flip a memory cell. The write margin is the minimum voltage on the bit lines in order to perform a transition write operation on a cell. Finally, the access time is the maximum time duration for a read operation. The typical topology of the 6T SRAM memory cell is presented in Fig. 7.2. It consists of a pair of inverters (MCP1, MCN1 and MCP2, MCN2) in a cross-coupled topology and two access transistors (MCN3 and MCN4) driven by the word line (WL) and connects the cell to the bit lines (BL and BLB, respectively). Initially, we should mention that since most of the time during the SRAM operation the access transistors (transistors MCN3 and MCN4 in Fig. 7.2) are off, almost no degradation is expected on these devices [16]. In addition, when a pMOS transistor in the cross-coupled pair (e.g. transistor MCP1) is under stress (Qb = low), then the nMOS transistor of the other inverter (MCN2) will be also

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WL VDD MCP1

MCN3

MCP2

Q

Qb MCN4

MCN1 BL

MCN2 Gnd

BLB

Fig. 7.2 Typical topology of a 6T SRAM memory cell

under stress (Q = high). Obviously, in that case transistors MCP2 and MCN1 are not stressed (they are in a recovery state). Consequently, a memory cell that does not alter its memory state is expected to become increasingly skewed due to an asymmetric transistor aging. However, more or less skew problems are also reported even if a memory cell has a more frequent switching activity. Thus, the performance characteristics of a memory cell will be degraded over time.

7.3.2 Aging Influence on the SRAM Sense Amplifier Operation Recently, the impact of transistor aging on the sense amplifier (SA) operation has been also studied [1, 5]. According to these studies, under aging conditions both the sensing delay and the input offset voltage of the sense amplifier are negatively affected (increased). The sensing delay is related to the speed performance of the sense amplifier (read response time), which is degraded. The input offset voltage is also an important performance characteristic of the sense amplifier, and it is defined as the differential input voltage that results in a differential output voltage equal to zero. A non-zero input offset voltage has a negative impact since it alters the minimum bit-line voltage difference that is necessary for a successful read operation. For an ideal sense amplifier, the input offset voltage is zero since the corresponding transistors are perfectly matched. However, in practice, due to local process variations, transistor mismatches are always present and various input offset voltage levels are observed even in “fresh” sense amplifiers (time-zero variability just after fabrication), which may change over time due to aging (time-dependent variability) [5, 24, 25]. A well-known and widely used sense amplifier is the latch-type sense amplifier that is shown in Fig. 7.3. It consists of a cross-coupled pair of transistors (MSP1, MSP2, MSN1 and MSN2), two activation transistors (MSP3 and MSN3) and two access transistors (MSPL and MSPR). The sense amplifier senses the voltage

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VDD SA_EN MSP3 SA_EN

IN_L

MSP1

SA Core (SAC) MSP2

NL

SA_EN

NR

MSPL

MSPR MSN1

IN_R

MSN2

OUT_L

MSN3

OUT_R

SA_EN Gnd Fig. 7.3 The latch-type sense amplifier (SA)

difference that is developed between the bit lines (which are attached to its inputs IN_L and IN_R) during the read operations. The SA_EN signal is exploited for the activation of the sense amplifier. The operation of this sense amplifier is divided into two phases. In the first phase, the SA_EN signal is low and the sense amplifier is inactive; the access transistors MSPL and MSPR are on so that the initial voltage difference on the bit lines (which is generated by the activated memory cell) is passed to the internal nodes NL and NR of the sense amplifier core (SAC). Next, in the second phase, the SA_EN signal turns to high, and the sense amplifier core is isolated from the bit lines and connected to the power supplies through the MSP3 and MSN3 transistors. The cross-coupled pair amplifies the initial voltage difference and the read value appears at the outputs OUT_L and OUT_R of the sense amplifier. According to the experimental results in [5], it is reported that under common and typical memory workloads, aging will induce transistor degradation in such a way that the sense amplifier will become increasingly skewed, as in the case of the memory cell. This stems from the fact that under these workloads a pair of transistors (e.g. MSP1 and MSN2) is under successive stress while the complementary pair of transistors (MSP2 and MSN1) is always relaxed (in a recovery state), causing an asymmetric aging. Thus, the Vt degradation of the first pair of transistors increases over time so that the mismatches between transistors MSP1 and MSP2 as well as between MSN1 and MSN2 will continuously increase and the same stands for the sense amplifier input offset voltage. As a result, over time, failures are expected to appear during the read operations. Note that in both cross-coupled pairs either of the SRAM memory cell or the sense amplifier, the nMOS Vt degradation does not cancel the effects of pMOS Vt degradation and vice versa [7, 16].

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7.4 Aging Monitoring Topology The aging monitoring architecture for SRAM memory cells and sense amplifiers is presented in Fig. 7.4. The idea is based on a small differential ring oscillator (DRO) which is embedded in the memory array so that during the monitoring (testing) phase, an SRAM memory cell or a sense amplifier plays the role of “active” load at its output. A dedicated DRO is placed at every bit line in the memory array; it drives either the corresponding sense amplifier or an activated memory cell of this bit line during the test mode of operation. According to experimental observations, a skewed (due to aging) memory cell or sense amplifier alters the duty cycle of the oscillation signal that is generated by the DRO. Consequently, the duty cycle of this signal can be exploited in order to identify overaged modules.

7.4.1 The Monitoring Circuitry In Fig. 7.4, the bit-line slice of an SRAM memory array is presented. Bit-line access transistor pair M1-M2 (one per bit line BL and bit-line bar BLB, respectively) permits the sense amplifier to access the cells of the memory array, in the normal mode of operation, by exploiting the column decoder signal CSEL (active at logic low). In the test mode of operation, the CSEL signal is never activated. Note that for simplicity the write circuitry is not shown in this figure. The DRO is placed next to the sense amplifier. It consists of three tri-stated differential delay elements (Dff-D cells). The Tst_EN (test enable) signal is used to activate (at logic high) the Dff-D cells in the test mode of operation or deactivate them (at logic low) in the normal mode of operation. The DRO drives either the internal nodes NL and NR of the sense amplifier core (SAC) block through a pair of switches (full pass gates) SSL and SSR or the bit lines BL and BLB of the corresponding bit-line slice through a second pair of switches SCL and SCR (see Fig. 7.4). The first pair of switches (SSL and SSR) is activated by the signal Tst_EN, while the second pair (SCL and SCR) is activated by the memory array access (Arr_AC) signal (both signals active at logic high). Two test modes of operation exist, one for the monitoring of the memory cells and one for the sense amplifiers. Initially, the mode for testing a memory cell is discussed. The sense amplifier remains inactive in this mode (SA_EN is low). The word line (WL) of the cell under monitoring is activated (at logic high), while the bit-line pre-charge circuitry (not shown in Fig. 7.4 also for simplicity) remains inactive too. In addition, the bitline pair BL and BLB is accessed by setting the Arr_AC signal to high. The DRO is activated (Tst_EN is set to high) and the generated oscillation signal drives the selected memory cell in the array, which plays the role of an active load. Each time the differential signal of the DRO changes state, the corresponding memory cell is written to the complementary state with respect to its present state. Given that the

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SA OUT_L Fig. 7.4 The monitoring circuitry

OUT_R

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Tst_EN signal is active, the switches SSL and SSR are on so that the oscillation signal is further propagated to the outputs OUT_L and OUT_R of the sense amplifier. In the test mode of operation for the sense amplifier monitoring, the SA_EN signal is activated. In addition, the Tst_EN signal is also activated while the Arr_AC signal remains inactive. This time, the oscillation signal generated by the DRO feeds only the sense amplifier, which now plays the role of the active load. Once again, this signal appears at the outputs OUT_L and OUT_R of the sense amplifier. In both cases, the duty cycle of the oscillation signal is used for the discrimination of aged modules (memory cells or sense amplifiers). The oscillation signal is propagated outside the memory array in order to perform measurements of its duty cycle for the aging evaluation. Then, the duty cycle is compared with an embedded reference value aiming to detect the overaged modules. Note that two reference values are stored upon exercising the testing procedure, one for the memory cells and one for the sense amplifiers. For the support of the test operation two extra signals are introduced, the Tst_EN and the Arr_AC signals, with respect to a typical SRAM, which are common for all bit-line slices.

7.4.2 The Differential Ring Oscillator (DRO) The differential ring oscillator consists of three differential delay elements (Dff-D cells). A Dff-D cell is a tri-stated cross-coupled dual rail structure, as it is illustrated in Fig. 7.5, with the addition of two activation transistors, one nMOS MDN3 and one pMOS MDP3. The activation transistors are controlled by the Tst_EN signal and its complementary signal, respectively. When the Tst_EN signal is low, the Dff-D cells are inactive, disconnected from the power supplies, so that their nodes are floating. This is the normal mode of operation, where the SRAM operates most of the time since aging monitoring is a small-duration periodic activity. In addition, in this mode, all four switches (SCL, SCR, SSL and SSR – see Fig. 7.4) are also inactive and the DRO is isolated from the rest circuitry. Thus, due to the presence of leakage currents the internal nodes of the DRO are stabilized at intermediate voltage levels between the two power supplies (VDD and ground). Consequently, a low, homogenous, voltage stress influences the transistors of the DRO (MDP1-2 and MDN1-2 in Fig. 7.5) so that their aging is slow. Note also that transistors MDP3 and MDN3 are not under stress in the normal mode. Although this may slightly affect the signal frequency of the DRO, the duty cycle of this signal is not altered due to the homogenous voltage stress. Consequently, the DRO is capable of effectively supporting the aging monitoring task throughout the SRAM lifetime.

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VDD MDP3 Tst_EN

MDP1

MDP2

OUT_L

OUT_R

IN_L

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MDN1

MDN2 MDN3 Tst_EN

Gnd Fig. 7.5 The differential delay element (Dff-D cell)

7.4.3 The Monitoring Methodology: Failure Prediction The methodology that is analysed next is used for periodic monitoring, in the field of operation, of the memory cells and sense amplifiers aging in SRAMs. In the test mode, either for a memory cell or a sense amplifier in a bit-line slice, the generated oscillation signal of the DRO reaches the outputs of the corresponding sense amplifier and is transferred to a digitizer block for evaluation (the general architecture is illustrated in Fig. 7.6). The BLOi signal is either the OUT_L or OUT_R signal of the i-th sense amplifier (see Fig. 7.4). In the digitizer block, the duty cycle of the signal is measured and digitized in a serial manner (each time a single cell or sense amplifier is evaluated). The result is compared with a reference duty cycle value in order to detect possible excess aging degradation. The reference duty cycle is stored in a ROM like these typically used for memory repair operations. A dedicated ROM for the reference duty cycle value of the cells and the sense amplifiers is used, since in general these are expected to be different. After the evaluation of a memory, cell or sense amplifier, the next cell or sense amplifier is evaluated and so on until the evaluation of all cells or sense amplifiers in the memory array. The reference duty cycle value corresponds to a memory cell or a sense amplifier accordingly that although it is aged enough, it does not generate failures during the SRAM operation. Furthermore, a memory cell or a sense amplifier with a duty cycle just outside this reference limit also does not generate failures. However,

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Row Decoder

. . .

SRAM Memory Array . . .

. . .

Bit-lines Pair

Word-Line

Fig. 7.6 The general SRAM architecture

Column Decoder . . .

CSEL

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Tst_EN

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Digizer

Data Bus

BLOn

I/O Circuitry

further aging will soon result in the generation of failures and the degradation of the reliability levels. Thus, failure prediction can be achieved, through the application of the proposed method, in order to early react for the memory repair. Periodic aging monitoring is a quite effective solution since aging degradation is a gradual phenomenon. Given that a memory cell or sense amplifier has been seriously affected by aging, so that its operation is near failures generation, then after the detection of this status the SRAM can be properly repaired in order to ensure aging tolerance and retain the memory reliable operation (as we will discuss in Sect. 7.6). The monitoring procedure can be periodically applied, in the field of operation, at the system start-up or during idle times, aiming to increase the effective lifetime of the SRAM. However, in case that the reliability standards are too high, aging monitoring can be applied at the end of predetermined time intervals, like the refresh operations in DRAMs but at definitely much greater time periods. This kind of periodic activity will not in practice affect the performance of the system where the SRAM is embedded.

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7.4.4 The Digitizer

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The digitizer block is presented in Fig. 7.7. It consists of an n-bit shift register (SR) and n switches (these are n full pass gates – SWi, where n is the number of columns in the memory array under monitoring), an m-bit counter (where 2m = w + 1 and w is the number of the word lines in the memory array), two identical counters (the high counter HC and the low counter LC) and optionally a divider-comparator block. The m-bit counter counts for the w word lines (rows) of the memory array plus one that is the row of the sense amplifiers. The data register in Fig. 7.7 is not part of the digitizer; it is the standard I/O data register of the SRAM. A very simple state machine is utilized for the operation of the digitizer, and the corresponding operational diagram is shown in Fig. 7.8. In the normal mode of operation, the Tst_EN signal and the Clear signal are low so that the m-bit counter is initialized to the zero state and the SR is initialized to the all-zero state except the leftmost bit (which drives the first switch SW1) that is set to high, while the two counters HC and LC are reset to the zero state. The digitizer is in the idle state. In the test mode of operation, the Clear signal is set to high. Next, the Tst_EN signal is also activated to high. The oscillation signal that is generated by the DRO of the first column is propagated through the corresponding output of the first sense amplifier (BLO1) and through the SW1 switch to the enable input (En) of the HC and LC counters. Depending on the test mode, a memory cell or the sense amplifier of the column is tested. When the BLO1 signal is high, the HC counts up, while when the BLO1 signal is low, the LC counts up, under the supervision of the CLK

Pass/Fail (Test result)

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Idle

Start Measurement (TST_EN = high)

Iniaon (Clear = high)

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NO FAIL YES

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Stop= high?

Next Row – Count Up (Next=pulse) (Restart, TST_EN = low)

YES

Finish = high? NO Shi SR (Shi = pulse, TST_EN=low)

Fig. 7.8 The operational diagram of the digitizer

signal. The CLK signal is the system clock and its frequency is higher, at least twice, with respect to the frequency of the oscillation signal. Obviously, at any time instance, the value of each counter (high signature and low signature, respectively) depends on the duty cycle of the BLO1 signal. Whenever one of the counters reaches its maximum value, the pertinent overflow signal is generated (H-Overflow or LOverflow). Thus, the End signal is activated and both counters are frozen. The ratio of the high and low signatures corresponds to the duty cycle ratio of the oscillation signal BLO1 and is used for decision-making on the aging of the pertinent module (memory cell or sense amplifier) under monitoring. A local divider can be exploited for the generation of the ratio, which is compared with the corresponding reference value. Alternatively, since in general an SRAM is embedded in a microprocessor system, the existing ALU can be used for the ratio generation and comparison. In case that the test result is “Fail” a repair operation follows, as we will discuss in Sect. 7.6. Next, the Tst_EN signal is deactivated to low and the two counters HC and LC are reset. In addition, a pulse is generated on the Shift signal for a single shift operation in the SR. Consequently, only the second switch SW2 is now on. Then, the Tst_EN signal is activated and the oscillation signal through the BLO2 output of the second column feeds the enable input (En) of the HC and LC counters. A second round of measurements follows for the evaluation of the second module according to the above discussion, and so on. After the evaluation of all modules in a row (e.g. after

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n shift operations in the SR), the Finish signal is generated by the SR. Then, a pulse is applied on the Next signal for a single count-up operation by the m-bit counter in order to select and test the next row in the memory array. Thus, the SR is re-initialized by the Restart signal that is generated by the m-bit counter, and the above measurement-evaluation-repair procedure is repeated for this row. When the modules of all rows in the memory array (w in number) plus the row of the sense amplifiers have been measured and evaluated (e.g. the m-bit counter overflows), then the Stop signal is activated to high, and the digitizer block returns to the idle state.

7.5 Manufacturing Testing Operations The above aging monitoring scheme can be used for the testing of the DRO, the memory cells and the sense amplifier modules during the manufacturing testing operations. The DRO can be exercised by exploiting a variation of the methodology presented in Sect. 7.4, among other testing procedures that can be also exploited in the fab. In that case, the SA_EN and Arr_AC signals remain inactive and only the Tst_EN signal is activated. Thus, the memory cells or the sense amplifier do not influence the generated oscillation signal by the DRO. This way, defective or overskewed DROs, due to transistor mismatches, are identified and the pertinent column is replaced by a spare one in order to maintain the aging monitoring capability and consequently the SRAM reliable operation in the field of operation. Next, after DROs testing, the memory cells and the sense amplifiers are tested. The proposed aging monitoring scheme is exploited as presented in Sect. 7.4 for the detection of over-skewed memory cells or sense amplifiers with unacceptable offset voltage levels, which are related to local process variation-induced transistor mismatches. Over-skewed memory cells or sense amplifiers are identified and the memory can be repaired according to the discussion in the next section. Consequently, after the completion of the two test procedures, possible cases of malfunction that are related to local process variations either in the DROs, the memory cells or the sense amplifiers are alleviated.

7.6 Experimental Results The above aging monitoring scheme has been validated by simulations on the memory bit-line slice topology in Fig. 7.4 that has been designed in the 90 nm CMOS technology of UMC (VDD = 1 V), using the CADENCE Virtuoso platform and the SPECTRE simulator, respectively. It consists of 256 memory cells. The transistors’ widths for the Dff-D cell, the switches (SCL, SCR, SSL, SSR) and the sense amplifier are presented in Table 7.1. The read response delay time of the “fresh” memory, without the monitoring circuitry and in the typical conditions, with respect to the word-line (WL) activation is 92.80 ps.

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Table 7.1 Transistor widths in the bit-line slice design Cell Dff-D (Fig. 7.5) SA (Fig. 7.3)

Switch (SCL, SCR, SSL, SSR)

Transistor MP1, MP2, MP3 MN1, MN2, MN3 MP1, MP2 MP3 MN1, MN2 MN3 pMOS nMOS

Width 300 nm 200 nm 400 nm 800 nm 1425 nm 960 nm 800 nm 800 nm

According to [5], under common memory workloads, a pair of diagonal transistors in the cross-coupled topology of the memory cell or the sense amplifier core, in Figs. 7.2 and 7.3, respectively, remains in a relaxed state, while all the rest of the transistors are under stress (this is the case of asymmetric aging). Without loss of generality, in the presented simulations, transistor aging (e.g. threshold voltage shift |Vt |) is considered for the transistors MCP1 and MCN2 of the memory cell, while MCN1 and MCP2 are in a relaxed state. Accordingly, transistor aging is considered for MSP1, MSN2, MSP3 and MSN3 of the sense amplifier core (SAC) in Fig. 7.3, while transistors MSP2 and MSN1 remain in a relaxed state so that they are not affected by Vt degradation. Obviously, the opposite situation is equivalent.

7.6.1 Experiments on the SRAM Memory Cells 7.6.1.1

Aging Influence on SRAM Memory Cells and Repair Options

As we mentioned in Sect. 7.3, the transistor aging affects the memory noise margins. The Static Noise Margin (SNM) is the maximum amount of noise that the cell can tolerate before its data is corrupted and its state is changed. Schematically, SNM can be obtained by drawing the static characteristic curves of the inverters of the cell to obtain a butterfly curve. The SNM is the size (side) of the largest square that can be fit in the eyes of the curves. If the sizes of the two largest squares (one square per eye) are different, then the smallest of them is chosen. With the use of the butterfly curve, the cell stability is explored [26]. Below, the SNM for both the hold and the read operation is calculated. A controlled voltage source Vn is used as a noise source at one of the cell’s inputs which is swept from 0 V (gnd) to 1 V (VDD ). The read and hold SNMs are determined as follows: • Read SNM: is determined by enabling the word line to connect the memory cell internal nodes to the pre-charged bit lines, and the Vn is swept from the ground to VDD . The Vn that flips the cell gives the Read SNM (RSNM).

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• Hold SNM: is determined by disabling the word line to isolate the memory cell internal nodes from the bit lines, and the Vn is swept from the ground to VDD . The Vn that flips the cell gives the Hold SNM (HSNM). Aging-induced Vt degradation disturbs the inverters’ characteristic curves and reduces the RSNM and HSNM. In Fig. 7.9 the RSNM for a “fresh” and an aged cell with |Vt | equal to 60 mV and in Fig. 7.10 the HSNM for a “fresh” and an aged cell with |Vt | equal to 60 mV are presented. For the case of a memory cell, the ratio of the DRO oscillation signal (high to low ratio of this signal during the test mode) with respect to the transistor threshold voltage shift (|Vt |) for the transistors MCP1 and MCN2 in Fig. 7.2, at the typical process conditions, is presented in Fig. 7.11. We can easily observe that the ratio of a skewed cell (|Vt | > 0) has a clear deviation with respect to a “fresh” cell (Vt = 0), which permits the detection of aged memory cells. After the detection and location of an overaged memory cell near failure, proper actions must be considered for the future reliable operation of the memory. Towards this direction, the repair method proposed in [16] can be adopted. According to this, in case of a single overaged cell in a memory array row, existing error-correcting

Fig. 7.9 HSNM measurement for (a) a fresh cell and (b) an aged cell (|Vt | = 60 mV)

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Fig. 7.10 RSNM measurement for (a) a fresh cell and (b) an aged cell (|Vt | = 60 mV)

Fig. 7.11 Duty cycle ratio vs Vt degradation (Vt shift) of the memory cell

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Fig. 7.12 Waveforms of the oscillation signal of (a) a “fresh” cell and (b) an aged cell (|Vt | = 60 mV)

codes (ECCs), commonly used in SRAMs, are exploited to correct possible errors. Thus, single bit errors are tolerated. If a second cell in a row is also detected as overaged, this can be replaced by a spare (redundant) one exploiting existing repair mechanisms that are embedded in the memory. The waveform of the oscillation signal that is generated by the monitoring circuit for a “fresh” memory cell (without any transistor degradation – no transistor threshold voltage shift exists – Vt = 0) is presented in Fig. 7.12(a). Next, in Fig. 7.12(b) the signal waveform is shown for the case of an aged memory cell (transistor degradation exists due to an absolute threshold voltage shift equal to |Vt | = 60 mV for the two indicated transistors). It is obvious from these figures that the duty cycle of the generated signal is decreased in the presence of a Vt shift.

7.6.1.2

Process, Voltage and Temperature Dependencies

The aging of the memory cells should be also examined under the presence of process, temperature and supply voltage variations. Initially, the statistical models of the used technology are exploited in order to conduct statistical (Monte Carlo) analysis aiming to explore the influence of process variations. 1000 Monte Carlo

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Fig. 7.13 Process variation related circuits’ distribution

runs are applied for the testing procedure of a memory cell, for the case of “fresh” cells and the case of aged cells with |Vt | = 150 mV. The oscillation signal duty cycle ratio distribution appears in Fig. 7.13. As it is expected, the distribution shifts towards lower duty cycle ratios with the transistor aging. Furthermore, we observe that due to transistor mismatches (time-zero variability), a portion of the “fresh” cells will be seriously skewed (“premature aging”). Depending on the memory specifications, the statistical analysis of measurements on fabricated circuits and possibly simulation data as well as the acceptable skew tolerance, a duty cycle ratio limit (reference duty cycle value) is specified. This reference value, after digitization, is stored in a small ROM in the memory. In case that during a test session the duty cycle ratio from a memory cell is below this reference value, the cell is characterized as over-skewed (either if the cell is “fresh” or aged) and a repair procedure must be applied to ensure the memory reliable operation. Note that just below this reference value, the memory is still functional but further cell aging will soon result to failures generation. The influence of supply voltage variations (a ± 10% of the nominal value is considered) and temperature variations are presented in Figs. 7.14 and 7.15 respectively, for a “fresh” and an aged memory cell with a threshold voltage shift equal to 60 mV and 150 mV. In both cases, there is enough headroom for aging detection under variations. We should mention here that since a testing procedure is applied at time intervals where the system is inactive, we do not expect a high voltage variability during the monitoring phase.

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Fig. 7.14 Voltage variation effects on the duty cycle ratio

Fig. 7.15 Temperature variation effects on the duty cycle ratio

7.6.2 Experiments on the SRAM Sense Amplifiers 7.6.2.1

Aging Influence on SRAM Sense Amplifiers and Repair Options

Aiming to explore the influence of aging on the sense amplifier operation, its input offset voltage was measured under various threshold voltage shift conditions for the MSP1, MSN2, MSP3 and MSN3 transistors of the sense amplifier core. The experiment was as follows. For every threshold voltage degradation level, the minimum voltage difference on the bit lines was measured in order for the sense amplifier to provide the correct response (independently of the required time). This voltage difference corresponds to the input offset voltage. In Fig. 7.16, the increment of the input offset voltage with respect to the transistors’ threshold voltage shift |Vt | is shown.

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Fig. 7.16 Sense amplifier input offset voltage vs transistors’ Vt degradation (Vt )

Fig. 7.17 Minimum bit-line voltage difference vs transistors’ Vt degradation

Furthermore, in a second experiment, the minimum bit-line voltage difference that is required on the bit lines in order for the sense amplifier to provide its response within the same time duration, after the activation of the SA_EN signal, as a “fresh” sense amplifier was measured. The graph of this experiment is presented in Fig. 7.17. As the threshold voltage shift |Vt | increases, the bit-line voltage difference should also increase in order for the sense amplifier to respond within the same time duration. Consequently, by increasing the time interval between the word-line activation (WL turns to high in Fig. 7.4) and the sense amplifier activation (SA_EN turns to high), the required voltage difference on the bit lines can be established. Obviously, this will result in the increment of the overall response delay of the sense amplifier. However, aiming to negate aging effects and ensure the reliable operation of the SRAM, the proper adjustment of the time interval between the word-line activation and the sense amplifier activation is a viable solution. The

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Fig. 7.18 Sense amplifier activation delay vs transistors’ Vt degradation

Fig. 7.19 Duty cycle ratio vs sense amplifier’s transistors Vt degradation (Vt shift)

delay on the activation of the sense amplifier vs the transistors’ threshold voltage shift |Vt |, which is required for the cancellation of the input offset voltage effects, is presented in Fig. 7.18. The plot in Fig. 7.19 presents the duty cycle ratio that is provided by the monitoring circuit against the threshold voltage shift |Vt | in the four transistors (MSP1, MSN2, MSP3 and MSN3 in Fig. 7.3) of the sense amplifier core for the typical process conditions. In a similar manner to the memory cell, in the sense amplifier case as the threshold voltage shift |Vt | increases, the duty cycle ratio is almost linearly decreased, as well. In Fig. 7.20(a) the waveform of the oscillation signal of a “fresh” sense amplifier (without any transistor degradation – no transistor threshold voltage shift exists – Vt = 0) during the test mode is presented. Next, in Fig. 7.20(b) the same signal waveform is illustrated for an aged sense amplifier (transistor degradation exists due

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Fig. 7.20 Waveforms of the oscillation signal for (a) a “fresh” sense amplifier and (b) an aged sense amplifier (|Vt | = 60 mV)

to an absolute threshold voltage shift equal to |Vt | = 60 mV for the above four transistors). Once again, from the simulations we observe that under Vt degradation the duty cycle of the generated signal is altered.

7.6.2.2

Process, Voltage and Temperature Dependencies

The influence of process, voltage and temperature variations for the case where the sense amplifier is under monitoring is discussed next. Initially, according to Monte Carlo analysis results on 1000 instances both for a “fresh” sense amplifier case as

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well as for an aged sense amplifier with a threshold voltage shift of 150 mV, the circuits’ distribution with respect to their duty cycle ratio is derived in Fig. 7.21. As expected, in the presence of aging the distribution shifts to lower duty cycle ratios. The results are similar to these for the case of the memory cells. Premature aging is also observed for the sense amplifiers. Once again, depending on the memory specifications and measurement data, a duty cycle ratio limit (reference duty cycle value) is specified, which after digitization is stored in a small ROM in the memory. The reference duty cycle corresponds to a sense amplifier that is aged enough although it does not generate failures during the SRAM operation. Sense amplifiers with a duty cycle below this reference value are characterized as over-skewed (either if they are “fresh” or aged), and a repair procedure must be applied in order to retain the memory reliable operation. The influence of voltage variations (±10% of the nominal power supply voltage) and the influence of temperature variations are presented in Figs. 7.22 and 7.23 respectively, for the “fresh” sense amplifier and aged sense amplifiers with a

Fig. 7.21 Process variation-related circuits’ distribution

Fig. 7.22 Voltage variation influence on the sense amplifier monitoring procedure

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Fig. 7.23 Temperature variation influence on the sense amplifier monitoring procedure

Fig. 7.24 Actual vs expected duty cycle ratio for various threshold voltage shift values

threshold voltage shift equal to 60 mV and 150 mV. As in the case of the memory cells, overaged sense amplifiers are still detectable in the presence of these variations.

7.6.3 The Digitizer’s Efficiency The efficiency of the digitizer block in Fig. 7.7 mainly depends on the frequency of the system clock signal (CLK) that is used for the sampling of the generated oscillation signal as well as the measurement time during the testing sessions. A quantization error is introduced by this procedure. Experimental results are presented in Fig. 7.24, where the measured by the digitizer duty cycle ratio is compared with the expected ratio for various threshold voltage shift values. The digitizer design is in the same 90 nm technology of UMC as the bit-line slice in

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Fig. 7.4. Both the HC and LC counters are 9-bit counters, while the clock (CLK) frequency is 2.5GHz. As we observe, the maximum quantization error introduced by the digitizer is 6.55%. This error can be further reduced by increasing the number of the counters bits and/or the clock frequency.

7.6.4 Performance and Power Consumption Effects For the design under consideration, the impact of the monitoring circuitry on the read response delay time of the memory is 2.80%. Since during the normal mode of operation the DRO is isolated from the sense amplifier, this small performance degradation is related to the extra parasitic capacitance of the switches SCL, SCR, SSL and SSR (see Fig. 7.4) that are attached on the bit lines and the inputs of the sense amplifier core. Considering the power consumption, the DROs and the digitizer are inactive during the normal mode of operation so that their impact is negligible. The only influence is related to the small parasitic capacitance of the DRO switches. The power consumption increment is only 1.24%. The silicon area cost of the DRO circuit is about 5.5% per bit-line slice, which incorporates 256 memory cells, the pre-charge circuit, the access transistors and the sense amplifier (the write circuitry is not included in this estimation). Given that a sense amplifier is shared between two memory blocks, the actual silicon area cost is less than 2.75%. For larger memory, arrays this cost is even less. Note that a single digitizer is used for the whole memory and the silicon area cost of this block is quite small.

7.6.5 Testing Procedure Aiming to ensure the reliable operation of an SRAM throughout its whole lifetime, the duty cycle ratio reference values must be updated after every repair operation. Moreover, after each system power-up, the memory operating status, due to earlier repair actions, must be retrieved. The testing procedure in Fig. 7.25 can be adopted. At the system power-up, the reference duty cycle values of the memory cells and the sense amplifiers are transferred from the ROM to two dedicated registers. Next, the memory testing procedures are applied. This step is required due to possible aging of memory cells or sense amplifiers at previous system activations. In case that according to the testing result all memory cells and sense amplifiers are healthy, the system enters the normal mode of operation; else, a memory repair phase follows. In this phase, if a memory cell has been detected as overaged, memory redundancy can be exploited for repair. If a sense amplifier has been detected as overaged, the memory timing is properly adjusted in order to set the new aging tolerance margin. In parallel, the reference duty cycle ratio value in the corresponding register is

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also properly adjusted by a predetermined constant step. Combined information is exploited from the graphs in Figs. 7.18 and 7.19 for the sense amplifiers, in order to determine the increment of the time interval between the word-line activation and the sense amplifier activation and properly adjust the corresponding reference value. Next, a second testing phase is applied in case that the previous repair procedure does not cover the actual aging status of the memory. If needed a second repair phase is also applied and the pertinent duty cycle ratio reference values are re-adjusted. The procedure is repeated until all SRAM memory cells and sense amplifiers are reported as healthy (functional) by the testing procedures according to the actual duty cycle ratio reference values. Then, the system enters the normal mode of operation. According to the discussion in Sect. 7.4, the normal operation is periodically interrupted for an appropriate testing procedure that will permit the detection of SRAM memory cells or sense amplifiers that may be near failure.

7.7 Conclusion The reliable operation of nanometre technology SRAMs is seriously influenced by process variations and aging mechanisms like bias temperature instability (BTI) and hot carrier injection (HCI), since the performance characteristics of both the memory cells and the used sense amplifiers are affected. Aging prediction techniques are mandatory in order to timely react, before errors generation, and maintain the memory reliable operation. Towards this direction, periodic aging monitoring by embedded sensors seems to be a promising solution. Desirable features of such an aging monitoring scheme are:

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• The ability to early react for memory repair after the detection of an overaged module that is near failure. • The reduced influence on the performance (speed and power) of the memory. The normal operation should not be altered. • The reduced silicon area overhead. • The ability to avoid the aging of the pertinent monitoring circuitry during the normal mode of SRAM operation. • The ability to reuse it for manufacturing memory characterization and testing.

References 1. Agbo, I., Taouil, M., Kraak, D., Hamdioui, S., Kukner, H., Weckx, P., Raghavan, P., & Catthoor, F. (2017). Integral impact of BTI, PVT variation, and workload on SRAM sense amplifier. IEEE Transactions on VLSI Systems, 25(04), 1444–1454. 2. Pae, S., Maiz, J., Prasad, C., & Woolery, B. (2008). Effect of BTI degradation on transistor variability in advanced semiconductor technologies. IEEE Transactions Device and Materials Reliability, 8(3), 519–525. 3. Cacho, F., Singh, S. K., Singh, B., Partasarathy, C., Pion, E., Argoud, F., Federspiel, X., Pitolet, H., Roy, D., & Huard, V. (2011). Hot carrier injection degradation induced dispersion: model and circuit-level measurement. In IEEE international integration reliability workshop (pp. 137–141). 4. Dounavi, H-M., Sfikas, Y., & Tsiatouhas, Y. (2018). Aging monitoring in SRAM sense amplifiers. In International conference on modern circuits and systems technologies (MOCAST). 5. Kraak, D., Taouil, M., Agbo, I., Hamdioui, S., Weckx, P., Kukner, H., Cosemans, S., & Catthoor, F. (2017). Impact and mitigation of sense amplifier aging degradation using realistic workloads. IEEE Transactions on VLSI Systems, 25(12), 3464–3472. 6. Kraak, D., Agbo, I., Taouil, M., Weckx, P., Cosemans, S., Catthoor, F., Dehaene, W., & Hamdioui, S. (2007). Mitigation of sense amplifier degradation using input switching. Design Automation and Test in Europe Conference (DATE) (pp. 858–863). 7. Kang, K., Alam, M. A., & Roy, K. (2007). Characterization of NBTI induced temporal performance degradation in nano-scale SRAM array using IDDQ. In IEEE international test conference (ITC) (p. 11.1). 8. Toh, S. O., Guo, Z., Liu, T.-J. K., & Nikolic, B. (2011). Characterization of dynamic SRAM stability in 45 nm CMOS. IEEE Journal of Solid-State Circuits, 46(11), 2702–2712. 9. Ceratti, A., Copetti, T., Bolzani, L., Vargas, F., & Fagundes, R. (2014). An on-chip sensor to monitor NBTI effects in SRAMs. Springer Journal of Electronic Testing: Theory & Applications, 30, 159–169. 10. Wang, X., Keane, J., Kim, T. T.-H., Jain, P., Tang, Q., & Kim, C. H. (2014). Silicon odometers: Compact in situ aging sensors for robust system design. IEEE Micro, 34(6), 74–85. 11. Tsai, M-C., et al. (2012). Embedded SRAM ring oscillator for in-situ measurement of NBTI and PBTI degradation in CMOS 6T SRAM array. In International symposium on VLSI design, automation and test (VLSI-DAT). 12. Alorda, B., Carmona, C., Torrens, G., & Bota, S. (2016). On-line write margin estimator to monitor performance degradation in SRAM cores. In IEEE international symposium on online testing and robust system design (IOLTS) (pp. 90–95). 13. Huard, V., Partasarathy, C., Guerin, C., Valentin, T., Pion, E., Mammasse, M., Planes, N., & Camus, L. (2008). NBTI degradation: From transistor to SRAM arrays. In IEEE 46th annual international reliability physics symposium (PRS) (pp. 289–300).

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14. Haggag, A., Anderson, G., Parihar, S., Burnett, D., Abeln, G., Higman, J., & Moosa, M. (2007). Understanding SRAM high-temperature-operating-life NBTI: Statistics and permanent vs recoverable damage. In IEEE 45th annual international reliability physics symposium (PRS) (pp. 452–456). 15. Tsiatouhas, Y. (2017). Periodic bias-temperature instability monitoring in SRAM cells. In IEEE European test symposium (ETS). 16. Ahmed, F., & Milor, L. (2016). Online measurement of degradation due to bias temperature instability in SRAMs. IEEE Transactions on VLSI Systems, 24(06), 2184–2194. 17. Rahma, M., Chen, Y., Sy, W., Ong, W-L., Ting, L-Y., Yoon, S-S., Han, M., & Terzioglou, E. (2011). Characterization of SRAM sense amplifier input offset for yield prediction in 28nm CMOS. In IEEE international custom integrated circuits conference (CICC). 18. Kumar, S. V., Kim, C. H., & Sapatnekar, S. S. (2006). Impact of NBTI on SRAM read stability and design for reliability. In 7th international symposium on quality electronic design (pp. 213–218). 19. Qin, J., Li, X., & Bernstein, J. B. (2007). SRAM stability analysis considering gate oxide SBD, NBTI and HCI. In International integrated reliability workshop (IRW) (pp. 33–37). 20. Liu, T., Chen, C-C., Wu, J., & Milor, L. (2016). SRAM stability analysis for different cache configurations due to bias temperature instability and hot carrier injection. In IEEE 34th international conference on computer design (ICCD) (pp. 225–232). 21. Khan, S., Agbo, I., Hamdioui, S., Kukner, H., Kaczer, B., Raghavan, P., & Catthoor, F. (2014). Bias temperature instability analysis of FinFET based SRAM cells. In Design and test in Europe conference (DATE). 22. Sfikas, Y., & Tsiatouhas, Y. (2017). BTI and HCI degradation detection in SRAM cells. In International conference on modern circuits and systems technologies (MOCAST). 23. Sfikas, Y., & Tsiatouhas, Y. (2017) Variation tolerant BTI monitoring in SRAM cells. In IEEE international symposium on on-line testing and robust system design (IOLTS) (pp. 100–105). 24. Agbo, I., Taouil, M., Hamdioui, S., Weckx, P., Cosemans, S., Raghavan, P., Catthoor, F., & Dehaene, W. (2016). Quantification of sense amplifier offset voltage degradation due to zeroand run-time variability. In IEEE computer society annual symposium on VLSI (ISVLSI) (pp. 725–730). 25. Kinseher, J., Heib, L., & Polian, I. (2017). Analyzing the effects of peripheral circuit aging of embedded SRAM architectures. In Design automation and test in Europe conference (DATE) (pp. 852–867). 26. Seevinck, E., List, F. J., & Lohstroh, J. (1987). Static-noise margin analysis of MOS SRAM cells. IEEE Journal of Solid-State Circuits, 22(5), 748–754.

Chapter 8

A Cost-Efficient Aging Sensor Based on Multiple Paths Delay Fault Monitoring Gaole Sai, Mark Zwolinski, and Basel Halak

8.1 Introduction Process and ageing variations are becoming the major reliability issues in modern semiconductor technologies. Those phenomena result in speed degradation of integrated circuits (ICs) and, therefore, delay faults. To prevent the failures caused by delay faults, the performance of ICs is usually constrained by large safety margins [1]. This means the ICs are designed for the specific circumstance that a circuit is running under the worst-case operating conditions, which will limit the performance and increase the power consumption of ICs [2]. In situ delay fault monitoring schemes have been proposed to ensure the reliability of an IC during its lifetime. Such schemes are usually based on the application of ageing sensors in monitoring the failure of a circuit before the actual delay fault occurs. The system will then scale its operating frequency or supply voltage adaptively based on its actual operating conditions to remove the unused margins and compensate for the performance degradation from the process, voltage, temperature and ageing variations [3]. A number of sensors have been proposed for in situ delay fault monitoring. Those sensors can be classified as delay fault detection and prediction techniques [4, 5]. Traditional delay fault monitoring sensors are usually implemented on the nearcritical paths of a circuit. However, the increasing complexity and technology shrinking of ICs have increased the number of near-critical paths and potential ageing-critical paths significantly [6]. This means the cost of in situ delay fault

G. Sai · M. Zwolinski · B. Halak () The School of Electronics and Computer Science, University of Southampton, Southampton, UK e-mail: [email protected] © Springer Nature Switzerland AG 2020 B. Halak, Ageing of Integrated Circuits, https://doi.org/10.1007/978-3-030-23781-3_8

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monitoring is becoming prohibitive. Therefore, a major challenge of such approach is to minimise the area overhead with an increase in near-critical paths and potential ageing-critical paths [7].

8.2 Chapter Overview This chapter presents a new design for a multiple paths delay monitor that used to predict ageing-induced timing errors. The rest of the chapter is organised as follows. Section 5.3 reviews two traditional delay fault monitoring techniques, Razor FF and Canary FF. Section 5.4 first introduces a cost-efficient delay fault monitoring technique named DMEDS that is specifically designed for ageing prediction and the case studies of the DMEDS in transistor and system level. It then presents the comparison between the traditional techniques and the DMEDS. Conclusions are drawn in Sect. 8.5.

8.3 A Review of Existing Ageing Sensor 8.3.1 Razor FF Razor FF [4] is a delay fault detection sensor, which is a flip-flop-type sensor using the double sampling technique. It detects the consistency of the output signal from a near-critical path after the rising clock edge. As Fig. 8.2 shows, Razor FF consists of a main Flip-Flop, a shadow latch, a multiplexer, one delay element and an error detector circuit. The shadow latch receives data as a reference which is sampled after clock rising edge to help the detection circuit detecting the delay faults. The error signal is generated by comparing the data between the main FF and shadow latch. Razor FF is a fault-tolerant sensor which is able to restore the data when the sample is missed. The delay element generates a detection window, Tdel, shown in Fig. 8.1. Transitions in this detection window, Tdel, will cause the shadow latch to sample a different signal with the main FF, which, therefore, triggers the error signal as the inconsistency between the samples from the main FF and the shadow latch. Usually, there are two methods to correct this error: Suspend the process for one clock cycle then restore the data in the shadow latch via the multiplexer in the next clock cycle shown in Fig. 8.2 or replay the instruction at system level [5]. Razor FFs are typically implemented on the critical paths of logic designs, but they only detect a timing error after it occurs; therefore, they cannot be used for predicting ageing-induced delay faults unless the design is modified accordingly, which would further increase its area overheads. Razor FF can only detect the delay faults in one path, and the area cost for multiple paths monitoring using Razor can be prohibitive. The timing degradation of paths increases with circuit ageing; the slack

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Fig. 8.1 The Razor FF and Timing Diagram

between the rising clock edge and the transition of the input signal will decrease. Hence, the input signal will first violate the setup time of the main FF. Meta-stability will occur in the main FF when the clock and input change about the same time. Therefore, the checking circuitry is required to detect meta-stability in the main FF, shown in Fig. 8.1. Moreover, as a delay fault detection sensor, Razor is not suitable for ageing prediction, because the upcoming timing error is unpredictable in this case.

8.3.2 Canary FF Unlike delay fault detection sensors, like Razor FF, the Canary FF [5], shown in Fig. 8.2, is a delay fault prediction sensor that checks data consistency before the rising clock edge. Canary FF consists of a main flip-flop, a shadow flip-flop, one delay element and a comparator. As shown in Fig. 8.2, the shadow FF receives delayed data as a reference and compares it with the data from the main FF. As the

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path ages, the error signal will be triggered if the delayed data violates the setup time of the shadow FF. Canary FF has a small safety margin to detect if a delay fault is about to occur. As a delay fault prediction sensor, Canary FF is more suitable for ageing detection compared to Razor. In this case, the input signal may violate the setup time of the shadow FF because of circuit ageing, not the main FF. Therefore, it does not require any circuitry for timing error recovery nor meta-stability detection for the main FF such as Razor FF. However, meta-stability occurring in the shadow FF will cause errors. On the other hand, implementing a shadow FF of the same size will cause a relatively large area overhead. As a delay fault prediction sensor, Canary is suitable

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for ageing prediction. However, a Canary FF can only detect the timing error for one path. Therefore, the area cost for multiple paths monitoring might be prohibitive.

8.4 Differential Multiple Error Detection Sensor This section introduces the operating principles of the DMEDS. The major advantages of DMEDS compared with traditional sensors are: 1. DMEDS monitors multiple paths simultaneously, therefore, a cost-efficient sensor. 2. As an external sensor, DMEDS does not replace the flip-flops of the original circuit. Thus, the DMEDS is easy to implement. Moreover, the implementation of DMEDS will have less influence on the functionality and performance of the original circuit. 3. DMEDS is metastability resistant as it is an error prediction sensor. It predicts the delay faults before the transition from a path violates the setup time of the original flip-flops of the original circuit.

8.4.1 Operating Principles of DMEDS Figure 8.3 shows the architecture of DMEDS. As the figure shows, the DMEDS monitors the delay faults from multiple paths at the same time. Thus, it significantly improves the cost-efficiency compared with traditional ageing sensors such as Razor FF and Canary FF. As shown in Fig. 8.3, DMEDS replaces the error predict circuitry

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with the multiple detection unit (MDU) and a stability detector (SD) compared with Canary FF. The major advantages of DMEDS over the traditional ageing sensors are its cost-efficiency and metastability resistant. The MDU is a multiple input XOR gate, and it monitors the transitions from two or more potential critical paths simultaneously. The transition from one of those input signals will upturn the output signal of the MDU. The SD will then capture the upturned signal when it occurs during the detection period of the SD, therefore, triggering the error signal. The MDU generates a small margin from its delay, and the SD checks the stability of the delayed signal when the clock signal is logic ‘1’. Thus, the detection window of the DMEDS begins from DMDU before the clock rising and DMDU before the clock falling, where DMDU is the propagation delay of the MDU. The small margin DMDU detects the delay fault before it actually occurs; hence, DMEDS is a delay fault prediction sensor. The small margin DMDU can be scaled by adjusting the transistor size of the MDU or insert buffers [8]. However, the DMEDS may trigger an incorrect error signal if a short path shares the same end with the potential critical path. Therefore, clock duty cycle needs to be scaled while the DMEDS implementation to make sure the transitions from all paths that share the same monitoring point respect the detection window, [9], during the circuit’s lifetime. In practice, it is almost impossible that more than one input data of the MDU coverage at the same time. Assuming that the transitions between the input signals of the MDU always have timing differences, therefore, any transition from the input data of the MDU will flip the output signal of MDU. However, the MDU will not be aware of the differences between the transitions if the transitions between the input signals are very close and the sensitivity of the MDU is not high enough to recognise the timing differences. Therefore, the traditions will become undetectable if an even number of transitions occurs at about the same time. In reality, the transitions from different potential critical paths will not be 100% correlated, as shown in Sect. 8.4.3. Transitions of the MDU input signals will be detected by the MDU eventually when an odd number of potential critical paths are assessed. As the DMEDS is a delay fault prediction sensor, it is not necessary to detect every single transition of the MDU input signal during the circuit’s lifetime, if some transitions are detected before a delay fault actually occurs in a potential critical path. The SD checks the stability of the output signal from the MDU. It triggers the error signal if MDU output signal flips during the stability checking period. The stability checking period starts from the clock rising edge and ends the clock falling edge. As Fig. 8.4 shows, the signal ‘Error’ will be triggered if the signal ‘Transition’ flips while the ‘Clock’ signal is ‘1’. There are three typical cases during the DMEDS monitoring two or more paths of a circuit, as shown in Fig. 8.4(I), (II) and (III). ‘Path 1’ and ‘Path N’ are chosen to illustrate the operation, but the principle applies to any two paths of to the situations where ‘Path 1’ is ageing faster than ‘Path N’. (I) At the time zero, the intrinsic delay of ‘Path N’ is smaller than the intrinsic delay of ‘Path 1’. As static timing analysis tools have optimised the circuit,

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(I) At Time Zero

(II) After Ageing

(III) Unpredictable Error

Fig. 8.4 Timing diagram of DMEDS

the transitions from any paths should not violate the detection window (DW) in this case. Therefore, the error signal of the DMEDS is not triggered. (II) Both ‘Path 1’ and ‘Path N’ age during the circuit’s operating time. Assuming that ‘Path N’ is ageing much faster than ‘Paths 1’, after a certain period, the transitions from ‘Path N’ violates the DW before the transitions from ‘Path 1’ (and other paths). The output signal of MDU is flipped by the transition in ‘Path N’, while Clock signal is ‘1’ (within the detection period of the SD). The SD then captures the transition of MDU output and triggers the error signal. (III) Assuming that ‘Path N’ is ageing slightly faster than ‘Path1’, the difference between the intrinsic from those two paths is becoming smaller and smaller during the circuit’s operation time. After a certain period of time, both ‘Path 1’ and ‘Path N’ violate the DW. The difference between the intrinsic of ‘Path 1’ and ‘Path N’ is too small to be recognised by the MDU. A glitch is generated when ‘Path 1’ and ‘Path N’ flip at about the same time. The stability checker does not capture the glitch. The delay faults of both two paths become unpredictable in this case. This situation arises because of correlation between paths; in reality, the transitions from different potential critical paths will not be 100% correlated. Transitions of the MDU input signals will be detected by the MDU eventually when an odd number of potential critical paths are assessed (see Sect. 8.4.3). In practice, delay fault monitoring sensors would not be implemented on every path. A limited set of paths should be selected [10]. The ranking of the potential critical paths might change after fabrication because of process variations, or after a certain time due to ageing variations. Hence, the near-critical paths and potential critical paths identification is required at time zero and after ageing is required before ageing sensors are implemented. The width of DW and setup time of the flip-flops will also be degraded after ageing. The detection window must be adjusted according to the worst-case process and ageing variations to ensure the DW degrades faster than the setup time.

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8.4.2 Transistor Level Design of DMEDS This section presents a case study of the transistor level design of DMEDS that has been implemented using a 32 nm CMOS technology node. Figure 8.5a shows the circuit schematic of a 2-input MDU, which is a 6 transistors XOR gate. Figure 8.5b shows the circuit schematic of the SD. The SD checks the stability during its checking period. During the checking period (when the clock is ‘1’), node X will be pulled down if the input signal ‘In’ is logic ‘1’, and node Y will be pulled down if the input signal ‘In’ is logic ‘0’. Nodes X and Y are the input signals of a 4 transistors NOR gate. The error signal will be triggered once both of nodes X and Y are pulled down during the same checking period. In another word, the flip of the input signal ‘In’ during the same checking period will trigger the error signal. Transistors T4 and T6 increase the sensitivity of SD. Nodes X and Y will be pulled down if the error signal remains between logic ‘1’ and ‘0’. The error signal will be cleared after the falling clock edge; therefore, it needs to be stored before the falling clock edge. As Fig. 8.4 (III) shows, the output signal of the MDU will not be a strong pulse if the timing difference between input signals is smaller than the minimum measurement resolution, which can be scaled by tuning transistor sizes [8]. Figure 8.6 shows the transistor simulation results when the DMEDS is monitoring two paths simultaneously at time zero and after 10 years. The degradation from ageing variations was estimated by the Synopsys HSPICE MOSRA. As Fig. 8.6a shows, the transitions from both paths arrive without violating the DW at time zero. Both transitions flip the output signal ‘transition’ and, therefore, generates a pulse signal. The signal ‘error’ is not triggered as the signal ‘transition’ stays at logic ‘0’ during the checking period of the SD. Figure 8.6b shows the simulation result for DMEDS after 10 years ageing. The width of DMDU has increased 24.5% after 10 years. In this case, both signals from Path 1 and Path 2 switch at the same times as in Fig. 8.6a. The transition from ‘Path 2’ arrives late, and it violates the DW. As a consequence, the second flip of the signal ‘transition’ caused by ‘Path 2’ switches

Fig. 8.5 Transistor Level Design of DMEDS

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Fig. 8.6 Multiple Timing Error Detection

within the checking period of the SD, which, therefore, triggers the error signal. The transition from ‘Path 1’ and ‘Path 2’ are propagated to the output signals of flip-flops, ‘q1’ and ‘q2’, after clock rising. Hence, there is no delay fault actually occurred.

8.4.3 System Level Design of DMEDS This section presents the case study of the system level design of DMEDS. The potential critical paths should be identified before the DMEDS implementation. A 32-bit pipelined MIPS in this case. The monitored paths were identified by performing static timing. The potential critical paths can be classified as follows: 1. Completely De-correlated: Write the data back to the specific bits of different addresses. The transitions between paths are 100% de-correlated in this case, as the data cannot be written to different addresses in the same clock cycle. 2. Partial Correlated: Write the data back to the specific bits of the same address or read the data from the register file. More than one critical path will be accessed simultaneously in this case. Assuming that the signal probability of each bit of

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Fig. 8.7 Percentage of Transitions

data is 50%, then the switching rate of each bit of data will be 0.28. Figure 8.7 shows the transition probability of potential critical paths, according to Eq. (8.1), odd transitions (OT), (8.2), even transitions (ET) and (8.3) no transitions (NT), respectively, where α is the switching rate and n is the number of potential critical paths. As Fig. 8.7 shows, the transition probability of OT is generally higher than ET. The correlation between the transitions increases with the growth of n. In this case, the error signal will not be 100% triggered when the transitions from potential critical paths violate the DW. However, the violations will eventually be detected when an odd number of potential critical paths are assessed. In the worst case, the probabilities of even and odd transitions are 50% with a 99% confidence level and ±4% interval in every 1000 clock cycles, shown in Fig. 8.7. Thus, accuracy depends on the number of potential critical paths which are monitored by a single DMEDS and the error sampling size of the system. 3. Highly Correlated: Data is assigned to the longest carry chain in the ALU. A few paths are sharing the carry chain; therefore, the correlation rate between those paths will be high in this case. However, the workload will be the same of the shared paths. Thus, only one of those paths needs to be monitored by the DMEDS in this case. In the worst-case, the highly correlated paths should be monitored by different DMEDSs. 

i

n−1 C (2k + 1, n) α , i≤ (1 − α) 2 k=0 i 

n C (2k, n) α 2k (1 − α)n−2k , i ≤ 2 2k+1

n−(2k+1)

 (8.1) (8.2)

k=1

(1 − α)n

(8.3)

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An equivalent circuitry of DMEDS has been used to verify the functionality of the DMEDS at the system level, as shown in Fig. 8.8. The behaviour of the circuitry is identical to the behaviour of DMEDS shown in Fig. 8.4. Figure 8.9 shows the system simulation result when the DMEDS is monitoring ten specific bits from ten different register files. All of the error signals are triggered when late transitions are detected by the 10-input DMEDS as they are 100% decorrelated.

Fig. 8.8 Equivalent Circuitry of DMEDS and Simulation Result

Fig. 8.9 10-input DMEDS functionality verification in a 32-bit MIPS

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Table 8.1 Comparison with other traditional ageing sensors FF type Extra number of transistors (I) Metastability Error recovery required Replace FFs Latch type Extra number of transistors (III) Metastability Error recovery required Replace FFs

Razor [4] 54 225% Yes Yes Yes Razor II 39 243.7% No Yes Yes

Canary [5] 30 125% Yes No No DSTB [12] 34 212.5% No Yes Yes

Razor-lite [11] 8 33.3% Yes Yes Yes iRazor [9] 9.46 59.1% No Yes Yes

DMEDS (II) 6.7 27.9% No No No DMEDS (II) 6.7 41.9% No No No

(I) Compared to standard 24T FF (excluding the delay chain) (II) 10-Input DMEDS monitors 10 paths simultaneously (nine 2-input XOR (54T) and one stability checker (13T) shared) (III) Compared to standard 16T latch

8.4.4 Cost Comparison with Other Traditional Ageing Sensors Table 8.1 shows a cost and performance comparison with different ageing sensors. The area overhead of flip-flop type sensors is compared with the standard 24 transistors flip-flop. Compared with Razor and Canary and Razor-lite, DMEDS saves 197.1%, 97.1% and 5.4% of the transistors, respectively, when ten paths are monitored by one 10-input DMEDS simultaneously. On the other hand, DMEDS is able to predict delay faults as a latch-type sensor. The overhead of a latchtype sensor is compared with the standard 16 transistor latch, Table 8.1. compared with Razor II, DSTB, and iRazor, DMEDS saves 201.8%, 170.6% and 17.2% of the transistors, respectively, for 10 path delay fault monitoring. DMEDS has significantly reduced the area overhead compared with other ageing sensors.

8.5 Conclusions This chapter introduced a state-of-the-art in situ delay monitoring technique, Differential Multiple Error Detection Sensor (DMEDS) [7]. This is a case study of how the DMEDS monitors multiple paths simultaneously. Compared with Razor [4], Canary [5], DSTB [9], iRazor [9], Razor-lite [11] and Razor II, DMEDS saves at least 197.1%, 97.1%, 170.6%, 17.2%, 5.1% and 201.8% of the transistors, respectively. Therefore, the DMEDS significantly reduces the area overhead. As an external sensor, DMEDS does not replace the flip-flops of the original circuit; therefore, the DMEDS is easy to implement. Moreover, the implementation of DMEDS will have less influence on the functionality and performance of the original circuit. Moreover,

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DMEDS is metastability resistant as it is an error prediction sensor. It predicts the delay faults before the transition from a path violates the setup time of the original flip-flops of the original circuit.

References 1. Mintarno, E., Skaf, J., Zheng, R., et al. (2016). Self-tuning for maximized lifetime energyefficiency in the presence of circuit aging, “ERSUT: A self-healing architecture for mitigating PVT variations without pipeline flushing”. IEEE Transactions on Circuits and Systrems II Express Briefs, 63(11), 1069–1073. 2. Agwa, S., Yahya, E., & Ismail, Y. (2011). Self-tuning for maximized lifetime energy-efficiency in the presence of circuit aging. IEEE Transactions on Computer-Aided Design Integrated Circuits and Systems, 30(5), 760–773. 3. Martins, C. V., Semio, J., Vazquez, J. C., et al. (2011). Adaptive error-prediction flip-flop for performance failure prediction with aging sensors. VLSI Test Symposium (VTS), 2011 IEEE 29th IEEE, 203–208. 4. Ernst, D., Kim, N. S., Das, S., et al. (2003). Razor: A low-power pipeline based on circuit-level timing speculation. Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture. IEEE Computer Society, 7. 5. Fuketa, H., Hashimoto, M., Mitsuyama, Y., et al. (2012). Adaptive performance compensation with in- situ timing error predictive sensors for subthreshold circuits. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 20(2), 333–343. 6. Calimera, A., Macii, E., & Poncino, M. (2012). Design techniques for NBTI tolerant powergating architectures. IEEE Transactions on Circuits and System II Express Briefs, 59(4), 249– 253. 7. Sai, G., Halak, B., & Zwolinski, M. (2018). Multi-path aging sensor for cost-efficient delay fault prediction. IEEE Transactions on Circuits and Systems II Express Briefs, 65(4), 491–495. 8. Alioto, M., Consoli, E., Palumbo, G., et al. (2010). IEEE transactions on circuits and systems I: Regular papers. IEEE Transactions on Circuits and Systems I, 57(7), 1583–1596. 9. Zhang, Y., Khayatzadeh, M., Yang, K., et al. (2016). iRazor: 3-transistor current-based error detec- tion and correction in an ARM Cortex-R4 processor. Solid-State Circuits Conference (ISSCC), 2016 IEEE International. IEEE, 160–162. 10. Semio, J., Saraiva, D., Leong, C., et al. (2014). Performance sensor for tolerance and predictive detection of delay-faults. Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2014 IEEE International Symposium on. IEEE, 110–115. 11. Kim, S., Kwon, I., Fick, D., et al. (2013). Razor-lite: A side-channel error-detection register for timing- margin recovery in 45nm SOI CMOS. Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013 IEEE International. IEEE, 264–265. 12. Bowman, K. A., Tschanz, J. W., SLL, L., et al. (2011). A 45 nm resilient microprocessor core for dynamic variation tolerance. IEEE Journal of Solid-State Circuits, 46(1), 194–208.

Index

A Adaptation frequency, 172–173 on-chip ageing monitoring (see Ageing monitoring) supply voltage, 172 Adaptive architectures voltage and frequency scaling adaptive voltage scaling implementations, 173–174 frequency adaptation, 172–173 supply voltage adaptation, 172 Adaptive body bias (ABB) vs. AVFS, 176–177 back body bias concept, 175 classic approach, 174–175 FBB and RBB, 175 Fmax distribution, 176 Ageing-aware logic synthesis BTI, 113 CMOS lifetime reliability, 113 See also Logic synthesis Ageing-aware transformation gate-level optimization, 138–143 logic restructuring, 126–132 technology mapping, 132–138 Ageing effects BTI-induced performance degradation, 35 CMOS threshold, 113 extra-functional properties, 3 hierarchical levels, 151 NBTI, 6 oxide traps, 19 SER, 36 technology node, 31

© Springer Nature Switzerland AG 2020 B. Halak, Ageing of Integrated Circuits, https://doi.org/10.1007/978-3-030-23781-3

Ageing mitigation BTI (see Bias temperature instability) cache memories, 98–103 discussion, 87–89 evaluation, 84–87 high-level data control, 69–70 instruction cache-based PUF, 103–109 MOSFET devices, 91 NBTI/PBTI, 67, 92 proposed technique application-level BTI balancing, 82–84 ATPG, 82 SBST, 67 SP (see Signal probability) SRAM (see Static random-access memory) Ageing models accurate prediction, 3 critical path determination, 30–31 explicit trap, 19–20 extra-functional properties, 3 FDIV bug, 4 mission scenarios, 8–9 MOSFET transistor basics, 10–12 phenomena, 6–8 stochastic trap, 20–23 system’s performance, 3–4 terminology, 4–6 Ageing monitoring CMOS transistor’ sizes, 150 NBTI and HCI, 152–156 NTV, 149 performance (see Performance) and reliability monitors (see Reliability) reliability of systems, 149

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226 Ageing monitoring (cont.) topology circuitry, 188–190 digitizer block, 193–195 DRO, 190, 191 monitoring methodology, 191–193 Aging monitors bit-line slice modifications, 183 BTI and HCI, 181 ECCs, 182 embedded ring oscillators, 182 experimental results, 195–196 IDDQ current, 182 manufacturing testing operations, 195 memory cell BTI degradation, 183 nMOS transistors, 184 SRAM memory cells, 181, 184 Anti-aging software, 80, 86–89

B Bias temperature instability (BTI) ageing modelling for (see Circuit-level analysis) behaviour, 12 gate-level stress balancing, 77–81 logic gates and circuits (see Logic gates) reaction-diffusion model, 13 and RTN, 17 SER (see Soft error rate) stress analysis (see Stress analysis) Bit-flips, 94, 98–101, 109

C Canary FF, 213–215 Capture-emission time (CET) abstraction, 24–27 ageing modelling, 22 behaviour, 23 individual trap distribution, 21 threshold voltage, 21–22 Circuit-level analysis BTI-induced degradation, 38 logic gate, 39 MOS transistors, 36–37 nMOS transistors, 37 operating time, 40 transistor threshold voltage variation, 37, 38 CMOS circuits OR gate, 71 SER (see Soft error rate)

Index Combinational logic BTI-induced SER, 53–55 n/pMOS transistor, 48 PMOS transistor, 71 and storage elements, 36 symmetric minimum-sized NOT gate, 49–51 NOR and NAND gates, 51–53 velocity saturation, 49 voltage glitch, 47 Cost-efficient aging delay fault detection, 211 ICs, 211 Critical path block-based, 30 BTI-balancing program, 87 BTI selection, 70–71 determination, 30–31 DMEDS implementation (see Differential multiple error detection sensor) estimation of ageing, 29 logic designs, 212 near-critical path, 212 path-based, 29 sensor architecture, 158 SP(0) distribution, 71–75 sub-circuit, 70 D Delay BTI-induced delay shift, 116 combinational circuits, 36 degradation functions, 30 logic gates and circuit (see Logic gates) measurement monitors, 161–162 path degradation, 81, 116 post-ageing, 124 propagation path, 5, 161 self-oscillating paths, 157 Differential multiple error detection sensor (DMEDS) advantages, 215 cost comparison, 222 operating principles, 215–217 system level design, 219–222 transistor level design, 218–219 Differential ring oscillator (DRO), 190, 191 Digital circuits, 6, 23, 28, 91, 143, 167 Digitizer block, 193–195 efficiency, 206–207 Double sampling with time borrowing (DSTB), 159

Index E Explicit trap model, 19–21, 27

F Flip-flops (FF) canary monitor, 161, 213–215 and latches, 156 level-sensitive latch, 159 Razor, 212–213 SETs, 56 type sensors, 222 Functional faults, 5, 6

H High-k devices, 6, 7, 11, 17 High-level worst-case estimation, 29–30 Hot carrier degradation (HCI) and BTI, 7 CET approach, 22 digital library cell performance, 151 hot electrons, 18 mechanism, 185 NBTI, 152–156 transistor’s threshold, 7

I IDDQ, 182 In situ monitors methodology ageing-aware gate characterization, 168–170 conventional monitor insertion, 165–168

L Lifetime abstraction analytic models, 23 CET map bins, 23 Logic gates ageing-aware gate library, 43–45 BTI-induced degradation, 43 and circuits, 39 CMOS, 48 delay degradation, 43–45 logic-level BTI mitigation, 132 stress condition, 68 stress probabilities calculation, 40–43 Logic synthesis basic flow, 114–115 optimization process, 115–116

227 M Masked fault, 5 Memories ageing mitigation techniques (see Ageing mitigation) bit flipping, 98–103 SRAM (see Static random-access memory) Metal oxide semiconductor field effect transistors (MOSFET) reliability issue, 91 threshold voltage shift, 36 transistor basics, 4, 10–12

N Netlist, 5, 28–30, 80, 114, 162, 165, 166

O Oxide defects device’s threshold voltage, 8 trap activation, 15–17 degradation, 17–19 formation, 12–15 Oxide layer, 10, 18

P Performance integrated circuits (see Ageing effects) memory cell, 186 and power consumption effects, 207 power-speed, 176 and reliability monitors (see Reliability) SNM degradation, 92 SRAM memory cell, 181 transistors, 28 PUF instruction cache-based, 103–109 SRAM, 92, 96

R Razor FF, 212–213 Reliability ageing effects (see Ageing effects) commercial synthesis tools, 116 delay measurement monitors, 161–162 detecting performance violations embedded monitors, 159–161 external-design monitors, 157–158 discussions, 162–164

228 Reliability (cont.) dual-function SRAM, 109 MOSFET, 91 SRAM, 95 synthesis, 116–118 ageing-aware (see Ageing-aware transformation) BTI-aware optimization techniques, 117 guard-banding method, 118–121 library re-characterization, 121–126

S Sense amplifier (SA), 187–188 process, voltage and temperature dependencies, 204–206 and repair options, 201–204 Sensors cost-efficient aging (see Cost-efficient aging) critical path, 158 dedicated, 182 operating conditions, 170 periodic aging, 208 Signal probability (SP) critical paths of the processor, 71–72 duty cycle, 68 gate-level simulations, 28 j-th clock cycle, 42 normalised propagation delay, 44 OpenRISC processor, 72–77 path delay degradation, 79 signal node, 68 stress table, 41 Single event transient, 46–48 Soft error rate (SER) CMOS circuits (see CMOS circuits) combinational logic (see Combinational logic)

Index single-event transients, 46–48 in storage (see Storage elements) Static random-access memory (SRAM) ageing impact as memories, 93–95 PUFs, 95–97 memory cells operation, 185–186 and repair options, 196–199 process, voltage and temperature dependencies, 199–201 SA operation, 186–187 testing procedure, 207–208 Stochastic trap models, 20–24, 26, 27 Storage elements BTI ageing, 56, 60–61 latch critical charge, 58–59 latch SER, 60–61 SER, 56 SET, 56 set-up time, 58–59 WOV, 57, 58 Stress analysis BTI-critical path selection, 70–71 instruction/program-level workload, 72, 76–77 SP(0) distribution, 71–72 T Transistors architecture-based solution, 3 CET map-based ageing, 22 HCI, 18 MOSFET (see Metal oxide semiconductor field effect transistors) pMOS, 36, 49 threshold voltage variation, 38 Trap activation, 15–18, 20, 27–29 Trap centric modelling, 27–29 Trap formation, 12–15, 17