Advances in Electronic Materials [1 ed.] 9783038132578, 9780878493470

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Advances in Electronic Materials

Advances in Electronic Materials

Special topic volume with invited papers only.

Edited by:

Erich Kasper Hans-Joachim Müssig Hermann G Grimmeiss

TRANS TECH PUBLICATIONS LTD Switzerland UK USA

Copyright  2009 Trans Tech Publications Ltd, Switzerland All rights reserved. No part of the contents of this publication may be reproduced or transmitted in any form or by any means without the written permission of the publisher. Trans Tech Publications Ltd Laubisrutistr. 24 CH-8712 Stafa-Zurich Switzerland http://www.ttp.net

Volume 608 of Materials Science Forum ISSN 0255-5476 Full text available online at http://www.scientific.net

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Preface This special topic volume ‚Advances in Electronic Materials’ covers different fields of materials such as silicon, silicon-germanium hetero-structures, high-k materials, III-V semiconductor alloys and organic materials as well as nano-structures for spintronics and photovoltaics. It starts with a brief summary of the formative years of microelectronics, which is a central area within information technology. Information technology is still one of the most important global technologies and an extremely complex area. Though electronic materials are primarily connected with computers, internet, or mobile telephones, they are used for many more applications to improve the quality of life for everyone. Progress in classical scientific fields such as physics, biology, chemistry, mechanics and software are often based on new developments within the area of electronic materials. The performance of electronic materials has made important progress during the last years and further improvements are expected. The second article summarises a few basic requirements and applications of future material systems by taking into account strong links to economics. New hetero-structure device concepts will be the basis for further improvements in micro- and optoelectronics and are described in detail in the subsequent chapter. High-permittivity (k) materials are playing an important role in downscaling both Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) and Dynamic Random Access Memories (DRAMs). Therefore, the next article presents a detailed study of the electrical properties of thin high-k dielectric films by paying particular attention to the strong impact of macroscopic, microscopic and atomic-size defects on leakage currents and reliability concerns in gate stacks. Today Non-Volatile Memories (NVM) represent a large portion of the overall semiconductor market and are considered as one of the most important technologies for the mobile application segment. The main technology line within this field is represented by the Flash Memory. In the following article alternative technologies are discussed which exploit new materials and concepts to go beyond the flash technology. The development of integrated circuits is based on a long and fascinating history, which is unique in modern time. Yet, the fantastic growth in semiconductor electronics is due to a unique combination of basic conceptional advances, the perfection of new materials and the development of new device principles. The next chapter therefore describes in more detail future material perspectives of nano-electronics and nano-spintronics by considering in particular nano-architecture and scalability issues. This chapter is followed by another article on future material perspectives covering organic materials. Organic materials have recently been developed to operate as the active semiconductor in a wide range of semiconductor devices, including field-effect transistors and photovoltaic diodes. These views on future perspectives are further discussed in the last chapter of the book, which reviews among other things the impact of nano-materials on photovoltaic power generation. Many new ideas have flooded the literature in the last few years most revolving around nanostructures. However, a dominant criterion in this connection is the performance-cost aspect, an essential prerequisite to large-scale adoption of these new perspectives. Fruitful discussions with Knut Deppert, Torsten Fritz, Karol Froehlich ,Hans-Joest Herzog, Reinhart Kuehne, Michael Oehme, Thomas Schroeder, Udo Schwalke and Wolfram Spitzberg are acknowledged. Erich Kasper

Hans-Joachim Müssig

Hermann G Grimmeiss

Table of Contents Preface Today’s Mainstream Microelectronics - A Result of Technological, Market and Human Enterprise H. Grimmeiss and E. Kasper Future Material Systems: Requirements and Applications E. Kasper, H.J. Müssig and H. Grimmeiss Silicon Based Heterostructures: Advances in Channel Materials E. Kasper The Influence of Defects and Impurities on Electrical Properties of High-k Dielectrics J. Dąbrowski, S. Miyazaki, S. Inumiya, G. Kozłowski, G. Lippert, G. Łupina, Y. Nara, H.J. Müssig, A. Ohta and Y. Pei Materials and Processes for Non-Volatile Memories R. Bez, E. Camerlenghi and A. Pirovano Nanoelectronics and Nanospintronics: Fundamentals and Materials Perspective K.L. Wang and I.V. Ovchinnikov Organic Materials for Large Area Electronics R. Friend Photovoltaic Power Generation: The Impact of Nano-Materials A.R. Peaker and V.P. Markevich

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Materials Science Forum Vol. 608 (2009) pp 1-16 © (2009) Trans Tech Publications, Switzerland doi:10.4028/www.scientific.net/MSF.608.1

Today’s mainstream microelectronics - a result of technological, market and human enterprise. Hermann G Grimmeiss1,a and Erich Kasper2,b 1

University of Lund, Solid State Physics, Box 118, S-221 00 Lund, Sweden 2 University of Stuttgart, Institut für Halbleitertechnik, Stuttgart, Germany a

[email protected], [email protected]

Keywords: semiconductors, microelectronics, integrated circuits, hetero-junction, bipolar transistor, history, Moore’s law

Abstract: Microelectronics is a central area within information technology, which is still one of the most important global technologies. It will be shown that the development of integrated circuits is based on a long and fascinating history, which is unique in modern time. Yet, the fantastic growth in semiconductor electronics is due to a unique combination of basic conceptional advances, the perfection of new materials and the development of new device principles. A brief survey of the development of microelectronics is given by not only focusing on the history of microelectronics but also taking into account materials and market aspects. Since microelectronics is an extremely complex area, a few criteria and reference points for integrated circuits are given. Thereafter, some examples are presented indicating the rapidly changing state-of-the-art. It will be shown that the development of material science within the area of microelectronics is not always driven by scientific curiosity but often by arbitrary and not always obvious preferences. After a short discussion of the performance advantages and disadvantages of germanium, silicon and III-V compound semiconductors, the SiGe heterojunction bipolar transistor is taken as an example for demonstrating a few important differences in the performance of all-silicon devices with regard to silicon-based heterojunction devices in general. In conclusion, the impact of human enterprise and research policy on the development of microelectronics is briefly discussed.

Introduction Information technology is still one of the most important global technologies. Ever since the invention of the transistor, we have witnessed a fantastic growth in semiconductor electronics, an important area within information technology. It is fair to say that this impressive progress has only been possible due to a unique combination of basic conceptional advances, the perfection of new materials and the development of new device principles. Very often, applications of microelectronics are primarily connected with computers, internet, e-mail, or mobile telephones. However, microelectronics is used for many more applications to improve the quality of life for everyone. Typical examples of fields where microelectronics plays an important role are automobiles, fuel cells, households, medicine and optical communication to name a few of them. Microelectronics is an extremely complex area and the result of several rather different fields such as

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materials science process technology circuit design and system design.

Since circuit design and system design are not the subject of this book, the following chapters will only deal with the areas materials science and process technology. For a better understanding of the history of mainstream microelectronics, it might be worthwhile to summarise a few reference points for integrated circuits (ICs) since all new device and technology ideas are challenged by these criteria. A dominant criterion in this connection is the cost aspect. As will be shown later, one of the miracles behind the history of microelectronics is the fast decrease in production costs of all electronic devices right from the beginning. This has been achieved by increasing the density of electronic devices in ICs and the wafer size. The most important contribution to low costs, however, results from parallel processing. Apart from the material costs, the costs for the production of one electronic device or one billion electronic devices are in principle more or less the same since they are all manufactured in parallel. Another reference point for integrated circuits is speed. This has been achieved by improving the speed of active devices such as transistors and by high output currents for interconnects. However, in order to use the advantage of high speed devices the speed of the interconnects has to be increased in parallel. A further criterion for integrated circuits is the power needed to drive the circuit, which should be as small as possible. This is attained by keeping the active power and the standby power low and has been accomplished, among other things, by decreasing the feature size and developing new device structures. Finally, there are additional reference points, which are of great importance for integrated circuits: Room temperature operation, high reliability and yield. In the history of microelectronics there are many examples of outstanding concepts for new devices and technologies, which never reached the market due to the fact that these applications did not work at room temperature. Other devices were applicable at room temperature but their reliability was not high enough to satisfy the customer. It will be shown later that quite a number of convincing concepts never survived because of too low yields and absent reliability. The history of integrated circuits is characterised by the rapidly changing state-of-the-art, which is unique compared with other branches. 15 years ago, the base of a transistor was about 2 0.5 m. This implied that 1 cm of a chip contained 40 million transistors. For storing one bit, only 2 devices were needed. Considering that about 20 000 bits are needed to store 1 page of 2 text, about 1000 pages could be stored on one chip of 1 cm . 10 years later, the base of a transistor was 5 – 8 times smaller. In the mean time, the size of a chip has been doubled and contained more than 2 000 million transistors. This means that about 50 000 pages of text could be stored on one chip corresponding to 100 books of about 500 pages. However, there is more to come. People are not only interested in storing information but sharing it with others. This is done by optical fibre cables. 15 years ago, each cable contained 24 fibres implying that 15 billions

Materials Science Forum Vol. 608 bits/s could be transmitted through one single cable. Or with other words, 700 000 pages of text could be transmitted per second to any place in the world. 10 years later, the numbers of fibres in a cable was increased to 72. Through each fibre 160 different signals (colours) could be conveyed with still higher speed. Hence, 100 000 billions of bits/s could be sent out through one cable corresponding to 5 billions of pages per second. This amount of information is equivalent to about 1 billion telephone calls or 1 million TV programs. However, there is more to come.

The Beginning of Semiconductor Electronics Looking back it is fair to say that the development of integrated circuits is based on a long and fascinating history. This is surprising considering that at its most basic level, the integrated circuit simply manipulates the characteristics of electricity. It was William Gilbert (1544 -1603), known for his investigations of magnetism and electricity, who first used the word “electricity” about 400 years ago. More than 200 years later, James Clerk Maxwell, the “father of modern physics”, discovered the theory of electromagnetism. His equations, which were proven correct by Heinrich Hertz, are at the root of computational electromagnetism. Maxwell put forth the idea that energies reside in fields as well as in bodies. His work has impacted and spawned the fields such as communication and engineering. In the 1880’s, Thomas Edison built one of the first practical electrical generators. Later, Nobel Laureate Guglielmo Marconi proved that wireless communication was viable. Some of his major accomplishments include receiving the world’s first patent for a wireless-telegraphy system in 1896. He transmitted the first wireless signals across the Atlantic between Poldhu, Cornwall, and St. John’s, Newfoundland in December of 1901. He also patented a magnetic detector, which long served as a standard wireless receiver. However, it was the invention of the vacuum tube, which launched the electronic industry and allowed broadcast radio to reach the masses in the 1920’s. In 1939, the first tube was used as a switch in calculating machines. Yet, it soon turned out that vacuum tubes were not the ideal solution for this application due to its size and energy consumption. A naval destroyer built in 1937 had about 60 vacuum tubes on board for the communication system. The post-war destroyers of 1952, however, had already more than 3 000 vacuum tubes on board due to other applications. Even more dramatic was the development with respect to computers. The ENIAC computer of 1946, the world’s fastest computer for years, contained more than 17000 vacuum tubes, weighed 60 000 pounds, und consumed 174 kW of electricity. Vacuum tubes clearly could not support any significant evolution of computers because the cost, bulk and reliability of vacuum tubes would limit commercial and military electronic systems. By the mid-1950’s, the shortcomings of vacuum tubes were visible to many in the industry, and many researchers began seeking a solution. The breakthrough came in 1948, when Bell Labs invented the transistor. The original device, created by William Shockley, John Bardeen and Walter-H. Brattain, consisted of a 1 mm germanium (and not silicon) wafer. Onto one surface of the wafer two point electrode contacts were made, side by side and close together, which were called emitter and collector and known as point contact transistor (Fig.1). Passing current pulses through the collector contact in the reverse direction then forms the assembly. Exactly what happened during forming was still the subject of speculation in 1959. Already in 1951, Bell Labs held their first transistor symposium and began licensing transistor technology

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• •

In the beginning of the 60s, the quality of conventional resistors and capacitors was much higher than the ones made with semiconductors. People were afraid, if semiconductor technology succeeded, all of the world’s circuit designers would be out of work.

Not earlier than by the late 60s (20 years after the invention of the transistor), most engineers had accepted the fact that integrated circuits were here to stay.

The Beginning of the Silicon Technology As already mentioned, the first transistors were fashioned not from silicon but from germanium. There were important reasons for this priority, among them the much greater ease of purifying germanium and the higher mobility of electrons and holes within it. But due to the smaller energy bandgap, the performance of germanium transistors degrades rapidly with temperature. Hence, one of the disadvantages of germanium is the low operating temperature of germanium devices and another one is the low breakdown voltage, which plays an important role in power amplification. Recognizing these problems, people were looking for alternative materials already in the beginning of the 50s. One of the choices was silicon. However, due to its higher melting point (1420 C), silicon is more difficult to refine. Furthermore, new crystal growing techniques had to be developed in order to match not only the crystal size and quality but also the purity. Yet in spite of all these difficulties, silicon had a decisive advantage compared with germanium, it easily forms an oxide. As will be shown later, this property is still one of the major reasons why silicon has survived until now as the main market leader. In 1955, Carl J. Frosch, Link Derick et al at Bell Labs used the silicon dioxide for a new technology and invented the combined process of oxide masking and photolithography for silicon. The new process together with the larger bandgap and higher melting temperature ended the role of germanium as a major player since no material was found that would provide diffusion masking for germanium. Though the silicon technology was born and eventually became the major player in microelectronics, germanium devices still dominated the market for many years. Time delays of this kind occur fairly often in the development of microelectronics. Since a better understanding of the new technology is needed, they are due to the time delay in research, which in certain cases can be quite large. Once the new inside is obtained, it has to be developed into new production facilities, which again is often rather time consuming. Finally, as long as the new technology is not providing clear advantages, the market is hesitant and the old technology will still dominate the market. The basis of silicon technology is still silicon dioxide since both active and passive devices can be fabricated very efficiently. Together with the photo-resist technique, silicon dioxide and related materials allow fabrication processes such as parallel processing and planar techniques, which are still unbeaten as one of the main criteria.

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Objectives of microelectronics Microelectronics means the multifunctional integration of electronic devices. Since the beginning, the objectives have been to further increase the

• • • •

Packing density (devices/area) Complexity (functions/chip) Multi-functionality (variety of devices) and Signal processing rate (information/time)

In 1965, Electronics magazine asked the head of research at Fairchild Semiconductor Corp. Gordon E. Moore to sketch out the next decade of the fledgling chip industry. He decided to plot the growth in the number of transistors on chips, starting with 4 transistors in 1961 to more than 200 on a chip in 1965. What he found was amazing: the number of components the industry would be able to place on a computer chip would double every year. Moore boldly predicted in print that it would do so for the next 10 years - the first appearance of what would come to be called Moore's Law. In 1975, he updated his prediction to once every two years. The results eventually made electronics the world's biggest industry and Moore's next start-up, Intel Corporation, the world's richest chipmaker. '’It's kind of funny that Moore's Law is what I'm best known for,'' says Moore. ''It was just a relatively simple observation.'' Starting in the 70s, the US Semiconductor Industry Association (SIA) was producing the National Technology Roadmap for Semiconductors (NTRS), which in 1999 became the International Technology Roadmap for Semiconductors (ITRS). The purpose of the ITRS is to provide a reference document of requirements, potential solutions, and their timing for the semiconductor industry. The most frequently cited trend is in integration level, which is usually expressed as Moore’s law. Roadmaps like the ITRS are very popular but predicting the future is difficult if not sometimes impossible. An interesting example is given by Moore himself. In 1997, pressed to cite more possibilities, Moore demurs: ''In the late 1970s, I looked around the house for all the potential applications for microprocessors I could find. I came up with 85 potential new uses, like light switches.” He then continued: “A couple of years later, I took another look, and more than half of the applications then on the market were things I hadn't even envisioned. So my batting average at making predictions is not especially good.'' Considering that he came up with a real hit 32 years ago, apologies are certainly not necessary. Fig.6 shows the IC Technology Roadmap of 1975, which predicted that the NMOS-technology will be taken over by the CMOS-technology in 1978 and the silicon technology will end in 1984 and replaced by the III-V semiconductor technology. Furthermore, it was also envisaged that optical lithography would end in 1983 and followed by E-beam/X-ray lithography. These are typical examples how roadmaps sometimes can be misleading. As will be seen in the following chapters, until now the market share of the III-V semiconductor technology, with regard to integrated circuits, never exceeded the 5% barrier. It will also be shown that optical lithography is still the dominating technology. It should, however, be observed that the 1975 IC Technology Roadmap already pointed out that the silicon-on-insulator (SOI) technology will play an important role with regard to future IC technologies, a subject, which will be discussed further down.

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Fig.6 1975 IC Technology Roadmap [4]

Impact of Material Science The continuous reduction of the structure size within silicon technology has been extremely successful in improving the performance of microelectronics and is in large measure responsible for the breakthrough of information technology. Yet from a circuit designer’s perspective, silicon is hardly the perfect material with respect to speed. At the end of the 60s, there was a market’s demand to increase the cut-off frequency limit for applications in computers and high speed communication (wireless fibre communication etc.) This was one of the reasons why people started looking for alternative materials. In contrast to silicon, many III–V semiconductor compounds are known to exhibit high carrier mobilities and saturation velocities. Almost endless variations on their chemical composition and, hence, energy bandgap are possible. Bandgap engineering, in fact, is a powerful tool for growing different kinds of heterostructures and, hence, creating faster transistors. Already in the 1960’s, new and advanced methods of epitaxial crystal growth of III-V semiconductors had led to systematic studies of mono-crystalline hetero-junctions in semiconductors. Together with the much higher carrier mobility and saturation velocities, these hetero-structures of compound semiconductors allowed much higher device speeds. Due to the direct band gap, efficient optodevices (lasers, detectors, etc) were and still are developed with these semiconductors. Together with the high packing density and high integration level, a very high multi-functionality was achieved. In the 70’s and 80’s, it was therefore very difficult in many European countries to obtain research funds for studying silicon because many authorities were convinced that “GaAs has been, is and will be the material of the future”. Due to their performance, compound III–V semiconductors should therefore without any doubt provide the best possibilities for accomplishing the objectives of mainstream microelectronics.

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However, in spite of these performance advantages, why are less than 5% of all manufactured ICs fabricated with III-V compound semiconductors? The answer is economics. Market shares are in most cases determined by the performance/cost ratio and ICs are simply much more difficult and expensive to fabricate from III–V compounds than from silicon. Cost estimates show that the cost/area increases by a factor of about 5 when going from silicon to GaAs and by a factor of about 10 when going from silicon wafers to other III-V compound semiconductor wafers. These figures are still more in favour of silicon considering that the 300-mm silicon wafer together with a 65-nm technology is already on the market and that further improvements can be expected within the next 15-20 years. World-wide investments in silicon technology is enormous and yields are high in the silicon world. However, there are also material related reasons why III-V compound semiconductors have difficulties in competing with mainstream IC applications, because these weaknesses are directly connected with economics. Like with germanium, high-quality oxides are scarce in the III–V world, impeding device integration, and high-purity, large-diameter crystals are difficult to grow. Furthermore, chip yields are much lower due to inherent crystal defects implying higher production costs, as mentioned earlier. Due to their materials performances, compound semiconductors should in principle offer the best solutions for mainstream applications but for economical reasons this was not sufficient to become the market leader. On the other hand, as already pointed out, silicon is not perfect either. As already mentioned, due to material properties, there is a cut-off frequency limit inherent to silicon technology, which is considerably lower than with III–V semiconductors and required by the market. Because of new applications in information technology, for which still faster circuits were needed, there was a market’s demand to overcome the cut-off frequency limit of the silicon technology since these applications will only generate a large market if low-cost systems can be offered. Though many mobilcom applications could be covered by all-silicon technologies, there were numerous other wireless applications such as wireless local area network (WLAN), hyperLAN and broadband satellite communication which were of interest but could not be realised with all-silicon technologies. In-home digital networks coupled to public networks are other examples. All these applications needed frequencies up to about 15 GHz already in the 1980´s. If fibre communication or some radar applications were included, circuit designers liked to have frequencies up to about 80 GHz available. These frequencies were difficult to obtain by mainstream all-silicon technologies at that time. The dominant question in the 80’s therefore was: How can the cut-off frequency limit of silicon devices be overcome without deteriorating the performance/cost ratio? The vision was realized by using the performance advantage of III–V compound semiconductors based on heterostructures. In this context, silicon-germanium alloys have been discussed since the mid-1950’s (see next chapter). Yet being aware of the fact that III–V compound semiconductors had shown their superior performance, the vision still remained to outperform silicon technology by using the performance advantage of III–V compounds, and to undersell the III–V technologies. One of the first and probably also one of the simplest bandgap-engineered silicon devices was the SiGe heterojunction bipolar transistor (HBT). The HBT may therefore serve as an example for demonstrating a few important differences in the performance of all-silicon devices with regard to silicon-based heterojunction devices in general. The npn HBT, for instance, differs from a silicon bipolar junction transistor (BJT) only with

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regard to the base, which in the HBT consists of a strained Si1-xGex epitaxial layer of either constant or varying composition (Fig. 7). The only constraint for a practical SiGe HBT design is that the integrated germanium content be low enough to guarantee film stability. Since the difference in the bandgap energy Eg is almost completely given by the discontinuity of the valence band, electrons have to overcome a much lower energy barrier in the HBT than in a BJT when being injected into the base.

Fig.7 Schematic diagram of a SiGe hetero-bipolar transistor (HBT) [5] This implies, somewhat simplified, that the (common-emitter) current gain  can be approximated by the expression



jn D n WE N E n i 2 (SiGe) D n WE N E      Z jp D p WB N B n i 2 (Si) D p WB N B

Z

E g (N C N V ) B exp( ) (N C N V ) E kT

where

฀

฀

Here, Dn,p is the diffusion constant of electrons and holes, respectively; NE,B is the emitter and base doping, respectively; and WE,B is the emitter and base layer thickness, respectively. The other symbols have their usual meaning. In most transistor designs, Dn /Dp is close to 1 and WE /WB between 3 and 5. To achieve a

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current gain of about 150 in a silicon BJT, the NE /NB ratio must be chosen between 30 and 50 since Z=1. Since the emitter doping can be increased above 1020 cm-3 only slightly, this restriction puts a limit on the base doping and, hence, on the base resistance RB. The situation is very different with the HBT. There, the current gain depends exponentially on the germanium content at the base-collector junction, implying that Z is about 100 for x = 0.2 and about 400 for x = 0.25. For many applications, current gain is less important than speed. Considering that the maximum oscillator frequency, at which power amplification is 1, can be approximated by

fT NB fmax  0.2  R BC BC WB2C BC

where ฀

fT 

1 2  EC



1 , 2 ( E   EB   B   BC   C )

a larger current gain can be traded against a higher fT and a lower base resistance by reducing

฀ the  base layer thickness and simultaneously increasing the base doping. Here CBC is the collector-base capacitance, and fT is the frequency at which the magnitude of the incremental short-circuit common-emitter current gain extrapolates to unity. The quantity fT increases with decreasing base layer thickness, because EC is the transit time of the carrier from the emitter to the collector. E, EB, B, BC and C are the carrier transit times in the emitter, from the emitter to the base, in the base, from the base to the collector and in the collector, respectively.

In 2007, the gate delay time of SiGe hetero-bipolar transistors was 3.0 ps, a new world record [6]. This implies that maximum oscillator frequencies of about 300 GHz have already been achieved. There are good reasons to assume that fmax values of 0.5 THz will be available in the near future implying that the competition of III-V compounds will become even more difficult, in contrast to the 1975 IC Technology Roadmap. The latest WWRF (Wireless World Research Forum) Vision predicts that by 2017 7 trillion wireless devices will serve 7 billion people. All devices will be reasonably priced to purchase and operate. Sensors and tags, e.g. in transport and weather systems, will provide ambient intelligence and context sensibility. Furthermore, all devices will be part of the (mobile) internet. Though this seems to be rather straight forward, it is nevertheless expected that the future development of the silicon based technology will be the result of further material inputs.

Impact of human forces The first generation of semiconductor pioneers was very broad in its ideas irrespective of the fact that the involved material problems often were solved first after several decades. It was William Shockley and Herbert Kroemer, who had the first visions concerning the concepts of

Materials Science Forum Vol. 608 hetero-junction and hetero-bipolar transistors, respectively. At that time, the HBT stood for a wide band gap emitter with Ge as substrate. In 1977, when germanium substrates were substituted by silicon, Peter Russer and Erich Kasper [7] patented the SiGe/Si double heterojunction bipolar transistor (DHBT) as it is fabricated now. However, the concept of the SiGe – HBT was verified much later, after the development of epitaxial technologies such as molecular beam epitaxy (MBE). It was Subu Iyer [8] from IBM, who 1985 reported at the International Si-MBE Symposium that the silicon related DHBT was realized by using a base of SiGe. Bernie Meyerson and his group at IBM spent much time to improve the technical performance and production of SiGe – HBTs by achieving and even surpassing the 100 GHz barrier [9]. These results removed all doubts about the superiority of the silicon heterostructure device concept. In the 80´s, a visionary CEO, Edzard Reuter, gave the German automotive company Daimler Benz (manufacturer of Mercedes cars) a new direction by establishing an advanced technology group including aerospace (MBB, Dornier) as well as military and electrotechnical companies (Telefunken, AEG). The research portfolio of this group included novel silicon technologies and devices. The head of this new department, Erich Kasper, gathered a number of excellent scientists, who, in competition with Bernie Meyersons group at IBM, pushed the HBT speed beyond 150 GHz [10, 11], which in principle implied that microwave systems could be realized with silicon based microelectronics. This increase in speed was technically important because it shifted the border line between silicon and competing semiconductors to higher frequencies, showing how important it is to have the right people at the right time at the right spot. When the visionary leader, Edzard Reuter, retired from his position as CEO of Daimler Benz, the company returned to its core business with technical success but failed with its international cooperation. Several other companies are now offering HBT–circuits for microwave and mm–wave applications. In the meantime, the BiCMOS-compatible production of these circuits was improved and enhanced by carbon co-doping of the base (SiGe:C), which resulted in a reduced boron outdiffusion from the base during the CMOS thermal budget. In 1991, Hermann Grimmeiss refounded the non-profit research institute IHP in Frankfurt (Oder), Germany, that above all worked at the technical implementation of carbon doping into device processing through a rigorous analysis of the underlying physical processes, especially with regard to junction space charge technologies. Since a couple of years, the institute under the new leadership of CEO Wolfgang Mehr keeps the world record of gate delays within the SiGe:C HBT-technology [6]. Germanium substrates initially used for discrete semiconductor devices were replaced by silicon when the integrated circuits technology started. As already mentioned, the general opinion at that time was that materials for substrates will continuously change to more advanced and developed materials such as GaAs or other III/V alloys. Though these materials got strategic importance for specific applications, they nevertheless failed to compete with silicon in volume production because of economical reasons. Instead, the contender of bulk silicon substrates turned out to become a more complex silicon-based structure, namely silicon on insulator (SOI). What is not addressed by the acronym SOI, is the bulk silicon below the insulator in the technical solution, which presently is favoured. Early attempts to realize such structures included hetero-epitaxial growth of silicon on sapphire, ion implantation of oxygen (SIMOX), and lateral overgrowth from seeds in oxide windows. The route, which right now is chosen, employs wafer bonding by using one wafer with an oxide layer and another one, whose surface is prepared by smart cut processes [12]. Smart cut (Fig.8) separates the main body of the wafer from its surface region by a He pre-implant before the bonding, annealing and breaking away

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Materials Science Forum Vol. 608 end of the 1980’s, it was shown that bandgap-engineered silicon devices allow for much higher cut-off frequencies than the ones made with all-silicon by using the performance advantage of III-V compounds. Considering that 300 GHz Si/Ge HBTs are already fabricated and undersell the III-V technologies, it is not surprising that these technologies are considered as a big success. Although Moore’s law almost certainly will be valid for R&D and production for quite a while, it will nevertheless end some time. Until then R&D most probably will develop in three parallel directions: (1) conventional silicon-based planar CMOS, including new materials, (2) non-conventional new silicon-based 3d CMOS devices, and (3) new device concepts based on different materials and perceptions. More details will be given in one of the following chapters. Whatever new technologies and device concepts are developed, they all have to be compared with existing CMOS criteria like low cost, parallel processing, high density, high yield, room temperature operation, high speed, low power consumption, and reliability. It is therefore assumed that new device concepts will first be applied as additions to silicon-based CMOS, since compatibility to CMOS is very important. Industry is very conservative, and will only adopt new technologies if silicon-based CMOS applications are no longer competitive. Technology driven materials research, including atomic layer scaling and interfaces for new nano-applications, is therefore utmost important. However, these goals can only be reached efficiently if universities and research institutes improve their collaboration with the tool and semiconductor industry. Research institutes are often capable of performing prototyping and are therefore predestined for bridging the gap between universities and the private sector. Nanoscience is a very interesting and highly exciting research field, however, breakthroughs in applications will only occur if these new concepts are able to beat silicon-based technologies.

References [1]

J.N. Shive: The Properties, Physics and Design of Semiconductor Devices (Bell Laboratories Series, D. van Nostrand Company, Inc., Princeton, New Jersey 1959)

[2] R.A.Greiner: Semiconductor devices and applications (McGraw-Hill Book Company, Inc., New York 1961) [3] John P. McKelvey: Solid State and Semiconductor Physics (Harper International Edition, New York 1966) [4] Dr. Claeys: private communication [5] H. Rücker, B. Heinemann, D. Knoll, and K.E. Ehwald, in: SiGe:C Heterojunction Bipolar Transistors: From Materials Research to Chip Fabrication, Advances in Solid State Physics 42, edited by B. Kramer, Springer-Verlag, Berlin, Heidelberg (2002), p. 471-482 [6] H.Rücker, B. Heinemann, R. Barth, J. Bauer, K. Blum, D. Bolze, J. Drews, A. Fox, O. Fursenko, T. Grabolla, U. Haak, W. Höppner, D. Knoll, K. Köpke, B. Kuck, A. Mai, S. Marschmeyer, T. Morgenstern, H.H. Richter, P. Schley, D. Schmidt, K. Schulz, B. Tillack, G. Weidner, W. Winkler, D. Wolansky, H.-E. Wulf, Y. Yamamoto: Proc. IEDM (2007), p. 651

15

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[7] E. Kasper and P. Russer, Verfahren zur Herstellung Hochfrequenztransistoren, German Patent P 2719464 (1977)

von

bipolaren

[8] G. L. Patton, S.S. Iyer, S. L. Delage, S. Tiwari and J. M. Stork: IEEE EDL 4 (1988), p. 165 [9] E. F. Crabbé, B. S. Meyerson, J. M. Stork and D. L. Harame: IEDM 1993 Techn. Dig. (1993), p. 83 [10] E. Kasper, A. Gruhle and H. Kibbel: IEDM 1993 Tech. Dig (1993), p. 79 [11] A.Schüppen, U. Erben, A. Gruhle: IEDM 1995, Techn. Dig. (1995), p. 743 [12] C. Mazuré and G. K. Celler, in: Advanced Electronic Substrates for the Nanotechnology Era, Interface 15, no. 4, p. 33, ECS, Pennington (2006)

Materials Science Forum Vol. 608 (2009) pp 17-26 © (2009) Trans Tech Publications, Switzerland doi:10.4028/www.scientific.net/MSF.608.17


           


          

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 Requirements and applications for three different scenarios in material science of microelectronics are discussed. Dimension scaling continous at the same pace (More Moore) by changing to immersion lithography and later to extreme ultraviolet lithography. The functionality of system on chip solutions will be increased by heterogeneous technologies combined with a microelectronics core (More than Moore). Material science and physical understanding of new device principles started well in advance to judge difficulties and options. The strong links to economy are illustrated by a simple model of exponential growth.

   Microelectronics has changed the way of humans more than any other technology [1]. With such pervasive impact on the social structure it is important that the highest and safest methods of manufacturing are maintained. Despite the importance of the immediate return of investment, microelectronics needs to be seen for the broader impact it has on the social structure rather than just as commodity. It is for this reason that there needs to be stronger input at the research stages from government and industry. The
             states that the welfare of a knowledge and technology-based society in the 21st century will depend on its capabilities to engineer complex materials systems on the nanoscale (~ 10-9 m) [2] because control of materials means the control of technologies. Integrated circuits (IC) technology was driven the last 40 years by a steady shrinkage of the device dimensions by that enabling higher number of transistors on chip and higher performances per transistor. This trend is known as dimension scaling and scaling will continue the next decade or more. Long time, the choice of materials [3] concentrated on the very well behaved ones like semiconductor silicon (Si), dielectrics silicon oxide (SiO2) and metal aluminium (Al). Dimension scaling has now reached a stage where more sophisticated materials, interface systems (Fig.1), and architecture innovations are necessary to hold on the high speed of progress and to enable further increases in device performance. In analogy to dimension scaling this is called material scaling [4]. In the November 2007 issue of Euro Asia Semiconductors [1] David Ridsdale entitled his comment with “The death of silicon” wondering that in media reports on new sub 100 nm product range one could think that no silicon was used in the production of these logic devices. Of course such reports were outside of serious commentary and have more to do with a misreading of industry’s marketing machine than a reality that silicon is no longer the work horse of the industry.

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Figure 1. Materials Innovation [3]@ IEEE . The dopant materials (B, P, As, Sb) are not included in the list.

    The industry has known for some time that there is a need to change materials and manufacturing processes in order to keep the industry on the scaling path of Moore’s Law. A multitude of new high-performance materials with specially engineered electrical, mechanical, and chemical properties must be introduced to extend Moore’s Law and allow fabrication of scaled devices that operate at higher speed and/or lower power. Material scaling started with back end of line (BEOL) processing with copper interconnect / low-k (k dielectric constant) interdielectrics of the multilayer metallization system. Nearer to the semiconductor is the replacement of the silicon dioxide or silicon oxinitride (SiON) gate dielectrics by a high-k oxide like hafnium oxide which is announced [5] to get in production soon. Introducing hafnium as gate structure has an enormous impact on gate leakage. Big enough for the marketing machine to bring out Gordon Moore to declare that it was the biggest advance since the introduction of polysilicongate metal oxid silicon (MOS) transistor. This may be the case as the technical achievements of microengineering are more extraordinary when you consider the tight fiscal rein the industry is in. Even Gordon Moore has stated the natural end of his transistor doubling law. No-one knows when that will be or what new clever carrot will be dangled in front of engineers to keep them on a self achieving path in place of Moore’s supposition. There is a constant discussion of brick walls and a never ending supply of optimism that any challenge will be met. The background information on this crucial interface of MOS transistors is given to the reader in chapter 5. The semiconductor body itself is considered to be improved by silicon based heterostructures. The arrowhead of these heterostructures is given by silicon germanium (SiGe) / silicon interface junctions. The most important contribution of silicon based heterostructures is not only given by the improvements in device performance but more by the higher freedom in design of processes, circuits and systems. Let’s give two examples of this interplay between material base, applications and technology. In future driver assistance and vehicle safety systems a surveillance of the vehicle surrounding with mini radar platforms would be highly welcome (radar gives distance and speed information at the same time and it is only weakly weather dependant) but the required small size could only be fulfilled with high frequencies in the mm-wave regime around 80 GHz. Earlier expensive solutions are now replaced by integrated SiGe Bipolar and Complementary MOS transistor (BICMOS) circuits proving and inspiring systems and markets in

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a frequency range before meant inaccessible by silicon microelectronics. Another example concerns the role of strain in a processing sequence which was believed before as a high reliability risk. With heterostructures the concept of stable equilibrium strain was introduced and proven as reliable method to modify semiconductor properties. Since processing engineers gained faith in the reliability, nearly all manufacturing process utilized strained MOS channels – now prepared by a variety of methods. The scaling of materials opens new opportunities from process level up to the system and application level. Vice versa, the diversification on the different levels also influences the priority of material research. Luc Van den hove from the Leuven, Belgium, located research center IMEC, one of the leading microelectronics institutes, points out [6] the considerable change in research platforms for the 32 nm generation and he observes two types of – what he calls – “shift of the focus”. A first observation is the increasing importance of memory as a technology driver for the ITRS (International Technology Roadmap for Semiconductors) roadmap. Since many years, research has been performed on non-volatile memories (NVM), originally with strong focus for use as embedded technologies, because NVM are important features in many products. High-k materials are expected to be introduced firstly as an inter-poly dielectric at the 32-nm node. In view of the phenomenal scale-down of NAND (NOT-AND) flash device dimensions [7], stand-alone NVM have taken the spot of leading technology driver (Fig.2). In addition, focused research topics on DRAM (Dynamic Random Access Memory) added transistor design routes specifically for memories, including research on high-k dielectrics with low equivalent oxide thickness and metal gate options sustaining a memory-oriented process flow. Recently, this trend was expanded with next-generation MIMCAP (metal-insulator-metal capacitors) process technology for the 45-nm generation. In order to scale DRAM towards the 50nm node and beyond, MIMCAP dielectrics require materials with a higher dielectric constant compared to current industrial materials. By mid 2008, an effective oxide thickness of 0.5nm is targeted for the MIMCAP dielectric in the sub-50nm technology node, going down to 0.3nm in 2009 for the sub45nm node. Scaling the dielectric equivalent oxide thickness while attaining very low leakage currents is one of the major bottlenecks DRAM industry is facing. In a first phase, a baseline process for MIMCAP evaluation is set up based on TiN electrode and ZrO2, as the capacitor dielectric. This baseline process is used as a vehicle for screening new electrode materials such as W, Mo, TaC, Ru, etc. The stringent DRAM specifications as dictated by the ITRS will be used as selection criteria. They include leakage current lower than femto-Ampere per cell and a total physical MIM (metal-insulator-metal) thickness smaller than 20 nm.

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Figure 2: Minimum resolution versus time, for different types of  (DRAM, Logic, Flash) [7] A second observation is the emerging of ‘fablite’ and ‘fabless’ business models. Previously, almost every electronics manufacturer had his own state-of-the-art wafer-processing infrastructure. Both the most advanced technology and the design expertise were present. Recently, as a result of the strongly increasing cost of R&D and the fact that many of these companies are competing more on the product level rather than on the ‘capital-intensive’ technology level, many of them are moving towards an asset-light strategy and are relying increasingly on foundries for the advanced ICs. This new balance in activities also reshapes the interactions between the various industrial players. As part of this, foundries and equipment and material suppliers have a stronger need for cost-effective R&D support than ever before.The efforts do hold on the speed of miniaturization and by that the increase in transistors per chip is shortly named by the term  . The basic transistor in this approach is the complementary metal oxide silicon (CMOS) type of a field effect transistor (Fig. 3).

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Figure 3: Evolution of logic device design It is assumed that the planar CMOS structure prolongs its dominance by strained layer channels and substrate insulation with silicon on insulator (SOI) substrates, before a multiple gate control of the channel, probably in the form of a wrapped Si fin (FINFET), will be necessary (Fig. 4). The term FinFET was coined by University of California, Berkeley, researchers to describe a nonplanar, double-gate transistor built on an SOI substrate, based on the earlier DELTA (singlegate) transistor design. Germanium-on-insulator (GOI) substrates are well suited for the integration of optical and electronic functionalities, because of the optical properties of Ge and its good lattice match with GaAs. A critical role in the move on of   is seen in how fast lithography can follow the demands. One of the most interesting lectures in microelectronics history should be devoted to the incredible effectiveness of optical lithography techniques. The resolution R of an optical system is given (equ. 1) by the Rayleigh equation R=k1
λ/NA (λ wave length of light, NA numerical aperture, k1 factor)

(1)

The proportionality factor decreased to about 0.25 in this day lithography system. As the resolution improves with lower k1, the contrast is lost in the image [7]. Resolution enhancement technology (RET) techniques have evolved to bring back contrast even as device half pitch has continued to

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Figure 4: Configuration for a fin-based multi-gate transistor shrink. Commonly used RETs include off-axis illumination, the use of phase-shifting masks, and the addition of sub-resolution assist features to mask features. As the Rayleigh equation suggests, there are three ways to improve optical resolution: 1) increase NA, 2) decrease wavelength, or 3) decrease k1. Table 1 summarises the NA, wavelength, and k1 for optical lithography used in production of recent devices, as well as the main alternatives for continued device scaling to 32nm half pitch and beyond. The roadmap suggests three main technology options for extending lithography to 32nm half pitch: Table 1:Roadmap [7] for optical and EUV lithography. Given is the most likely solution for the numerical aperture (NA) and the factor k1 (see equ. 2). Wavelength (nm) Halfpitch (nm)

90

248

193

13.5

0.8/0.32

65

1.2/0.4

45

1.2/0.28

32

1.55/0.26

0.25/0.59

22

0.25/0.41

16

0.35/0.41

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● continue to increase NA at the 193nm wavelength using higher-index fluids and glass materials or ● use the existing NA and wavelengths, but extend the effective k1 beyond the diffraction limit by applying double patterning or ● scale the wavelength to 13.5nm, using EUV light sources and reflective reduction optics in a vacuum environment.

         Monolithic integration leads to larger circuits or to systems composed of several circuits with different functions. We then talk about system on chip (SOC) which are mainly fabricated as pure CMOS chips or as BICMOS (bipolar and CMOS). These SOC solutions are partly in competition with hybrid integrated chips on an carrier (multi chip module MCM) which is also termed system in package (SIP). In the starting phase MCMs are often faster to produce and more cost effective but with higher production volume in the past, monolithic integration was always favored. The microelectronics core of CMOS circuits may be joined by devices and structures which are different from that of the CMOS. A good example is micromechanics which uses silicon as a platform and silicon technologies for fabrication but adds also some specific processes to create fine mechanical plates and bars which stretch or bend under the influence of pressure, acceleration or electric fields. The possibilities will increase with even smaller structure dimensions -  . Free standing strained layer stacks can roll up [8] and create three dimensional structures on top of the planar surface of the IC. In general, the combination of a microelectronics core with functions requiring additional techniques is called   . In other words, by using existing wafer technology and production lines new innovative products will be created having not only memory and processor, but also power and radio frequency (RF) interfaces for wired and wireless communication, as well as sense and actuator functions. A list of heterogeneous technologies comprises high frequency functions (RF passives and waveguides and antennae), embedded MEMS (microelectromechanical systems), smart power, biochips, flexible electronics, photonics and micropower harnessing for autonomeous sensor networks. These technologies add new opportunities to the maturing microelectronics industry with its severe economic boundary conditions. In order to illustrate the industry status which stands with Moores law synonimeous for a long lasting exponential growth let us simplify the economic situation with a model of N equal companies covering the market with an annual value of M. Since more than 40 years – and this is unmatched by every other industry branch – the market volume is increasing exponentially. M(t) = M0 exp (aM * t)

(2)

Looking from the consumer side this market value is created by a large number nc of chips with a mean price Pc. From the producer side the costs K of manufacturing include investments, materials, salaries, financing, infrastructure and profit. In equilibrium the costs of all producers (including profit) have to meet the market value. M = nc * Pc =K * N

(3)

At least the main component of the costs – the price of the production site – is also growing exponentially. K(t) = K0 exp (aK * t)

(4)

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By comparing equ (2) – (4) one can easily see that in an exponentially growing economic system the number of succesful companies N(t) is also a function of time. N(t) = N0 exp [(aM - aK) * t] N0 = M0 / K0

(5)

The number of companies is increasing (decreasing) when the cost increase is lower (higher) than the market increase.    products increase the market value and can decrease the costs because of a longer lifecycle of production sites. The real economic systems are naturally more complicated than the simple model. The main differences concern the unequal sizes of the companies and the ongoing differentiation in the manufacturing process. The differentiation in production is highly evolved in mature industries such as the automotive industry. In contrast, generalists start in new emerging areas. The first companies in the semiconductor industry were growing single crystals, developed process sequences, built their own equipment, designed circuits and propagated applications. Soon, single crystal growth and substrate preparation were performed by several wafer suppliers. Later, equipment was built and combined to process lines by equipment manufacturers. The latest, economically very successful differentiation proceeded with the provision of a foundry service – technically now on the front line and cost effective by sharing the immense mask costs between several customers. The large scale implementation of this idea made Taiwan – the silicon island – to a main hub of chip manufacturing and nurtured fabless company models in other parts of the world. The exponential increase of the market on a long time scale is overlaid on a fine time scale by a considerable often as volatile seen noise. The waves are partly linked to the general economic situation but with much larger amplitude. The phenomenon resembles on a class of feedback loop processes in which a contineous flux switches to up and downs, e.g. waves in streams or stop and go in crowded traffic. In traffic situation with high flux densities the smooth curve gets unstable in favour of a stop and go function. As Reinhart Kuehne claimed [9], noise increases already below the critical flux density and it can be used as indicator of this critical point. To our knowledge a similar theory for exponential growing markets does not exist but we propose to collect not only the growth rate but also the noise - it could be a valuable measure of critical points in the growth curve. Microelectronics is influencing all aspects of modern life, which lead to a heavily interwoven relationship between economics, science and politics. Economics are driven by scientific progress and science needs the appreciation from both the customer and the politics. This is an excellent subject for research politics and small start-ups because the number of solutions and the product variety is high. The progress offered by scaling is enormous. Obstacles –red bricks- to overcome are that numerous that one speaks about red walls. The industry sight is optimistic to overcome these obstacles because up to now new scientific and engineering results helped to be on route. Nevertheless, material science and physical understanding of new devices and functional principles have to start well in advance to judge difficulties and options correlated with alternative paths. Suggestions based on alternative principles of microelectronics are termed   A rich and highly sophisticated toolbox of technologies was developed in the course of   and   . We can assume that elements of this toolbox will also play on essential role in   but unrestricted to be mentally focussed on one transistor function and one transistor type. There are many fantastic ideas which often can be classified into three large groups.

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(i) Usage of novel principles to realize device or circuit functions (e.g. quantum computation, cellular automata architecture, spintronics). Kang Wang will focus in his chapter on the potential of using other properties than electric charge as central medium of device characteristics. (ii) Exploitation of the tremendeous potential of group IV element chemistry. At the moment there are not very strong links between carbon based lifescience and organic chemistry on one side and silicon and silicon alloy based semicondructors on the other side although both, carbon and silicon, are similar in their on four outer electrons based chemistry. Our increasing knowledge and preparation ability of carbon monolayer sheets (graphene), of the roll up of sheets into tubes (carbon nanotubes) and of semiconducting polymers and related organic structures allow completely new directions, see R. Friends article in this book. (iii) Further reduction of dimensions in the nanometer regime will allow to exploit quantum size effects [10] and force scientists to rethink on nanostructuring. Quantum effects (gate oxide tunneling) already coerced CMOS technology to reshape the gate stack, but in future new opportunities given by quantum effects will be in the focus (yet in Si, they will take over only below 10 nm) (e. g. effective band gap increase, visible light from silicon nanocrystals, intraband transitions from multiquantum wells and superlattices, midinfrared and terahertz emissions, ultrafast tunneling with low voltage swing). The efforts to follow the deterministic route for sub 32 nm structuring will be enormeous (nano imprint, extrem ultraviolet (EUV) lithography). As already mentioned, we see a clear correlation between the economical efforts and the challenges for material science. Nanostructures may be grown in a selforganized or selfassembled manner like the Stranski - Krastanov mechanism. Lattice mismatched material couples as Ge on Si grow flat only up to about half a nanometer before they form small islands. The equilibrium force behind Stranski - Krastanov growth is the relaxation of strain energy in freestanding islands. About 109 to 1011 islands/cm² are created within one minute of epitaxy depending on the growth conditions. Meanwhile the efforts are directed toward positioning of the islands on prepatterned substrates and toward narrowing the size distribution of islands [11]. On the forefront of manufacturing is again the BEOL metallization scheme. Copper lines with selfassembled airholes are going to be part of novel metal/low k interconnect systems. In the following chapters we have asked respected authors to give a very personal view on their research areas in micro- and/or nanoelectronics. Despite the unavoidable incomplete selection, we hope to be able to convince the reader of the important role of material science plays in improving existing approaches, in finding add on solutions and in preparing and judging alternatives.  [1]

D. Ridsdale, The death of silicon, Euro Asia Semiconductor, p. 5, Nov. 2007, Angel Business Communications Ltd, Watford (UK), (2007)

[2]


            , Manfred Rühle, Helmut Dosch, Eric J. Mittemeijer, Marcel H. van de Voorde, Max-Planck Institute for Metals Science, Stuttgart (ISBN 3-00-008806-7).

[3]

T.C. Chang, Where CMOS is going: Trendy hype vs. real technology, IEEE SSCS Newsletter, p.5, Sept.2006, IEEE, Piscataway (USA), (2006)

[4]

H. Grimmeiss, pers. communication

[5]

M. Bohr, R. S. Chau, T. Ghani and K. Mistry, The High –k Solution, IEEE Spectrum (INT), Okt. 2007, p. 23, IEEE (2007)

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[6]

Luc Van den hove, Adapting to latest trends in semiconduct industry, IMEC Newsletter 50,5 (Oct. 2007)

[7]

N. Harned and F. van de Mast, Technology options for lithography at 32nm, EuroAsia Semiconductor, p. 23, Oct.2007, Angel Business Comm., Watford (UK), (2007)

[8]

C. Deneke, Fabrication of Novel Radial Crystals and Superlattices, ISCS 2007, Abstract Booklet p. 271, www.iscs2007.org, (2007)

[9]

R. Kuehne, Traffic flow on extra urban roads: driving as an example for nonlinear dynamics [Verkehrsablauf auf Fernstraßen: Autofahren als Beispiel für nichtlineare Dynamik]. In: Physikalische Blätter, Vol. 47, No. 3, 1991. p. 201 (1991)

[10]

E. Kasper and D. Paul, Silicon Quantum Integrated Circuits, Springer Verlag, Berlin, 2005

[11]

NANOSIL, Network of Excellence, Seventh Framework Programme, www.nanosil-noe.eu/nanosil.html

Materials Science Forum Vol. 608 (2009) pp 27-53 © (2009) Trans Tech Publications, Switzerland doi:10.4028/www.scientific.net/MSF.608.27


            
           !    "   !##   !# ##  


 Heterostructure device concepts promise several advantages in micro- and optoelectronics. From the material point of view, the main obstacle to be overcome is the large lattice mismatch of silicon based heterostructures. One of the best of them, silicon germanium (SiGe) is lattice mismatched to silicon by up to 4% depending on its Ge content. Basic investigations on strained layer growth, interface properties, and deviation from equilibrium are done with SiGe / Si heterostructures. Early results are discussed in context with our recent understanding. The application focus of this review is devoted to micro- and optoelectronic devices which could be fabricated after solving or understanding the basic interface problems. This includes devices already in production, and those in emerging fields for inclusion in the next generation of integrated circuits, as well as a selection of future device concepts with high merits to be proven in experiment.

   The semiconductor body itself is considered to be improved by silicon based heterostructures. The arrowhead of these heterostructures is given by silicon germanium (SiGe) / silicon interface junctions. The main advantages of heterostructures are due to tailoring of material properties, to adjustment of strain, and to interface functions not available in bulk material. Consider a single heterojunction with a large bandgap material A on one side and a smaller- band gap material B on the other side. The energy required for crossing the interface is different for electrons and holes, such acting like a filter for carriers inside the semiconductor body. A p/n – junction in bulk material may also be used as energy barrier but always with the same energy amount for both carrier types. The principle of a heterobipolartransistor consists in avoiding back injection of holes by a relevant heterojunction filter. Two heterobarriers A/B/A may be used to localize carriers, and by doing that with appropriate dimensions (typical below 15 nm), a quantization of energy levels is obtained. With several heterobarriers A/B/A/B… spaced within a small distance (a few nanometers) a superlattice is formed with interacting quantum wells penetrated by the carriers through tunnelling. Such a superlattice could be considered as man - made semiconductor because the electronic band structure depends not only on the parent materials but also on the artificial lattice periodicity. Within the historical development of microelectronics the community had to learn that serious technical obstacles had to be overcome in order to benefit from the heterostructure advantages. The most serious ones of these obstacles were chemical differences and lattice mismatch. A model system for lattice matched heterosystems was found in the III-V material realm with GaAs/GaAlAs nearly perfectly fitting together. But joining III-V semiconductors with silicon (Si) turned out to be difficult because of the chemistry defining each of the materials as dopants for the other group. The main attention was therefore focussed on the group IV elements and compounds. In the following table the cubic (diamond or zinc blende lattice cell) group IV compounds are summarized.

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 : Group IV elements and compounds carbon (diamond), silicon carbide (SiC), silicon (Si), germanium (Ge) and tin (Sn). Given are their atomic number (Z), atomic weight (M), density ( ρ ) lattice constant ao, and band gap Eg (eV) at 0 K Compound Z M ρ (kg/m3) ao (pm) Eg (eV)

Diamond (C) 6 12 2 620 356.7 5.48

SiC 14; 6 28; 12 3 200 435.9 2.6

Si 14 28.1 2 330 543.1 1.17

Ge 32 72.6 5 320 565.8 0.74

Sn 50 118.7 7 300 648.9 0.0

The differences in lattice constants are very large with the exception of the completely miscible alloy SiGe. In equilibrium only small amounts of carbon in Si and of tin in Ge are soluble. With the advent of low-temperature growth techniques like molecular beam epitaxy (MBE) or advanced chemical vapour deposition (CVD) methods the formation of non- equilibrium compounds such as SiGe:C and SiGe:Sn seemed to be possible. Recently the incorporation of Sn in the Ge lattice attracted considerable attention [1, 2] because already with 10 % Sn a direct (group IV) semiconductor material is predicted and on top of Ge:Sn tensile strained Ge is expected to exhibit spectacular carrier transport properties. In the following part the impact of lattice mismatch and strain on nanometer layers and their electronic structure is evaluated. Surface morphology and misfit dislocation networks play an important role in strain relief processes. The basics of dislocations were introduced in metallurgy where plastic deformation was explained as atomic phenomenon by dislocation movement. For the reader not so familiar with dislocation concepts they are listed in a glossarium. The implication of silicon based heterostructures on devices and circuits is ordered within three categories: where the advantages are already proven, where progress is so fast that emerging applications can be predicted with high probability, and that category where concepts are introduced which could promise great advances.    
         Silicon and germanium are both from the group IV of the periodic table of elements and therefore similar in many respects. The main differences are given by the lattice mismatch (about 4.2 % between Si and Ge), the surface energy, the oxidation behaviour and the processing temperatures (the melting point of Ge (≈ 1180 K) is about a third lower than that of Si (≈ 1700 K)). The SiGe/Si material system is now acknowledged as a model for strained-layer configurations because the chemical similarity of the partner materials does not mask the pure strain influence. Systematic investigations of this heterostructure couple started in the 1970`s. It might therefore be interesting to compare the not easily available early data [3-6] with our recent sophisticated understanding. With molecular beam epitaxy (MBE) SiGe layers and SiGe/Si superlattices have been grown at 750° C. At these intermediate temperatures the growth mode switched from 2D to a StranskiKrastanov one when the lattice mismatch was larger than 0.8 %. Fig. 1 shows the electron micrograph of SiGe islands the appearance of which restricted the Ge content to below 20 % for planar technology. Nowadays the island growth is either suppressed by lower temperatures or utilized for quantum dot self organisation phenomena. Above a critical thickness the interface changes from a pseudomorphic one (same in-plane lattice spacing of substrate and compressed SiGe) to a strain-relaxed one with misfit dislocations at the interface. Fig. 2 shows a freshly appearing orthogonal misfit dislocation network. At the crossings of the network the dislocations interact because of forces between them depending on the Burgers vector directions. The broad background pattern is caused by slight surface and alloy concentration modulations, a phenomenon

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preceding the island formation. The dislocation spacing p decreases with increasing thickness (Fig. 3) up to full strain relaxation which is obtained at about ten times the critical thickness. The strain relaxation was independently measured by X-ray diffraction. A comparison with equilibrium theories (e. g. v. d. Merwe or, Matthews-Blakeslee [7]) proved higher critical thicknesses and lower strain relaxations as expected. Relaxation of the brittle materials silicon or SiGe is kinetically limited by high dislocation nucleation and movement barriers. The concept of metastable strained layers pushed the SiGe device work in the 1980’s when the decrease of growth temperature [8] to 550°C and below enlarged the metastable regime considerably.

Fig. 1 Island growth of a lattice-mismatched SiGe on Si. Growth temperature 750°C. [4]

Fig. 2 Misfit dislocation network at the interface between a SiGe / Si superlattice and the Si substrate [4]

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Fig. 3 Dislocation spacing vs layer thickness for different SiGe alloys. [6]       The lattice mismatch causes either strain or results in generation of misfit dislocations at the interface. The thickness t at which strain is partly relaxed by the first misfit dislocations is called critical thickness tc. Its value is well defined only at thermal equilibrium whereas at low growth temperatures (e. g. 550°C) the nucleation and glide of dislocations is kinetically impeded, resulting in a rather large metastable region. By lowering the growth temperature below 550°C the critical thickness may be further increased, a region which is called ultrametastable [9]. The lattice constant of SiGe is slightly larger than that of Si. For a rough estimate the lattice mismatch f of an alloy is linearly interpolated (Vegard’s law) between the two parent materials: f =

a f − as

(1) = 0.042x

as

where af, as are the lattice constants of film and substrate, respectively, and x is the Ge molar content of the alloy.

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For more exact calculations a small parabolic deviation has to be considered. Recent investigations [9] on epitaxial material confirmed the old measurements on bulk crystals [10]. Taking into account the parabolic deviation, the lattice mismatch f of SiGe reads exactly as: f = 0.0417 x − 0.005 x(1 − x ) .

(2)

The structural and morphological stability of lattice-mismatched heterostructures is rather complex and covers both extremes, instability as well as perfect stability. For device processing a basic insight into the fundamental mechanisms of mismatch accommodation is necessary. Nature gives several answers to lattice mismatch. In the case of SiGe on Si the answers are: Strained films, strain relaxation by misfit dislocations, surface undulations, cracking. Cracking happens only during cooling down of thick Ge films and needs not to be considered for most devices. To simplify the picture, we first treat the equilibrium answer and then discuss the kinetic limitations imposed by the low growth temperatures and by processing of multilayer device structures. Up to the critical thickness tc the layers are strained, that means every atomic row in the substrate is continuing across the interface. This low-thickness regime is completely stable. The reason is given by the energy balance favouring strain in a small volume instead creating possible atomic defect structures like misfit dislocations. Misfit dislocations are line defects where atomic rows do not continue across the interface. Misfit dislocations are characterized by the line vector l and the Burgers vector b which defines the inhomogeneous strain field around the dislocation. The glide plane given by the vectors l and b allows easy movement of the dislocation. In diamond lattices the glide plane is the densely packed (111) plane. Dislocations cannot end inside the material, they are either closed or end at surfaces. Let us first consider a strained layer on top of the substrate. The in-plane strain value ε is directly linked to the mismatch f: a ε = − f s ≅ − f (strained layer) (3) af The minus sign in the equation stems from the given definitions of mismatch f and strain ε. A larger-layer film has a positive mismatch; the resulting compressive strain is referred to as negative. The near-unity correction factor as/af stems from the different reference lattices. For mismatch definition the substrate lattice is usually used as reference whereas for the film strain the film lattice is the reference. In what follows we take the correction factor as unity. The lattice expansion by one dislocation is given by the effective Burgers vector b' = b ⋅ cos λ  The Burgers vector is only effective for lattice accommodation with its edge type component in the interface plane. The angle λ is therefore defined as the one between the Burgers vector and the dislocation-line normal vector in the interface. The misfit dislocation density of a planar arrangement is defined by (1/p), the inverse of the dislocation spacing p (Note: the dislocation density within a volume – e.g. for threading dislocations – is given by the dislocation lengths/volume, which reads as dislocation per area, whereas the density of dislocations in a sheet is given by dislocation lengths/area, which reads as dislocation per length). For a completely relaxed film the misfit dislocation spacing p in the interface is given by (b’ takes the same sign as f). p = b’/f

(4)

For a partly relaxed film with both, dislocations and strain, the relation (5) holds f = - ε + b’/f

(5)

The relaxation degree r describes the relative amount of strain released by the introduction of misfit dislocations

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ε r = 1 +  f

 ε  = 1 − f 

(6)

The relaxation starts with a film of the critical thickness tc. With further increase of the layer thickness the strain decreases (Fig. 4). Full relaxation (r à, ε à ) is approached only at thicknesses much larger than the critical thickness.

Fig. 4 Plot of the compressive film strain vs film thickness t of Si0.92Ge0.08 layers on Si substrates. Above the critical film thickness ( ≈ 0.1µm ), the compressive strain is lowered by misfit dislocations. [6] The equilibrium critical thickness may be calculated rather easily from basic dislocation theory when – the reader should keep that in mind – the film is assumed to be flat. Differences in published numerical values are caused by differing assumptions about the dislocation core and the range of the inhomogeneous strain [11]. The as-calculated equilibrium thickness tcm (the index m refers to v. d. Merwe and Matthews-Blakeslee who pioneered this kind of equilibrium calculations) is rather small, e.g. 6 nm for a 25% SiGe alloy (f ≅ 0.01).

 t cm   −2  t   f = 5 ⋅ 78 ⋅ 10 ln cm   b   b 

(7)

The amount b of the Burgers vector is 0.384 nm in Si. The concept of the equilibrium critical thickness in the here given simple form is only meaningful for low lattice mismatches. At higher mismatch values the film strain is reduced by surface corrugations which cause a conversion from the flat v.d. Merwe growth mode to direct island growth (Volmer-Weber mode) or island growth on a thin wetting layer (Stranski-Krastanov mode) e.g. Ge on Si builds an only about 0.5 nm thick wetting layer on which nucleation of islands takes place. When the islands grow larger then misfit dislocations are generated additionally. The

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generation of at least the first dislocations is assumed to be from surface nucleation sites (NS) which are either small imperfections or surface steps (Fig. 5). Under the strain force dislocation half-loops move to the interface creating a straight misfit dislocation segment (M) and two threading dislocation arms (T) connecting the misfit dislocation with the surface. The misfit dislocation network when placed below the active device could be the ultimate near-device getter but the threading dislocations cause the electronic problems with this kind of material.

Fig. 5 Nucleation of dislocation half-loops (NS) and movement to the interface, creating segments M and T. The growth temperature of SiGe is strongly reduced (typically 450°C-750°C) compared to Si epitaxy. Surface atom migration and dislocation nucleation are kinetically suppressed. Flat, strained layers (pseudomorphic structure) are obtained under metastable growth conditions with much higher thicknesses and higher mismatch values than under equilibrium. In Fig. 6 the critical thicknesses under equilibrium (lower line) and that obtained at low growth temperatures (MBE, 550°C) are compared. The metastable critical thickness tcb (the index b refers to People-Bean [8] who discovered the large amount of metastability and published the fit relation in 1986 [7]) is roughly given by:

 t cb  2  t cb  1  f =  ln  b   b  200    .

(8)

With growth temperatures below 550°C even higher critical thicknesses can be obtained (ultrametastability). Strained layers just below the equilibrium critical thickness tcm are inherently stable. But also metastable layers turned out to be stable against heat treatments considerably higher than their growth temperature. The main reason is given by the silicon cap ontop of the SiGe structure which is either grown for functional purposes (emitter of the Heterobipolartransistor-) or to facilitate technological steps (oxidation, resist coverage). The equilibrium critical thickness is doubled by the cap but the kinetical limitation is even stronger as one can easily understand that from a surface nucleation site the dislocation half loops are not forced to move through the unstrained cap. Processing of strained SiGe up to 850°C is successfully demonstrated.

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Fig. 6 Critical thickness tc as function of the Ge content x. Stable region (equ. 7) and metastable region (equ. 8) are strained. Relaxed region with misfit dislocations. The direct observation of misfit dislocations is possible by X-ray topography and transmission electron microscopy (TEM). Above the critical thickness dislocations nucleate and move to the interface, leading to an increasing misfit dislocation density with increasing layer thickness (Fig.7). In these plane-view TEM micrographs the misfit dislocations are seen as mainly straight lines along both perpendicular directions of the [101] interface [6]. Long misfit dislocation segments and thus a low density of threading dislocations are typical for high growth temperatures and lowmismatched layers, as given here by 750° molecular beam epitaxy of a 0.3% mismatched SiGe on Si. The lowest energy would have a misfit dislocation network with equidistant by running straight dislocations. The distances experimentally observed are not equal for all dislocations, giving an indication that the equilibrium configuration despite the rather high temperature was not obtained. Instead, a mean dislocation spacing p is defined as measure of the global misfit-dislocation density (Fig.3). The values for the dislocation spacing vary with thickness from infinity below the critical thickness tc (in Fig. 3 different curves with critical thickness values of 40, 90, 220 nm are shown) to a saturation value at a thickness several times higher than the critical thickness. These findings are confirmed by X-ray diffraction (XRD) measurements of the residual strain ε (Fig. 4). The strain value ε decreases rather slowly with thickness. At ten times the critical thickness the strain of the form reduced to 25% of the pseudomorphic value. The strain follows in this example a power law

ε t  =  ε 0  t c 

−0.6

(9)

The slow relaxation r with increasing thickness defines a broad range of misfit and thickness, where both dislocations and strain have to be considered. We will later, when virtual substrates are introduced, discuss concepts which overcome the slow relaxation. The relaxation degree is

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influenced by equilibrium considerations and by kinetic limitations of misfit-dislocation nucleation, dislocation glide and dislocation interaction. In equilibrium, the driving force for new dislocations

Fig. 7 TEM micrographs of Si0.92Ge0.08 layers showing the decrease in dislocation distance p with increasing film thickness t: (a) t = 0.1 µm ; (b) t = 0.2 µm ; (c) t = 0.3 µm ; (d) t = 1 µm . The magnification and orientation in the graphs (b) (d) are the same as in (a). [6]

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is reduced by increasing relaxation because the strain energy drops with the square of the strain. Nucleation from the surface is a heterogeneous process initiated at surface defects. X-ray topography is a well suited method to investigate [12] heterogeneous nucleation at low densities (Fig.8 ) (the method gives a direct image of the dislocation strain field which is magnified afterwards). At the critical thickness dislocations spread out from defects whereas other perfect areas are further pseudomorphically strained. The interaction between crossing dislocation is shown in Fig.9 where the crossing dislocation is forced to move out of the interface plane. Defect etching [13] is a measure commonly used to investigate the dislocation distribution of low or moderate dislocation densities. The following example shows the crossing misfit dislocations (Fig.10) with threading dislocations at the ends of the misfit segments.

Fig. 8 X-ray topography of heterogeneous nucleation of misfit dislocations. [12]

Fig. 9 TEM micrograph of misfit dislocations in a SiGe supperlattice of thickness t=190 nm (5


periods of 380 A ). [3]

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Fig.10 Defect etching of threading dislocation marking the end of dislocation segments For processing with low thermal budget transient enhanced diffusion (TED) gains in importance, and that is nothing specific with heterostructures. But in heterostructures the role of carbon doping for suppression of boron diffusion [14] was emphasized. Interstitials react with substitutional carbon and avoid thereby enhanced interstitial driven boron diffusion; sharp, extreme high by doped regions are possible [15]. With increasing mismatch and with increasing layer thickness the layer-by-layer surface gets unstable against undulations. This can be understood from the Asaro-Tiller-Grinfeld (ATG) [16 ] instability theory which has been derived in the context of strained-layer epitaxy by Srolovitz (see [11] and references therein). For an isotropic surface energy γ the minimum wave length λc of a sinusoidal perturbation is given by λ = c

(10)

2 µπγ (1 − ν )σ

2

Surface energy anisotropy introduces energy barriers for island formation. Following a classification scheme of Berbezier [17] the surface shows four main morphological regimes: The regime I (Fig. 11) is characterized by a flat surface (layer by layer growth) which gradually roughens, regime II is associated with the formation of ripple – like islands with very low aspect ratios (Fig. 12), and regime III is related to the coexistence of “hut” and “dome” islands with typical

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aspect ratios of 0.1 and 0.3, respectively. In regime IV the larger islands of the bimodal distribution are dislocated whereas the smaller ones are coherent with the substrate. The facets of the hut islands

Fig.11 Kinetic phase diagramm (at TG ~ 550 0 C) representing the main morphological regimes as a function of (thickness) and (strain) on Si(001). [17]

Fig. 12 Ripples on the surface of a SiGe/Si superlattice [4]

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are (105) planes whereas the rounded shape of the domes is dominated by (113) and (111) planes. The driving force for islanding is the relief of strain energy in cap-shaped islands (Fig. 13) which overcomes the increase in surface energy by a nonplanar surface. This was in principle already shown by the early energy considerations of Jesser and Kuhlmann-Wilsdorf [18] and Stoop [19]. A low-mismatch approximation of their formula for the contact angle θ of islands delivers cos θ = 1 − f [1 + π − π ln(2πf )]

(11)

The following table 2 gives some numerical values of the contact angle θ calculated by equation (11).

 !: Contact angle θ as function of mismatch f after equ. (11). The elasticity properties of substrate and film are assumed to be equal in this approximation Mismatch f 0.01 0.02 0.03 0.04 29,34 38,10 44,06 48,63 Contact angle θ The island saves energy compared to layer-by-layer growth on the substrate below the island and by the free expansion of island layers above the substrate surface. The actual shape of the islands is additionally influenced by differences in surface energy, and by anisotropy of the surface energy, and reflects the kinetic evolution of islands from surface diffusion of adatoms. Qualitatively, a lower film surface energy favours Stranski-Krastanov growth mode where islands appear on top of a flat wetting layer (regime I in Berbezier’s classification scheme). A higher film surface energy (compared to that of the substrate) favours Volmer-Weber growth mode with direct island growth on the substrate. The appearance of (105), (113), and (111) facets is an indication of the surface energy anisotropy with local minima at these facets. Kinetic limitations are more prominent at low growth temperatures with increasing suppression of nonplanar surface morphologies. This can easily be understood with the help of the ATG instability which requires a minimum wavelength (equ. 10) for which a mass transport via surface diffusion is necessary, are typical for this layer growth mode.

Fig.13 Schematic representation of a “cap-shaped” island of h atomic layers on a substrate which is elastic to a depth of d layers. [19] With further growth thickness the island size is large enough for local misfit dislocations (regime IV), the islands start to coalesce (Fig. 14) and later a closed layer is formed when the stress as driving force for undulation is reduced by the misfit dislocation network. The dislocation network is much more complicated for coalesced islands than for layer-by-layer growth (v. d. Merwe growth

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Fig.14 Coalescence of SiGe islands ,Ge content x=0.25, mean thickness 909 nm, growth temperature 750 0 C .  : Carbon/Pt surface replica. The shadow is produced by inclined Pt evaproration. "  : TEM micrograph of the dislocation structure in large islands. [4] mode or 2D growth), see Fig. 15. Short segments of misfit dislocations defined by the original island and a high threading-dislocation density result from the continuation of originally at-island surfaces ending segments (remember: dislocations are not allowed to end in the interior of a crystal).

Fig.15 TEM micrograph of the closed SiGe layer. Same Ge content and growth temperature as in Fig. 14 but higher mean thickness (500 nm). [4]

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#     A first overview on the electronic properties of heterostructure is delivered by the band line-up (also called band ordering) between the two semiconductors with different bandgaps Eg (Si: Eg = 1.12 eV, Ge: Eg = 0.67 eV, 300 K). The SiGe / Si system is unique in that sense that depending on the strain situation the heterostructure type may be switched. For compressive by strained SiGe on unstrained Si (Fig. 16) the nearly flat conduction band (between type I and II) lets electrons easily cross the interface [20]. In tensile strained Si on unstrained SiGe (Fig. 16) the holes are collected on the SiGe side and the electrons on the large band gap Si side (type II interface). For a more detailed look also higher subbands and effective mass changes have to be considered. As an example the electron transport in a tensile strained Si channel [21-23] will be considered now. By the tensile biaxial strain the degeneracy of the electrons (all six cubic axis are energetically equal in the unstrained indirect semiconductor Si) is lifted with an energetic preference for the vertical direction (Fig. 17). It is easily recognized that for in-plane electron movement the low transverse effective mass is valid (in unstrained Si the resulting effective mass is a mixture of longitudinal and transverse masses). This leads to improved transport properties in the channel direction whereas tunnelling in the vertical direction (high longitudinal mass) is suppressed.



 

 
  

  
  

 





Fig.17 Energy ellipsoids (E = const) as function of wave vector k for tensile-strained Si. The symmetric ellipsoid for –k is not shown (me, mt effective masses in longitudinal and transversal directions).

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In general, strain in a cubic lattice cell reduces the symmetry and causes by that a splitting of the before degenerate states [24], e.g. of the heavy and light holes with zero momentum (k=0, Γ point of the Brillouin zone). This hole splitting by strain is common to direct (e.g. GaAs) and indirect semiconductors (e.g. Si and Ge). Only for indirect semiconductors a strain splitting of the lowest lying conduction band is observed which defines indirect semiconductors as good candidates for strain-induced manipulation of the electronic band ordering. In indirect semiconductors the conduction band is degenerated because the band edge is correlated to a finite momentum (X – direction (001) for Si, L– direction (111) for Ge) which is given 6 fold degenerate (6g) in X(Si) and 8 fold degenerate (8g) in L(Ge). In the following we consider a biaxial in-plane stress on a (001) surface of Si. The in-plane strain shifts the energy of the 4 in-plane directions (4g) (100, 010 and their opposite directions) and also that of the perpendicular (001) out-of-plane directions (2g). This is shown in Fig. 18 for a strain value of ε = 0.01 (roughly valid for a 25% Ge content SiGe alloy). The absolute average position of the band (2g and 4g) is shifted by a rather small amount (30meV) but the 6g band edge is splitted by 60meV and 120meV from this average position. The splitting is such that for tensile strain the 2g electrons (perpendicular momentum) and for compressive strain the 4g electrons (in-plane momentum) create the new conduction band edge. The energy positions for different strain values are summarized in Fig. 19 and 20. For compressive by strained SiGe on Si substrate the band edge of the conduction band is always given by the 4g electrons (part of the Xband). The L-band which dominats the Ge ( X ≥ 0.85 ) rich side in unstrained SiGe is always higher. The valence band edge follows the heavy-hole referred to as (V2) energy. For tensile strained Si on a SiGe virtual substrate (Ge content xs) the 2g electrons build the conduction band edge and the light holes (V1) build the valence band edge.

Fig.18 Conduction-band splitting by a biaxial strain of ε $0.01. Top: Tensile strain (strained Si on virtual substrate). Bottom: Compressive strain (pseudomomorphic SiGe on Si).[20]

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Fig.19 Band energies of compressive by strained SiGe (Ge content x). The valence bands are denoted V1, V2, V3 for the light hole, heavy hole, spin orbit split-off holes (soh), respectively. The conduction bands are denoted 2g, 4g for the X-electrons, perpendicular and in-plane, respectively and L for the (111) electrons. [20]

Fig.20 Band energies of tensile strained Si on a virtual substrate (Ge content xs). Notation as in figure 19 [20] (with permission ) .

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% & ' &  &(   ( &   The spread of commercially available circuits with SiGe / Si heterostructures started with the heterobipolartransistor (HBT) which gave tremendous speed advantages in bipolar and BiCMOS circuits (BiCMOS means bipolar circuit plus CMOS logic, CMOS means complementary metal oxide semiconductor transistor). The channels in CMOS transistors are elastically strained to improve hole and electron mobility. A global strain platform for the future will be described in the section on virtual substrates. The manufacturing generations from the 90 nm node to the 45 nm node mainly used process-induced strain for which heteroepitaxial source / drain regions are one of the solutions. In the next sections of this chapter these proven advantages, some emerging fields, and a selection of speculative concepts is given. ' &  &    & Integrated npn HBT transistors are now commercially available with around 200 GHz transit frequency ft [25, 26] and maximum oscillation frequency fmax, the research is targeting towards the Terahertz realm (half THz is demonstrated) with npn transistors and above 100 GHz for pnp transistors. This strained SiGe layer transistor proved the processing possibilities and reliability of SiGe / Si heterostructures. The energetic stability and the reliability of strained SiGe heterostructures paved the way to a widespread, but rather unspectacular application in CMOS circuits [27-29]. The strain in CMOS circuits is easily obtained (in competition with other strain generating methods) with SiGe source / drain (S/D) regions (compressive strain for p-channels) and recently also with Si:C S/D regions (tensile strain for n-channels). Within a few years the attitude has changed from suspicious neglection to eager adoption of strained heterostructures in Si based microelectronics. The output characteristic (Fig. 21) and the transconductance of strained- channel [24] MOSFETs are considerably improved (10 % - 50 %) in an otherwise unchanged transistor geometry.

Drain Current [µA/µm]

350 strained-Si Si control

300

V -V =1.2 V G

T

250 200 150 V -V =0.8 V G

100

T

50 V -V =0.4 V G

T

0 0

0.5

1

VDS [V]

1.5

Fig.21 Output characteristics of a tensile strained ( ε = 0.8%) n-channel MOSFET, compared with an unstrained one. [21]

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#        Which are the emerging areas that will benefit from this newly gained confidence in heterostructures performance and reliability? Optoelectronic integration, manipulation of elastic strain with strain platforms and Germanium-on-Insulator (GOI) structures will satisfy the demand for increasing performance and will fuel market prospects with system-on-chip (SOC) applications. Optoelectronic integration (Fig. 22) with microelectronics on Si is especially attractive on Siliconon-Insulator (SOI) substrates where low-loss optical waveguides, fast photodetectors and modulators and coupling structures for external lasers promise 100 Gb/s on chip systems for the near future. For an overview see [30-32]. The detector speeds obtained now are around 40 GHz [33] with broad spectral responsivities from around 0.6 µm to 1.6 µm wavelength. A specific spectral sensitivity may be obtained by a resonant-cavity enhanced photodiode (RCE PD) where a detecting heterostructure is embedded inside an interferometric cavity [34].

Fig.22 Scheme of an integrated optoelectronic waveguide circuit on an SOI substrate.

Strain platforms provide a surface layer on a silicon main body which offers a lattice constant different from silicon. Such substrates are known under different wordings: compliant substrate, pseudo-substrate, metamorphic, strain-relaxed buffer, virtual substrate. On top of those substrates strain-adjusted heterostructures may be grown by epitaxy. We prefer here the term virtual substrate, if the strained structure is grown on a relaxed buffer on a bulk or SOI substrate. The material technology of virtual substrates and of germanium layer on insulators is discussed later in this chapter. &   Speculative concepts appeared which have to prove their functionality yet. A selection includes spintronics, resonance phase operation, charge injection transistor (CHINT) logic. What are the strongest arguments to push them forward? Spintronics in SiGe / Si gains its profit from isotopically clean Si and Ge which reduces the electron / nucleus spin interaction enormously. Both, Si and Ge possess isotopes which have zero nuclear spin. These zero nuclear-spin material will allow two-dimensional carrier transport with long spin conservation because of the lack of interaction with the nuclear spin. Basics of SiGe electron spin resonance transistors and transmutation doping of isotopes are found in [35, 36]. Conventional transistor operation is broadband, but far below a transit frequency fT. Amplification beyond fT in a selected band is called resonance phase operation. Resonance phase operation was demonstrated by our group with a modified HBT [37]. Generally, it allows operation of a transistor far above the transit frequency within a window given by a phase delay of about 180°. This operation mode could be the key to electronic access to the THz regime. The basic principle is based on a high phase delay of a signal (around 180°) without degrading the amplitude of the signal. The technical solution is based on a band-gap engineered base for coherent transport [38] followed by a transit time region.

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The CHI T which allows specific logic operations [39] belongs to the real-space transistor family [20] which uses transport property modulations for the transistor function instead of the capacity modulation of the MOSFET. Therefore it could be superior to MOSFETs in ultralarge-scale integration (ULSI) where the load of the capacitance via long interconnects increasingly determines the system performance. For the SiGe / Si system the attractiveness for system-on-chip (SOC) solutions using a CHINT / HBT integration scheme is enhanced by the same basic structure with pseudomorphic SiGe layers between Si [40].

)       *  First successes with moderately strained channels feed the desire to manipulate the strain in a wider range of magnitude, direction, and sign [41]. Structures able to adjust the strain of SiGe and even Si layers on top of a Si substrate are called strain platforms. A universal solution to strain platforms is given by so called virtual substrates which are composed of the thick Si substrate and an ultrathin (50 nm to 400 nm) strain-relaxed buffer layer of a mismatched material system (e. g. SiGe) offering a surface lattice constant different from the underlying Si substrate. Our group [42] managed to adjust the lattice constant in ultrathin SiGe buffers by nucleation of misfit dislocations from supersaturated point-defect concentrations. Supersaturation of point defects was controlled by Si ion impact (100 eV to 1000 eV energy) or very low growth temperature intervals (Fig. 23).

Fig.23 Virtual substrate with strained-device layer. The ultrathin buffer was grown under point defect supersaturation. [45]

Ge would be a very promising candidate [43] for the 30 nm and below CMOS generation because it is the only common semiconductor with a high hole mobility. The leakage problem with the lowband-gap material Ge (this was mainly responsible that the first Ge transistors were replaced by Si) is strongly reduced by a dielectric insulation scheme (Germanium-on- Insulator (GOI) silicon substrat / oxide layer / thin Ge layer). The GOI fabrication (Fig. 24) will benefit from virtualsubstrate quality and availability.

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Fig.24 GOI (germanium on insulator) fabrication with relaxed Ge on Si (virtual substrate) bonded to an oxide-covered Si wafer. The lower wafer is cut, e.g. by hydrogen implantation with subsequent anneal (smart cut). [45] +   SiGe hetero devices had a broad impact on our understanding of strained-layer and superlattice interfaces and they added significantly to silicon based concepts of quantum effect devices. Some of the earlier concepts proved their superiority in IC manufacturing or will do it in emerging fields within the next generations of the manufacturing process. The manufacturing road map is strongly based on planar processing and deterministic pattern formation. Manufacturing routes beyond CMOS which utilize nonplanar elements and self organization strategies could – and in my personal opinion will – replace the conventional processing by simple cost reasons. SiGe quantum dots and quantum wires with their strain induced tendency to self arrangement and ordering are prime candidates for the building blocks in silicon based alternative manufacturing (Fig. 25).

Fig.25 Ordered Ge dot array on prepatterned Si. [44]

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  , -   In the diamond cubic lattice the dislocations propagate primarily by glide on {111} planes. The dislocation (Fig. A1) is a line defect which is characterized by its local line vector l and its characteristic Burger’s vector b the nature of which is indicated by an atom-by-atom circuit along the path around the dislocation (Fig. A2). The dominant Burger’s vector in the diamond lattice is

Fig. A1. A positive edge dislocation formed by inserting an extra-half layer of atoms between atomic planes above the slip plane

Fig. A2. The Burgers vector of a dislocation represented as a closure failure EA = b in the ideal lattice when a closed circle was drown around the dislocation in a real lattice.

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along 1/2, the Burgers vector length b is a / 2 (0.38 nm in Si). The dislocation cannot end in the interior of a crystal, it ends either at surfaces or is closed as dislocation loop. Under undisturbed conditions the dislocation follows preferentially the directions. A simple construction due to Thompson (Proc. Phys. Soc. B66, 481, 1953) greatly assists in understanding of interactions between dislocations (Fig. A3). The tetrahedron ABCD is made up of the four {111} planes. For convenience this tetrahedron is opened, the vertex D having originally been above the plane of the paper. In Fig. A1 the Burgers vector is perpendicular to the dislocation line, which is referred to as an edge dislocation. Dislocations with Burgers vector parallel to the dislocation line are known as screw dislocations (Fig. A4). Other angels between l and b exist, these are mixed dislocations, e.g. 60o dislocations of AB dislocation lines with AD Burgers vector in Thompson`s reference tetrahedron. Dislocations may easily glide along the {111} slip planes, the slip plane is defined by the both vectors, line direction l and Burgers vector b. Movement of the dislocation perpendicular to the glide plane is called climb which needs generation or annihilation of point defects and is therefore much slower. However, there are four {111} planes and so a dislocation can change to another plane under certain circumstances which is called cross slip: See e.g. in Thompson`s tetrahedron the dislocation with AD Burgers vector, this dislocation may move within the ACD plane and also within the ADB plane (Fig. A3).

Fig. A3. Thompson’s Reference Tetrahedron

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Fig. A4. A right-handed screw dislocation formed by displacement of a part of the crystal above the slip-plane parallel to the dislocation line .

Despite the severe local distortion around the dislocation, there is still matching of the most lattice planes (except the one which causes the displacement b). The strains decrease with increasing distance from the dislocation such that displacement of atoms a few atomic spacings away from the dislocation may be treated using linear elasticity theory. So the energy per length E ds of a single dislocation is given by

E ds =

µ ⋅ b2  R  ln  4π  ri 

for a screw dislocation and

Eds =

R µ ⋅b2 ln  4π (1 −ν )  ri 

for an edge dislocation. ( µ = shear modulus, ν Poisson’s number, R and ri, outer and inner cut-off radius, respectively). The energy dependence on the square of the Burgers vector length b causes the Burgers vector to be usually the smallest possible one: 1/2 . Smaller vectors like a/6 for partial dislocations are indeed possible, but with a plane defect (a stacking fault) connected with. In the Thompson tetrahedron (Fig. A3) the partial dislocation vectors are given by the dashed lines (e.g. Aδ). The core of the dislocations is often split up in two partials with a stacking fault between them (e.g. Aβ + βD for an AD Burgers vector). This complication of the dislocation core is not

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considered further in this short review. Since the strain energy is very large, dislocation lines cannot exist in thermal equilibrium in uniform solids despite the increased configurational entropy. In heterostructure couples a dislocation network at the interface may exist in equilibrium because the homogeneous strain in the heterostructure is reduced. The energy balance is the starting point for equilibrium theories, the manifold of slightly differing results of them are caused by the choices of the cut-off radius Rl and ri, respectively. The inner cut-off radius is of the order of the Burgers vector length b. The outer radius is given by the geometry of the sample as shown for different geometries by v. d. Merwe’s group. In misfit dislocation theory of thin films on thick substrates two situations are especially interesting; for low densities of misfit dislocations the outer cut-off is given by the film thickness t and for high densities it is given by the half distance p/2 to the neighbouring dislocation line. From the energy of a dislocation a force F can be deduced, the resolved shear stress on a glide plane and the straightening tendency of curved lines are then transformed into forces. A very popular equilibrium theory of misfit dislocations from Matthews and Blakeslee is based on the force consideration. The force Fσ of the shear stress is given by

Fσ = 2 µ (b ⋅ cos λ )hε

1 +ν 1 −ν

which tends to extend the misfit dislocation line whereas a restoring line tension force FT acts from the bent arrangement of misfit dislocation and connected threading dislocation (Fig. A5),

FT = µ ⋅ b 2

(1 −ν cos 2 θ )  h  ln  4π (1 −ν )  ri 

This formula accounts for the mixed character of the dislocation (the angle θ between l and b reflects the edge or screw character, cosθ = 1/2 for the common 60° dislocation) and for the effective misfit strain relaxation (the angle λ between the Burgers vector b and line normal in the interface reflects the interface edge component of the dislocation which defines the amount of lattice adjustment, cos λ = 1/2 for the 60° dislocation). Screw components and edge components perpendicular to the interface contribute to a twist-and-tilt of the layer, respectively. These components usually cancel out each other on the four symmetric {111} slip planes on an (100) oriented sample.












Fig. A5. Misfit dislocation: Segment BB’.






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Threading dislocations: Segment AB, A’B’ The lattice adjustment within a linear theory can be given by

f = −ε + (b ⋅ cos λ ) / p = ε + (b ⋅ cos λ ) / p where f is the lattice mismatch (relative difference of the film and substrate lattice constants), ε is the strain, p is the mean misfit dislocation distance and b ⋅ cos λ is the effective Burgers vector ( b ⋅ cos λ = 0.19 nm for a 60° dislocation in (100) Si).

Fig. A6. Formation of dislocation loops by aggregation of (a) interstitials and (b) vacancies.


. /  The cooperation with my co-workers at the institute, especially with M. Oehme is acknowledged. Special thanks to W. Spitzberg (former editor: Wiss. Berichte AEG – Telefunken) who provided early editions of this journal. Financial support is acknowledged from DFG (SiGePIN / Forschergruppe 730), BMBF (SILEM) and from the EU (Nanosil).

0 [1] K. Alberi, ISCS 2007, Abstract Booklet, http://www.iscs2007.org, p. 133 (2007) [2] A. Sakai, S. Takeuchi, O. Nakatsuka, M. Ogawa and S. Zaima, ISCSI – 5, Extended Abstracts, p. 31 (2007) [3] E. Kasper, H. J. Herzog, H. Kibbel, Appl. Phys. 8, 199 (1975) [4] E. Kasper, H. J. Herzog, Wiss. Berichte AEG – Telefunken, 49, 213 (1976) [5] E. Kasper, W. Pabst, Thin Solid Films 37, L5 (1976) [6] E. Kasper, H. J. Herzog, Thin Solid Films 44, 357 (1977) [7] J.W.Matthews and A.E.Blackeslee, J. Cryst. Growth 27, 118 (1974) [8] Q. People, J. C. Bean, Appl. Phys. Lett. 49, 229 (1986) [9] E. Kasper, A. Schuh, G. Bauer, B. Holländer, H. Kibbel, J. Cryst. Growth 157, 68 (1995) [10] J. P. Dismukes, L. Ekstron, R. J. Paff, J. Phys. Chem 68, 3021 (1964) [11] EMIS Datareview 24: Properties of SiGe:C (Eds.: E. Kasper and K. Lyutovich), IEE, INSPEC, London, 2000 [12] R. Kohler, H. Raidt, W. Neumann, J-U. Pfeiffer, H. Schafer and U. Richter: J. Phys. D: Appl. Phys. Vol 38 (2005), p.1 [13] J. Werner, K. Lyutovich, C. P. Parry: Eur. Phys. J. Appl. Phys. Vol. 27 (2004), p. 367 [14] H. J. Osten et al., Appl. Phys. Lett. 71, 1522 (1997) [15] J. Murota, A. Moriya, M. Sakuraba, Proc. 8th Int. Symp. Si Mat. Sci. Technol., San Diego, p.822 (1998)

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[16] [17] [18] [19] [20] [21] [22] [23] [24] [25] [26] [27] [28] [29] [30] [31] [32] [33] [34] [35] [36] [37] [38] [39] [40] [41] [42] [43] [44] [45]

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D.J. Srolovitz, Acta Metall 37, 621 (1989) I. Berbezier and A. Ronda, Phase Transitions (2008)… W.A. Jesser and D. Kuhlmann-Wilsdorf, Phys. Status Solidi 19, 95 (1976) L.C.A. Stoop, Thin Solid Films 24, 243 (1974) E. Kasper and D.J. Paul, Silicon Quantum Integrated Circuits, Springer Verlag Heidelberg (2005) S. Olsen, IEEE Trans.-ED 53, 2296 (2006) G. Hadjisavvas, L. Tsetseris and S. T. Pantelides, IEEE-EDL 28, 1018 (2007) J.-S. Wang, P.-N. Chen, C.-H. Shih, C.Li, P. Su, Y.-M. Sheu, D. Y.-S. Chao and K.-I. Goto, IEEE-EDL 28, 1040 (2007) F. Schäffler, Semiductor Sci. Technol. 12, 1515 (1997) J. Eberhardt, E. Kasper, Solid-State Electronics 45, 2097 (2001) J.D. Cressler, Silicon Heterostructure Handbook, CRC press, New York (2006) Y. C. Yeo, Semiconductor Science and Technology 22, 5177 (2007) H. Ohta, TEDM Tech. Dig., p. 247, (2005) Y. Liu, Proc. Symp. VLSI Tech., p. 247, (2007) M. Oehme, J. Werner, E. Kasper, M. Jutzi, M. Berroth, Appl. Phys. Lett. 89, 071117 (2006) Landolt – Boernstein, New Series, Group III, Vol. 34 C3 (Ed. In Chief: W. Martienssen), Semiconductor Quantum Structures, Optical Properties, Springer (2007) M. Oehme, J. Werner, E. Kasper, S. Klinger and M. Berroth, Appl. Phys. Lett. 91, 051108 (2007) M. Jutzi, M. Berroth, G. Wohl, M. Oehme, E. Kasper, IEEE Photonic Techn. Lett. 17, 1510 (2005) J. Yu, E. Kasper, M. Oehme, Thin Solid Films 508, 396 (2006) R. Vrijen, E. Yablonovich, K. Wang, H. W. Jiang, A. Baladin, V. Roychowdhury, T. Mor, D. Di Vincenzo, Phys. Rev. A 62, 012306 (2000) I. S. Shlimak, Phys. Solid State 41, 716 (1999) E. Kasper, J. Eberhardt, H. Jorke, J.-F. Luy, H. Kibbel, D. W. Dashiell, O. G. Schmidt, M. Stoffel, Solid-State Electronics 48, 837 (2004) A. A. Grinberg, S. Luryi, IEEE Trans. ED-40, 1537 (2003) M. Mastrapasqua, C. A. King, P.R. Smith, M. R. Pinto, IEEE Trans. ED-43, 1671 (1996) E. Kasper, German Patent, 198 607 01 (1998) E. Kasper and K. Lyutovich, Properties of Silicon Germanium and SiGe: Carbon, EMIS Datareviews Series 24, INSPEC (IEE), London (2000) K. Lyutovich, F. Ernst, E. Kasper, M. Bauer, M. Oehme, Solid State Phenomena 69-70, 179 (1999) C. Claeys and E. Simoen, Germanium-based Technologies, From Materials to Devices, Elsevier Amsterdam (2007) A. Karmous, A. Cuenat, A. Ronda, I. Berbezier, S. Atha and R. Hull, Appl. Phys. Lett. 85, 6401 (2004) E. Kasper, Appl. Surf. Sci. 254,6158 (2008)

Materials Science Forum Vol. 608 (2009) pp 55-109 © (2009) Trans Tech Publications, Switzerland doi:10.4028/www.scientific.net/MSF.608.55

The Influence of Defects and Impurities on Electrical Properties of Highk Dielectrics J. Dąbrowski¹, S. Miyazaki², S. Inumiya³, G. Kozłowski¹, G. Lippert¹, G. Łupina¹, Y. Nara², H.-J. Müssig¹, A. Ohta², and Y. Pei³ ¹IHP, Im Technologiepark 25, 15236 Frankfurt (Oder), Germany ²Graduate School of AdSM, Hiroshima University, Kagamiyama 1-3-3, Higashi-Hiroshima 739-8530, Japan ³Semiconductor Leading Edge Technologies, Inc., 16-1 Onogawa, Tukuba 305-8501, Japan Abstract: Electrical properties of thin high-k dielectric films are influenced (or even governed) by the presence of macroscopic, microscopic and atomic-size defects. For most applications, a structurally perfect dielectric material with moderate parameters would have sufficiently low leakage and sufficiently long lifetime. But defects open new paths for carrier transport, increasing the currents by orders of magnitude, causing instabilities due to charge trapping, and promoting the formation of defects responsible for electrical breakdown events and for the failure of the film. We discuss how currents flow across the gate stack and how damage is created in the material. We also illustrate the contemporary basic knowledge on hazardous defects (including certain impurities) in high-k dielectrics using the example of a family of materials based on Pr oxides. As an example of the influence of stoichiometry on the electrical parameters of the dielectric, we analyze the effect of nitrogen incorporation into ultrathin Hf silicate films.

1. Introduction Fabrication of microelectronic chips is more economical when elements occupy less area of the chip. This leads to miniaturization and performance improvement1,2,3. Development of high density Complementary Metal Oxide Semiconductor (CMOS) devices requires the fabrication of capacitor structures in which a high capacitance density is achieved. The technological specifications depend here on the application, being different for MOS Field Effect Transistors (MOSFETs) and for Metal Insulator Metal (MIM) capacitors; within these groups, they are different for MOSFETs in highperformance microprocessors and in low-power microprocessors, and for capacitors fabricated during front-end and during back-end processing3. Nevertheless, if the increase in the capacitance density is achieved by a decrease in the film thickness, then in all cases a troublesome side-effect is a strong increase in the leakage current, leading to unacceptably high power consumption and to degraded reliability (lifetime and performance) of the integrated circuit. This side-effect may be alleviated if the dielectric has a higher dielectric constanta. The focus of the current search for such high-k materials centres on hafnium, zirconium, and rare earth metal oxides4,5,6,7,8. Production of circuits containing MOSFETs with high-k (probably HfO2/SiO2 or HfSiON/SiO2) gate stacks was announced by Intel in January 2007 for 45 nm technology node9, followed by a similar announcement made by IBM and, later, also by AMD; the chips are on the market by now. Estimates show that even the stringent requirements for MIM capacitors in DRAM (10-8 A/cm² at 0.55 V and 0.40 nm equivalent oxide thickness10) could be fulfilled by a material with a modest tunnelling barrier height with respect to the metal gate (about 2.3 eV), a typical effective electron mass (above about 0.2 me), and dielectric constant achievable, for example, in group-II hafnates and zirconates, which is about 40-50. A material with similar properties but having the dielectric cona

The dielectric constant is often designated by the letter k; hence the name “high-k” for the materials with high dielectric constant. For practical reasons, in the equations in this Chapter we adopt the symbol  instead of k.

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stant somewhat below 200 would solve the problem at least until the year 2022; a group-II titanate or tantalate might be the possible solution. However, electrical properties of thin high-k dielectric films are influenced (or even governed) by macroscopic, microscopic and atomic-size defects11,12,13,14. Defects open new paths for carrier transport, easily increasing the currents by orders of magnitude, causing instabilities due to charge trapping, and promoting the formation of defects which damage the film permanently. Interaction with the substrate may lead to contamination11. Charge traps are generated in the bulk of the film and at the interface during charge injection into the oxide15. The majority of responders to the poll conducted during the International Integrated Reliability Workshop in 2005 thought that traps are most critical challenge for high-k integration16. Introduction of new gate dielectrics into CMOS technology gives rise to a number of problems. These problems can be divided into two groups. First, there are processing issues associated with controlled growth of high-quality films: - Stoichiometry and crystallography; - Dielectric constants; - Fixed charges (trapped charges which cannot be re-charged); - Electrically active bulk and interface states. and with other fabrication steps in the CMOS process flow: - Thermal stability (films must survive processing temperatures); - Interaction with dopants, atoms from the electrode and impurities such as, H, N, or C. Second, there are device issues associated with the electrostatic potential drop across the dielectric in the operating transistor and capacitors: - Leakage currents (associated with band offsets, band structure, defect states); - Bias Temperature Instability (associated with charge trapping); - Flatband and threshold voltage shifts (associated with charges and dipole moments); - Lifetime of the dielectric (degradation mechanism, associated with leakage currents). Reliability concerns for high-k gate oxide are partially related to those of ultrathin SiO2. First, both are the cases of weakest-link problem and can be treated within the framework of Weibull statistics17, in particular, within the framework of the percolation model18. Second, in MOSFETs a SiO2 or SiO2-rich interface layer is present on the boundary between Si and the dielectric. This layer is the weakest element when the primary sources of damage are electrons emerging from the oxide (gate injection when pMOSFET is in ON state). The interface layer is also exposed to the most of the electrical stress, since it has a lower dielectric constant than the rest of the dielectric. The electric field, the amount of charge transported across the structure, and the energy of these charges are the key quantities responsible for wear-out and failure of the dielectric. Consequently, a failure event in a high-k gate dielectric stack of a good quality is initiated in the SiO2 interface layer19,20, at least for gate injection (for substrate injection, as in nMOSFET in ON state, the opposite may be the case21,22). What is new in materials with high dielectric constant, notably those with the perovskite structure, is that they exhibit defect-induced instability (resistance switching, see e.g., Ref.23 and references therein). While such effects may be used for Non Volatile Memories (NVM, e.g., Refs. 24 and 25), when undesired they may change the leakage current even by orders of magnitude during the device operation. Moreover, the leakage through undamaged ultrathin SiO2 gate dielectrics is dominated by tunnelling through the defect-free regions26, but the leakage in an undamaged HfO2 film is likely to be completely defect-controlled at low voltages22. Since defect-assisted leakage increases with the applied voltage weaker than the leakage through defect-free dielectric (at least if the applied voltage exceeds the distance from trap state to the Fermi energy), it follows that the factors governing the

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reliability at device operating conditions (low voltage) may be hidden under test conditions (high voltage). For completeness, we note that it remains the common feature of SiO2 and high-k that the breakdown mode of ultrathin high-quality films shifts from easily detectable hard breakdown to much less pronounced, noisy soft breakdown27,28. At the same time, such reliability issues as Bias Temperature Instability29,30,31 (BTI), may have more impact in high-k dielectrics. BTI (an effect caused by trapping of charges32,33 on defects) occurs in high-k gate dielectrics both as Negative BTI34 (NBTI, known in SiO2 pMOSFETs) and as Positive BTI35 (PBTI, destabilizing high-k nMOSFETs). These issues fall however beyond the scope of this presentation.

2. Leakage Mechanisms 2.1. Static leakage, relaxation current, and displacement current A characteristic feature of leakage currents flowing across dielectric layers is that it usually takes a certain amount of time (measured in seconds or minutes) from the moment when the bias is applied to the stabilization of the measured current36. The transient currents are not only flowing for a much longer time than the duration of the displacement current expected given the RC product for the film, but they tend to exhibit logarithmic dependence on time, in the form of the empirical Curievon Schweidler law37, I ~(1/ t)n, with n between 0 and 1 (for the general treatment allowing for the broader range of n up to 2, see Jonscher38). The physical origin of this dependence may stem either from bulk properties of the film (effects such as relaxation of dipoles in the dielectric and re-distribution of the trapped charge under the influence of the applied electric field38,39) or from the interface. When the relaxation is due to the dielectric polarization, the amount of the relaxation current measured at a given gate voltage should be independent of film thickness but correlated to the magnitude of the electric field pulse (or step) corresponding to the voltage pulse (or step) that causes the transient38 as, e.g., in BSTO40 (Ref. 40 compares relaxation in SiO2, SiO2/Si3N4, Al2O3, HfO2, Y2O3, Ta2O5, and BSTO and discusses its impact on MOSFETS and DRAM capacitors). When the relaxation arises due to trapping and de-trapping, one expects thickness dependence, because the electric field affects the tunnelling probability. The logarithmic dependence is then due to the fact, that charge tunnels more slowly from (and to) more distant traps41. Such transients are small in thermal silicon diode42, although already pronounced in deposited SiO2 films43. Even in thermal SiO2 the leakage current (in Fowler-Nordheim regime) may decrease by one order of magnitude during one hour44, but the relaxation currents become really substantial in, for example, hafnium oxide45, aluminium oxide45,46, and tantalum pentoxide47; we also observe them in our Pr-based oxides. 2.2. Intrinsic limits on leakage The material cannot be made more insulating than the tunnelling across a defect-free film allows. This tunnelling current J flowing when the voltage V is applied across a homogeneous dielectric with the thickness t ox can be approximated as48,49 2  Aeff  V  m* q 2 B  V   ,   exp   2 t ox J (1) 2   q  B  t ox   2  

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Fig. 1. Dielectric constant  LF needed to fulfil ITRS requirements for leakage and EOT, assuming that the dielectric film is perfect, that the barrier for tunnelling is 1.8 eV for MOSFET gate dielectric and 2.0 eV for MIM capacitors (2.3 eV if  LF < 50), that the leakage current is described by the effective mass of 0.2 me, and that the prefactor is approximately the same as for Al/SiO2.

where  B is the tunnelling barrier and q is the electron charge. This expression is obtained by approximation of the WKB expression given by Simmons48 and works fine when the voltage is not too close to the Fowler-Nordheim (FN) regime, i.e., V is sufficiently smaller than ΦB; in addition, t ox cannot be too small (but thicknesses of the order of 1 nm are still in the range where the equation reasonably holds). The prefactor Aeff depends to a certain extent on the materials parameters and for Al/SiO2/n-Si films (given the data of Ref. 48) is of the order of 4107 if t ox is expressed in nm, qΦB in eV, V in V, and J in A/cm². Using a slightly more sophisticated model, in which the influence of the image force is also included, we now estimate what dielectric constant is needed to fulfil the requirements of the ITRS for EOT and leakage current in DRAM storage mode capacitors10 (given that the leakage should not exceed about 10-8 A/cm² at the specified voltage) and also in transistors in high-performance circuits50. Figure 1 shows that a perfect material with the (low frequency) dielectric constant  LF around 10, with the tunnelling barrier of 1.8 eV, and with the electron effective mass of 0.2 me would fulfil the Roadmap specifications for transistors in high performance circuits till the end of the Roadmap. As for DRAM storage capacitors, the solution till the year 2019 would be a material with the dielectric constant of about 100, and till 2022 – with the dielectric constant about twice higher. (We assumed a higher barrier in DRAM, since MIM capacitors will have metal electrodes with work functions as high as practicable). 2.3. Work function, Schottky barrier, and interface effects There are three classes of issues associated with the boundary between the dielectric and the electrode. First, the carriers entering the dielectric are confronted with an energy barrier there. Second, the film may be rough and its thickness may vary from place to place. Third, the interface may have

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Fig. 2. Temperature dependence of leakage across perfect dielectric films with various thicknesses. The barrier at zero bias,  SE, is set to 1.2 V and the effective electron mass is 0.2 me.

its specific electron states, either due to defects or to the change of the potential seen by the electrons as they approach the boundary. First, we will consider the energy barrier. In thicker films the leakage may be dominated by Schottky thermal excitation of electrons above this barrier. If, for some reason, the contacts cannot quickly enough supply as many carriers as the film might let through, i.e., when the bulk of the film is conducting more than the contact to the electrode, the current is “contact limited”. Schottky voltage dependence of the leakage current flowing across a homogeneous dielectric of thickness tox under voltage V applied across the oxide, is51      SE   SE V   t ox  , (2) J SE  A* T ²exp  k BT where T is the temperature, kB is the Boltzmann constant, A* = 120(m*/ me) A/(cmK)² is the effective Richardson constant,  SE is the barrier at zero voltage, and the factor β SE equal to 1 q³ , (3)  SE   SEmetal  2    0 measures the amount of barrier lowering under electrical field V/tox;  0 is the dielectric permittivity of free spaceb. The barrier is lowered by the image force: the carrier injected into the dielectric is attracted back to the electrode by its electrostatic image in metal. The amount by which the barrier lowered depends on the applied voltage because the full barrier height corresponds – by construction - to the situation when the carrier in the conduction band of the insulator is “infinitely” separated from any other materials.

b

Note that the dielectric constant that enters Eq. (3) is the high-frequency  , not the low-frequency  LF, the high-k dielectric constant of technological interest; this is because the atomic vibrations which are responsible for  LF are not fast enough to respond to the motion of the electron.

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Fig. 3. Temperature dependence of leakage across perfect dielectric films with various thicknesses. The barrier at zero bias,  SE, is set to 1.0 V and the effective electron mass is 0.2 me.

Figure 2 illustrates the Schottky emission in films with the barrier 1.2 V at zero bias and having different thickness, from 4 nm to 10 nm. It is evident that at room temperature a noticeable thermal current appears only in the thickest film. In thinner films the tunnelling current clearly dominates; this current depends on temperature only weakly. It is also worth noticing that Schottky emission is more pronounced at lower voltages. Nevertheless, below 1 V only insignificant Schottky current is measured at room temperature. This changes when the barrier is lowered to 1 V (Fig. 3): although also in this case the Schottky component is significant at room temperature only in the thickest film, it grows now to roughly 10-6 A/cm² at 1 V. In principle, it is thus difficult to expect a significant Schottky current in a typical room temperature measurement when the barrier exceeds the height of about 1 eV; the current would then be either below the detection limit or would be overshadowed by the tunnelling component. This means that in practice the observation of a real Schottky emission indicates that either the material cannot be regarded as an insulator suitable for MIM capacitors (the barrier is too low), or that the leakage current flows predominantly through large-area macroscopic defects connecting the electrodes of the capacitor. For example, it may happen that the barrier has been locally lowered by a high concentration of charge trapped at the interface, which produced a strong electrical dipole moment. Our previous work52 has shown that the interface dipole moment may strongly depend on the arrangement of atoms and may be strong enough to affect the barrier height by as much as 1 eV. It is therefore imaginable that inhomogeneities, local surface contamination, or local crystallization of the film may result in the appearance of local Schottky conducting spots. Interface dipole moment formation has been invoked as a general mechanism affecting the barrier seen by the carriers53. The barrier height is also affected by chemical changes at the interface, that is, by the formation of an interface layer. The typical example is the SiO2 interface layer that separates the high-k dielectric from the silicon substrate in MOSFETs. This layer introduces an additional barrier for carriers; naturally, this comes at the price of the effective dielectric constant, and therefore its presence deteriorates the leakage current at the target EOT. It also has a detrimental effect on reliability of the gate stack, but appears to be necessary in order to maintain a high mobility in the channel. In the

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Thickness 6nm

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Thickness variation Δt, nm Fig. 4. Leakage currents at 1 V in films having different nominal thicknesses t (4, 6, and 8 nm) and the same thickness inhomogeneity of 0.4 nm rms. The barrier is 2.3 eV and the effective mass equals to 0.2 me. Normal distribution of areas with thickness deviation Δt from the median is assumed (solid line). The ordinate gives the current density flowing through the film area with thickness equal to t+Δt; this current density is weighted by the normal distribution.

final balance, what counts is the ratio of the mobility to the EOT, obtained at the conditions satisfying the leakage and reliability constraints. Interface layers may also have a lower barrier than the bulk of the film. An example is a TiO2containing layer that may exist in capacitors grown on TiN substrates. Naturally, this effect is not limited to MIM capacitors but applies also to gate oxides with some metal gates. Leakage is also affected by local film thickness variations. For example, if the barrier is about 2 eV, the effective mass is about 0.2 me, and the current is measured around 1 V, the leakage through an otherwise perfect, several nm thick film increases approximately one order of magnitude for each 0.3 nm rms (root mean square) of thickness variation. This estimate is obtained under the assumption that the power spectrum of film thickness distribution contains significant contribution only from waves long enough that the electric field E(x,y,z) may be approximated as E(x,y), where x and y are the lateral coordinates. Figure 4 shows that the maximum current flows through regions thinner than the nominal thickness by about 1 nm; this offset is larger in thinner than in thicker films Surface roughness influences the leakage and, in the course of events, also the oxide reliability. This has recently been discussed54 in the context of ZrO2 and TiO2. The third group of issues is associated with the interface states. There are several effects in this group: Fermi level pinning, charge trapping and re-trapping, leakage, and failures. Fermi level pinning was in focus of interest because it was difficult to obtain gate electrodes with suitable work functions: one matching the Fermi level of n-type silicon channel, and one matching the Fermi level of p-type silicon channel. It seemed that enough interface states were located at the boundary between the dielectric for the electrode to pin the Fermi level at a fixed position55. Effects

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Fig. 5. Leakage currents caused by the presence of positively charged defects located close to the anode interface (points with lines). The areal density of defects is of the order of 1% of the interface atomic sites. The potential barrier of the film is 2.3 eV, the effective electron mass is 0.2 me. The lines without points mark the current flowing across such a film without defects but with thickness inhomogeneity as indicated (rms). Data for films with nominal thicknesses of 8 and 4 nm.

such as the dependence of the metal-gate work function on the annealing temperature56, or work functions for various metals either limited to a narrow range of values55 or spread over a considerable range57 have been reported in this context. Defects in the dielectric (specifically, oxygen vacancies in HfO2) have been invoked in order to explain this behaviour. However, it turned out that the physical background of this apparent pinning is the different orientation of metal crystallites at the interface58. At any case, the problem has been solved technically and dual metal gate band edge technology is now available for HfO2 gate oxide stacks. Second, re-charging (charge trapping and de-trapping) of states distributed within a certain distance from the interface is responsible for relaxation currents. If one assumes that the trap depth (i.e., the tunnelling barrier) is of the order of the conduction band offset between Si and HfO2 (1.8 eV) and estimates the tunnelling time as a function of tunnelling distance, one finds (using the expression derived by Lannoo et al.59,60 and 0.3 me for the effective mass of electrons in the dielectric) that the lifetime of the trapped electron is 50 s for a trap located 4.8 nm away from the interface. This time decreases rapidly to 2 s when the distance is reduced 4.4 nm and becomes about 0.1 s at 4.0 nm and about 0.1 ms at 3.0 nm. No significant relaxation effects should be thus observed in films thinner than about 8-9 nm. Still, the typical logarithmic relaxation has been observed even in 6 nm HfO2 films45. The reason is that the interfacial SiO2 prevents de-trapping45,54 Interface states also promote leakage. This may happen because interface states extend into the film and locally reduce the effective thickness of the dielectric in this way. Also, if a defect is located so close to the interface that the carrier life time on the defect state is very short, the presence of the defect shifts locally the edge of the film from the materials boundary to the depth where the defect potential is strong enough. Figure 5 illustrates the later effect on the example of a positively charged defect which – when located in the bulk of the film – would introduce a bound state about 0.5 eV above the Fermi level at zero bias. The film is assumed to be otherwise homogeneous, with 2.3 eV tunnelling barrier and the effective electron mass of 0.2 me. The defects are modelled by onedimensional quantum well 0.2 nm wide, the total current flowing through these defects is obtained

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by multiplying the computed current by 2% (which corresponds to less than 2% areal density of defected sites, because the capture cross section for a charged defect is larger than the physical dimensions); the Coulomb interaction is assumed to depend on the distance as for a point charge, not as for a uniformly charged, three-dimensional sheet to which such one-dimensional quantum well corresponds. A series of image point charges was added to the electrostatic potential. Such defects were placed at three distances from the interface: 0.6 nm, 0.9 nm, and 1.2 nm, one at a time. The current increase due to each of these defect families is clearly visible on top of the leakage through the perfect and flat film. Around 1 V, this increased current has a magnitude similar to that due to thickness variation of several Å rms; the equivalent rms inhomogeneity increases with film thickness and with the distance of trap from the interface. The maximum in the IV characteristic due to the most distant trap in the 8 nm film (Fig. 5, left) is a signature of an efficient localization of the electron on this trap: when the maximum of the resonant transmission probability on the path through this defect drops below the Fermi energy in the metal electrode, this leakage path becomes increasingly difficult to follow. In the context of defects in the interfacial region it is worth mentioning that if Si substrate is oxidized during the deposition, this is expected to be a poor oxidation process. First, it takes place at temperatures low compared to the temperature needed to obtain a good oxide. Second, the ultrathin interfacial oxide layer grows under mechanical constraints imposed by the hard high-k material covering it, while the interface grown during thermal oxidation is placed under a free silicon dioxide layer which can easily accommodate any stress and strain from the interface because the oxidation temperature exceeds the temperature at which viscous flow of SiO2 begins. Third, also postdeposition anneals of high-k films are typically conducted well below the usual temperatures for thermal oxidation. Creation of interface defects during device operation will eventually lead to failure of the ultrathin oxide: when two neighbouring defects are created, one at the substrate interface and the other at the gate interface, this may be sufficient to produce a conducting path across the dielectric. An interesting observation has been reported in this context61: Weibull slope of ultra-thin (1.36-1.72 nm of physical thickness) oxynitrides increased from about 1 at low current to about 2 at high current as gate current increased during Constant Voltage Stress. As discussed in Section 3.2, Weibull slope is proportional to the average number of defects needed to form a breakdown path. The authors attribute this effect to low trap generation at SiON/Si interface, where most of nitrogen resides. 2.4. Leakage due to bulk point defects Electrically active point defects contribute to the leakage in two physically different ways. First, they may act as midway stops for tunnelling electrons. This is the worst case worst from the point of view of power losses, because such a defect locally decreases the effective thickness of the dielectric by dividing the tunnelling process in steps; since the tunnelling probability depends exponentially on the barrier thickness (cf. Eq. 1), this causes a dramatic increase in the leakage current, particularly when the defect is located right in the middle of the film. In other words, the presence of a significant amount of such centres makes it impossible to achieve the parameters estimated for the perfect material (cf. Fig. 1). The effect exerted by positively charged point defect sites close to the anode has been already illustrated in Fig. 5. We will now consider the case of defects located further away from the interface.

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Current density, A/cm²

1.E+00

at 3.9 nm at 3.3 nm

1.E-02

at 2.7 nm

1.E-04

at 2.1 nm

1.E-06 at 1.5 nm at 0.9 nm

1.E-08 at 0.6 nm

ideal film (8 nm)

1.E-10 1.E-12 0.0

0.5

1.0

1.5

2.0

Applied voltage, V Fig. 6. Leakage caused by the presence of positively charged defects located at various distance to the anode interface. The volume density of defects in each family is about 1020/cm³, as in Fig. 5. The defect and film parameters are as in Fig. 5; the high concentration of 1020/cm³ was chosen to facilitate the comparison with Fig. 5. The defects are assumed to be non-interacting, hence their contribution to the current scales linearly with their density. Above 2 V (not shown), the currents due to traps closer to the interface converge to the Fowler-Nordheim IV of the perfect film.

It may happen that the distance between such defects is so small that charge carriers tunnel from one defect to the other, thus dividing the route under the potential barrier into several (or many) short steps. This hopping may result in current-voltage characteristic which – depending on the ratio between the dielectric relaxation time and the carrier transit time – is either space-charge limited or ohmic. Ohmic behaviour appears when the voltage drop between subsequent defects is small; in this case the tunnelling current is approximated by linear current-voltage dependence. The character of voltage dependence of space-charge limited current results from re-distribution of the electrical field in the material in response to the presence of injected carriers62. This current is typically proportional to the squared voltage and reversely proportional to the third power of the dielectric thickness. It may also happen that there is only one defect in the path. We may then observe a Trap Assisted Tunnelling (TAT) current. A TAT centre is most efficient when located in the middle of the film (Fig. 6). In practice, a TAT defect located there halves the effective tunnelling thickness. Fortunately, this comes with the pre-exponential factor proportional to the area fraction of the middle part of the film occupied by the defect, that is, roughly to the ratio ND/No, where ND is the concentration of traps and No is the concentration of atomic sites. The localization of carrier on the trap contributes to the tunnelling characteristic of the defect. When the defect is close to the interface, it cannot hold its electron (or hole) for a long time, and as a consequence, its trap state becomes broadened; the major contribution of such a defect to the current occurs directly via the change of the effective tunnelling length (cf. the discussion of Fig. 5). But when the trap is located far away from the contacts, the tunnelling probability has a pronounced resonance centred close to the energy of the trap state in the bulk (infinite distance to any interface). This translates into a resonant character of the current flowing across a single family of defectsc. As long as the applied voltage is small enough that the defect state remains above the Fermi level in the c

Defects occupying the same distance from the interface and having the same energy of the trap state.

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electrode, carriers must be thermally excited in order to take advantage of the leakage path through this defect. The low voltage part of the IV characteristic dominated by the mid-film defects in Fig. 6 is thus temperature dependent, with the activation energy roughly corresponding to the distance to the Fermi energy in the cathode; this is the trap filling regime. But when the applied voltage shifts the trap state down to the Fermi energy, the current reaches its maximum. Further increase of the voltage makes the defect-assisted leakage path less accessible, because this path is most efficient for electrons arriving from the energy matching that of the resonance. With increasing voltage, the energy of origin of these electrons moves further and further away from the conduction band of the dielectric. The tunnelling barrier thus increases and the current drops. Apart from the trap filling regime, tunnelling currents depend weakly on temperature. Temperature dependent leakage assisted by defects is however observed when the leakage path is dominated by thermal escape from the defects. This happens when tunnelling of carriers from the defect to the other electrode is less probable than thermal emission from the defect. In this case the current reflects the thermal emission probability, at least until the electrode can supply enough carriers to the defects that this supply does not limit the current. If the defects are positively charged when empty, the thermal emission barrier is lowered by the electric field: the carrier is electrostatically attracted back to the defect. This leads to a similar functional dependence of the current on the electric field as for Schottky emission. This change of the barrier for thermal escape in response to the electric field is known as Poole-Frenkel (PF) effect63. A conceptual difference between Poole-Frenkel effect and Schottky effect is that in the former the attracting charge is real and resides on the point defect, while for Schottky effect this charge is an electrostatic image induced in the metallic contact. Poole-Frenkel current is thus bulk-controlled, while Schottky current is contact-controlled. Since the distance between the separated charges is doubled in Schottky effect (assuming metal contacts) in comparison to Poole-Frenkel effect, Poole-Frenkel barrier lowering is described by the factor β PF twice as large as SEmetal (cf. Eq. 3):

 PF  2 SEmetal 

q³

 eff  0

.

(4)

In the ideal case, the effective dielectric constant eff is equal to the squared optical refraction index n, that is, to the high-frequency dielectric constant   of the film, as for Schottky effect (in amorphous film, eff may turn out quite different64). One might therefore expect that although both mechanisms reveal themselves by a linear dependence of log(J) on V ½, the slope is twice as large if Poole-Frenkel emission is at work, and that this difference in slope constitutes the criterion to decide whether the leakage is contact- or bulk-controlled. Unfortunately, Poole-Frenkel emission may (and sometimes does) exhibit the same slope as that derived from Schottky equations (2) and (3). This is due to statistics of electrons in the conduction band. When the material is uncompensated, that is, when the Fermi level is between the conduction band and the states from which the electrons are emitted, the concentration of electrons in the conduction band follows the formula for intrinsic material:    n u  exp   PF  , (5)  2 k BT  where  PF is the energy distance between the conduction band and the emitting states. The doubling of the field-induced barrier lowering is now cancelled by the factor 2 in Eq. 5, so that the slope in log(J) vs. V ½ plot is equal to that for Schottky mechanism65. On the other hand, when the material is compensated, i.e., when at T=0 there are partially occupied states in the gap, the concentration of electrons in the conduction band is described by

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Fig. 7. (Left) Poole-Frenkel plot for the PrAlO3 sample (Fig. 9, left) on TiN substrate and with Au top electrode. Steeper lines correspond to the compensated Poole-Frenkel slope, the less steep lines – to the uncompensated Poole-Frenkel slope. The compensated Poole-Frenkel mechanism appears to govern most of the leakage from TiN to Au, but it can be recognized only at negative voltages exceeding -1.3 V when the current flows from Au to TiN. (Right) In the negative voltages region down to -1 V, the current flowing from Au is space-charge limited. After Ref. 11.

   nc  exp   PF  .  k BT  Only in the latter case is the Poole-Frenkel slope indeed twice as steep as the Schottky slope.

(6)

Generally speaking, effects like the compensation degree65, interaction between traps66, energy distribution of trap states67, or change of the shape of the trapping potential by the electric field68 may influence the value of β PF. Since even a neutral defect has a trapping potential that differs from a well with vertical walls, thermal emission from a neutral trap is also affected by the electric field: the barrier is lowered because a monotonously decreasing potential (due to the applied voltage) is added to it. The sensitivity of the barrier height to the electric field decreases with decreasing spatial extension of the trapping potential. The functional dependence of the barrier on the applied voltage is related to the shape of the potential69. In order to be able to assign a Schottky slope to a contact-controlled mechanism, one may compare the current flowing across the same dielectric but from electrodes with different work functions. This can be easily done in MIM capacitors with different bottom and top electrodes. If the current is contact-controlled, reversing the bias will result in a change in the barrier and in a significant change in the emission current. If the current is bulk-controlled, the emission current should be symmetric, at least in the first approximation. This method has been used in the literature to make the distinction between these two mechanisms65. Unfortunately again, the above criterion holds under the assumption that the dielectric stack itself is symmetric. Figure 7 illustrates what can happen when this assumption fails. The left panel contains a log(J/V) vs. V ½ plot for a Au/PrAlO3/TiN sample with 12 nm PrAlO3 film. The linear dependence for positive voltages (electrons arriving from TiN) has the compensated Poole-Frenkel slope. When the bias is reversed, Poole-Frenkel process is observed only at negative voltages exceeding about 1.3 V. The current flowing from Au to TiN is considerably lower than from TiN and Au and is limited by space charge at negative voltages down to -1 V (Fig. 7, right). This indicates that the (more reactive) interface to TiN has developed an interfacial region where charge can be trapped on defects which are positively charged when empty. Electrons are efficiently trapped there only when the external electric field counter-acts the internal field due to the presence of space charge; otherwise, any trapped electrons are thermally emitted. These traps do not exist under the Au contact. In this particular case, the trap states were attributed11 to Ti atoms substituting metal atoms in PrAlO3.

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Fig. 8. Nano-size defects produced during a failed growth of 13 nm PrAlO3 on TiN. (Left) AFM topography and (middle) C-AFM current map. The current flows through depletions about 1 nm deep. (Right) Higher resolution AFM scan: the defects have structured bottom. After Ref. 11.

Finally, we note that in contrast to semiconductors, a point defect in a dielectric does not have to introduce “deep” states into the forbidden gap in order to be a potential hazard to the electrical quality of the material. A deep state means that it is associated with a wave function derived mostly from the orbitals of the atoms directly involved in the formation of the defect. for example, from an orbital which is “dangling” due to unsatisfied valence of the impurity atom to which it belongs. A charged defect may also bind a carrier directly by its electrostatic potential. The binding energy of a carrier in Coulomb potential is proportional to the effective mass of the carrier and reversely proportional to the square of the high-frequency dielectric constant  . The high-frequency dielectric constant is considerably (e.g., three times) smaller in the dielectrics of our interest than in semiconductors; this correlates with higher band gaps of the dielectrics. As a consequence, “shallow” states in a dielectric have noticeably larger binding energies than shallow states in Si or in GaAs and can be of the order of 1 eV. These formally shallow states behave thus like deep states (at least from the point of carriers flowing or tunnelling across the dielectric) and the defects involved can act as TAT or PF centres. 2.5. Macroscopic process-induced defects There are many sources of macroscopic defects. For example, local variations in surface strain (as on strained Si or on SiGe) affect the surface oxidation rate, and hence the thickness of the interface layer with high barrier for carriers54. For films grown on conventional Si or on metal electrodes (as on TiN for MIMs), macroscopic thickness variations may be caused by surface nano-roughness (e.g., by dust particles, TiN grains, etc.). Another possibility is that surface contamination affects either the initial film growth or becomes responsible for some chemical interaction between the surface and the film during post-deposition anneal. Conducting Atomic Force Microscopy (C-AFM) images in Fig. 8 illustrate a suspected case of such a reaction with the substrate11. After an initially flat (0.3 nm rms) PrAlO3 film deposited on TiN at room temperature was annealed at 700°C, it developed 107/cm² of circular depressions, 1 nm deep and 500 nm wide in average. This was accompanied by a strong increase in the leakage measured on macroscopic (310-3cm²) contacts. The whole leakage detectable by C-AFM was localized at these circular hot spots. Grain boundaries are often the weak spots through which more current flows. However, this is not necessarily always the case. As an example11 consider Figure 9 showing again a C-AFM image, but

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Si[200]

Intensity [cps]

3

10

2

10

1

10

30

31

32

33

34

35

36

37

38

39

40

TwoTheta [degree]

Fig. 9. (Left) θ-2θ spectrum of a 12 nm PrAlO3 film grown on TiN at room temperature and annealed at 900°C. The sharp peak around 33° comes from the Si substrate, on which the TiN layer was grown. (Right) AFM topography overlaid with C-AFM current map, taken for the 900°C sample. The black areas indicate the hot spots through which the leakage current flows, while the red and dark red colour shows the height. The images for the 700°C sample are similar, but the wormlike structure is not visible. See text for discussion. After Ref.11.

this time obtained from a sample in which strong crystallization after 900°C anneal was evident from XRD. In the sample cut from the same wafer (12 nm PrAlO3 deposited by MBE on TiN substrate at room temperature) and annealed at 700°C no crystallization could be unambiguously detected. The AFM topography of the 700°C sample (not shown) is featureless, while the 900°C sample exhibits a characteristic wormlike structure (visible also in SEM, not shown) and most probably indicating the location of grain boundaries. The wormlike protrusions running along the boundaries may consist of amorphous PrAlO3 trapped between the grains and possibly containing some amorphizing TiO2 admixture from the substrate. The whole leakage detectable by C-AFM flows in both samples through very localized hot spots with diameters below 30 nm (which is the size of the AFM tip apex) and area density of 109 cm-²; also the macroscopic leakage current is nearly the same for both samples. The position of the hot spots does not correlate with the position of the grain boundaries. The origin of the hot spots is unclear, but it cannot be excluded that they are created around extended defects which form in the initial phase of growth, and are possibly decorated with Ti atoms arriving from the substrate. Detailed analysis of the influence of processing steps of other dielectrics on the microscopic defect structure visible in C-AFM can be found, for example, in Refs. 70, 71, and 72. Impurities like Ti and other point defects may be associated with extended defects, as it was probably the case in the example shown in Fig. 9. The impurities and/or defects may also be distributed over the bulk of the film. If they can temporarily trap and release electrons (in other words, if they introduce electron transition states into the forbidden gap of the dielectric), they may act as leakage centres. For an example of a resistivity switching effect attributed to dislocations and oxygen vacancies in SRTiO3, see Ref. 73. The bottom line is that – since the deposition process that is necessary to grow high-k films depends on more parameters than a standard thermal oxidation process used to grow SiO2 films on Si – it is not straightforward to take over the results of materials screening in research labs as directly representing the behaviour of these materials when produced in a fully qualified commercial process. While such parameters as crystallographic structure, chemical and thermal stability, and electronic structure of the films are likely to be properly described, the essential details determining the leakage and reliability are easily distorted due to the fact that the conditions of film growth in a research

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lab performing a materials scan are, in general, far from optimal for a given system. Electrical characterization of such films carries a lot of information that useful in future development, but we think that most of its value comes from attempts to estimate the influence of imperfections and from that – to estimate the electrical behaviour of the ideal film, that is, to estimate the intrinsic limits which can be asymptotically approached by process optimization. Finally, we note that a close similarity has been observed in the breakdown characteristics of certain process-induced (“extrinsic”) and wear-out induced failures74. A simple method to detect processinduced defects has recently been described by Suto75.

3. Leakage Instabilities and Dielectric Failure 3.1. Time Dependent Dielectric Breakdown In general, Time Dependent Dielectric Breakdown (TDDB) occurs as randomly generated defects get aligned and form a percolating path connecting the gate and the channel. Currently, there seems to be no consensus on the breakdown model. The reasons for that are manifold, and if one of the most important is that such models are aimed at predicting what happens in the next 10 years. Therefore, the test devices must be overstressed by excessive voltage and temperature in order to accelerate their failure by orders of magnitude. These results must be then extrapolated to device operating conditions. Since there is no comparison with direct breakdown data under these conditions, the extrapolation requires a good knowledge of breakdown mechanism in order to properly include the dependence on the applied voltage (or electric field) and temperature. This is not trivial because there seem to be several competing mechanisms degrading the oxide lifetime. It is easy to extrapolate the wrong mechanism; the result of this extrapolation may be either a severe overestimate or a severe underestimate of the device reliability. The microscopic information needed to properly evaluate the role of each of the breakdown mechanisms seems to be lacking, at least in most cases. Also, the experimental database used for extrapolation may be inadequate. This includes (but is probably not limited to) the case when part of the information is collected from literature. Not all necessary data are published together with the conclusions and there is a danger of taking into account the results obtained under conditions irrelevant to those in the system for which the model is supposed to be applied. Currently, there is an emphasis on empirical models (for an interesting lecture, see Ref. 76), rather than systematic mathematical modelling. This seems to be gradually changing, because mathematical models allow one to analyse the consequences, which a given hypothesis has in the context of changed experimental conditions. For example, if TDDB has polarity asymmetry and the damage increases with the increasing energy of electrons emerging from the oxide after tunnelling, then time to breakdown is smaller in PMOS than in NMOS, or if NBTI is due to relaxation, then it does not depend on frequency. 3.2. Weibull statistic and percolation paths Breakdown events are conveniently characterized by Weibull statistic and described by the percolation model. Neither Weibull statistic nor the percolation model assumes any specific mechanism by which the defects are created. Analysis of experimental data in their terms may reveal correlations (for example, the character of the dependence of Weibull slope on oxide thickness or the lack of such dependence on the stress voltage) which allow subsequent conclusions regarding such mechanisms. Since

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Formally speaking, Weibull statistic17 is solely a result of a mathematical transformation in which the distribution function F (s) describing the probability that an individual from a certain population is characterized by a certain statistical variable S with a value below or equal to s. The distribution function is written as F (s) = 1 – exp (-φ (s)). This is a convenient notation for any “weakest link” problem, that is, when the lack of occurrence of an event is given by the probability that a trigger event does not occur in any of a series of possible cases. For example, a chain does not break when none of the links break, or a dielectric does not fail when it holds on its whole area. The probability of survival is given by the product of survival probabilities of each element, which – given the Weibull transformation – yields the probability of failure equal to 1 – exp (-n φ(s)), a nice scaling with respect to the number n of links (which in the case of dielectric failure is a function of the area of the electrode). The function φ (s) is then assumed to have the simplest form that makes sense, i.e., φ (s) = (s/so). In principle, the only physics behind Weibull statistics is the natural applicability of the latter to a weakest link problem. The Weibull slope  has, in general, no physical meaning as it is solely a parameter of an arbitrarily chosen function which happens to be the simplest one able to approximately represent a broad class of statistical problems. A nice feature of Weibull representation of statistical data, that is, of a plot of W = ln (-ln (1-F (s)) against ln (s) in which a distribution function described by φ (s) = (s/so) takes the form of a straight line with slope , is that when two quite different classes of mechanisms contribute to the failure process, two regimes of x can often be easily distinguished in which  is markedly different. Naturally, there is no guarantee that such a bimodal failure will be revealed by a Weibull plot whenever it takes place, as there is no guarantee that any weakest link problem governed by a single mechanism will yield a straight line on the plot. Nevertheless, the Weibull approach works in an astonishingly broad range of cases and helps to make a practical comparison of relative robustness of physically similar systems (as in comparison of quality of various gate oxides and in reliability prediction, particularly in scaling of the reliability data acquired for test area to the chip gate area) and in analysis of modality of the failure. Another general feature of Weibull statistics is its scaling with the sample size. If the electrode is sizeable enough to encompass so many potential breakdown spots that the number n of links may be treated as proportional to the area A of the electrode, the difference between two Weibull representations W1 and W2 obtained for areas A1 and A2 becomes equal to W1 – W2 = ln (n1/n2) = ln (A1 – A2).

(7)

If no such scaling is found in experiment it means that the weak spots are sparsely distributed over the surface (so that Poisson distribution of weak spots in capacitors must be assumed instead), or that the statistical has been overlaid with fluctuations due to, for example, inhomogeneous film thickness or composition (methods of dealing with such problems have been discussed by Roussel77, and recently by Costa78). Nevertheless, specific problems may introduce more physics into Weibull statistics. Fortunately, this is the case of gate reliability physics, and the Weibull slope can be associated with a physical quantity. The reason for that is that an oxide failure event may be viewed as a case of a percolation event79,80: defects are created or activated more or less randomly in the film until a percolation path of defects connecting both electrodes is formed, at which point a breakdown event occurs. This problem may be treated analytically when the oxide with thickness t ox and area A ox is divided into cubic cells with length a, each of them assumed to have some (uniform) probability to become a defect81 (cf. Fig. 10). If the statistical variable S describes the conversion of an individual cell into a defect, for each cell we have:

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Fig. 10. A sketch of defects randomly generated in the oxide. The diagram on the left is more realistic but requires computer simulation, while the diagram on the right can used to formulate the analytic (but more approximate) model, as discussed in the text. According to Suñé81.

Fcell (s) = s for each cell,

(8)

Fcol (s) = sm for each column of m cells,

(9)

so that and for an area A = M a ² covering M columns the survival distribution functiond R becomes (10) R = (1- Fcol) M = (1- sm) M. Consequently, the Weibull plot will show W = ln (– ln (R)) ≈ ln (M) + m ln (s),

(11)

where we have used the fact that since s is much smaller than one, ln (1- s m) can be approximated as -s m. If we now associate the statistical variable s with the concentration of defects Nd = s / a ³ (the effective defect size a may be viewed as the average distance between defects; this is approximate in the cube model) and cast the survival distribution function R obtained from measured breakdown data on the Weibull plot against ln (Nd), we immediately obtain W = ln (– ln (R)) = ln (M) - 3 ln (a ) + m ln (Nd ).

(12)

In other words, the Weibull slope  is now equal to the number of defects that constitute the shortest percolation path; we can also define the critical defect density NBD as the density Nd at which the Weibull function W = 0, that is, at 63.2% failure rate. Since the Weibull slope  is equal to the number of defects that constitute the shortest percolation path, it is also proportional to the thickness of the oxide and becomes saturated at its lowest value of 1 when only one defect needs to be created in order to short-circuit the dielectric80 (Fig. ). This is a significant conclusion not only because of its consequences for reliability prediction of ultrathin oxides, but also because Weibull slopes of high-k dielectrics may under certain conditions be several times lower than those of SiO2 for the same physical thickness82,83,84,85. Interpreted in terms of the percolation model, this result means that the effective diameter of the single defect in a percolation path is significantly larger in a high-k dielectric than in SiO2. However, the physical meaning of the adjective “effective” requires further analysis, because what is directly measured is not the critical density Nd of defects, but rather time to breakdown or charge to breakdown. The quoted difference between Weibull slopes observed for SiO2 and high-k materials (HfO2, ZrO2, Al2O3) was found from plots against time to breakdown. The problem of measuring this density and relating it to time to breakdown is discussed in the next Section.

d

Precisely, the reliability function yielding the fraction of the population that survives.

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Fig. 11. Simulated dependence of Weibull slope on normalized oxide thickness for trap generation rates with various dependences on the distance from the interface. According to Stathis80.

In summary, the percolation model (also in its analytical form) is in agreement with experimental data from above 10 nm to about 1 nm for a wide range of voltages; this seems to be the case for SiO2 as well as for high-k dielectrics. Reduction of time to breakdown with thickness is observed due to NBD reduction (the number of defects needed to create a percolation path decreases with the physical thickness of the oxide) and to increase in the leakage current. Weibull slopes are essentially independent of stress voltage and temperature. This is consistent with a simple geometric model with NBD being independent of stress conditions:

TBD (t ox , A,V , T ,...) 

N BD (t ox , A) J (V , t ox ) f (V , T ,...)

(13)

As a marginal remark we note here that the percolation formula (12) recovers the natural area scaling: it scales as ln (N), that is, it scales as ln (A ox) if the failure can take place anywhere on the area of the capacitor or if the weak spots where the current or electric field is high and failure is likely occur are densely distributed over this area.

3.3. Defect generation and charge to breakdown In order to make a quantitative physical interpretation of the Weibull slope for time to breakdown, one needs a relationship between the trap density Nd and time. This is a difficult task since the result depends on stress conditions, on sample characteristics and – naturally – on the mechanism of trap generation. However, it can be simply assumed86 for this analysis, that the statistical variable s in Eqs. (8-11) is associated to by the power law to the total charge Q = Jt that has flown across the oxide during time t under stressing current J:

s(t )  so Q  ,

(14)

N d (t )  Q  ,

(15)

or

since we assumed previously that s is related with the concentration Nd of defects through the relation Nd = s /a ³, where a is the effective defect radius. Given Eq. (11), we now obtain

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W = ln (M) + m ln (so) + m α ln (QBD),

(16)

W = ln (M) + m ln (so) + m α ln (J) + m α ln (TBD),

(17)

where M = A/a² is the number of columns and J is the stress current. In other words, when the Weibull function is plotted against time to breakdown, the Weibull slope is scaled by the factor α, that is, is given by t    ox . (18) a This means that if the dependence of the defect concentration on charge to breakdown is superlinear (that is, when the defect formation rate increases as more and more defects are produced), then Weibull slope is larger than the number of defects in the path. Lifetime extrapolated from conditions of artificially enhanced defect creation rate is now better than it would be if the defects were created all the time with the same rate (the case of the simple linear dependence). Conversely, a sublinear dependence of the defect concentration on charge to breakdown (that is, when defect formation slows down as more and more defects are created) means that the Weibull slope is smaller than the number of defects in the path, i.e., the extrapolated lifetime is now worse than it would be in the case of the simple linear dependence. Moreover, computer simulations show that Weibull slope is sensitive to spatial homogeneity of defect creation rate80. If more defects are likely to be created at the interface, then the Weibull slope decreases: its dependence on oxide thickness becomes weaker (Fig. 11). There is also a reliability issue indirectly associated with the presence of PF defects through redistribution and the resulting local enhancement of the electric field in films containing PF defects. Namely, when the stress applied during reliability test approaches the electric fields in which PF emission is high or even saturates due to complete ionization of traps68, the film is likely to develop a space charge due to ionized traps. This means that the electric field distribution becomes inhomogeneous, that is, the electric field is enhanced at the electrode, resulting in a local enhancement of stress. When this effect dominates the reliability characteristics (and indeed, a correlation between the parameters of dielectric breakdown and Poole-Frenkel conductivity has been observed87,88), the predicted lifetime may be underestimated by an unknown factor. 3.4. Hard, soft, and progressive breakdown When the test structure is stressed by a constant voltage (Constant Voltage Stress, CVS), the manifestation of a breakdown event is the sudden increase of the leakage current. When the stress is applied by a constant current source (Constant Current Stress, CCS), breakdown is revealed as a sudden drop in the stress voltage. After hard breakdown (HBD) has occurred, there is an ohmic conducting path connecting the gate and the channel. This path can be characterized by a gate post-breakdown resistance defined as RG = VG / IG (eg.., see Kaczer89). This resistance is such that the current through the gate is several orders of magnitude larger than before the breakdown event. It was found that the magnitude of RG depends on the position of the breakdown along the length of the transistor89; this dependence (observed by Kaczer for SiO2 gate oxides) seems to be a general effect, because it apparently stems from the resistance of the length of the n-doped region in the extension over where the breakdown path was formed. If the breakdown path is located over the channel, RG is more or less constant89.

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Fig. 12. Schematic representation of hard, soft and progressive breakdown modes. After Ribes102.

High stressing voltage (or high supply voltage in older technologies up to about 1990) result in significant current flowing through the oxide as soon as the percolation path shorted the substrate to the gate. The corresponding increase in the local temperature may suffice to produce additional defects around the percolation path, resulting in an unacceptable level of gate leakage. Sometimes the heating was even sufficient to melt the silicon90, completely destroying the transistor. Since the amount of damage depends on the dissipated power, the post-breakdown resistance depends on the area of the gate: the discharged energy is the energy stored in the capacitor. HBD was the dominant mode of breakdown until just about 2000. When the stressing voltage is reduced, HBD becomes less probable, because the short-circuit current (in other words, the dissipated power) is not high enough to melt the silicon or even to form new defects around the percolation path. Under reduced stress (or supply voltage), the gate leakage still increases as the defects are created, and it grows in a sudden step when the percolation path is closed, but this increase is relatively small (sometimes it may even be overlooked if the area of the test device is too large, so that the background current is high; this may lead to inaccurate values of the Weibull slope91) and the dissipated energy does not inflict further local damage. Hence, the post-breakdown resistance is not affected by the level of the leakage current and the postbreakdown current has no systematic dependence on the gate area92,93. The transistor in which such a soft breakdown (SBD) event takes place is still able to operate94. Still, when the transistor is in off state and if SBD occurs near the drain extension, there is a strong increase in Gate-Induced Drain Leakage (GIDL); an increase by five orders of magnitude has been reported94. This increase is caused by charge trapping in the oxide over the overlap region. Although SBD at other locations has a minimal effect on the operation of the transistor, the gate area in modern short-channel transistors is small and the hazardous region may be its considerable fraction, degrading the electrical parameters: a substantial drop of the transconductance and of the saturation current occurs95. Nevertheless, since the transistor does function, it seems to be desirable to investigate the statistics93 of the damage due to SBD and analyse the electrical effects of multiple breakdowns96, so that this information is available to circuit designers. Moreover, at least for some applications, the first breakdown might not always be the best definition of device failure, provided that the postbreakdown gate leakage is not too high. In practice this means that device failure criteria have to be defined at the device level and also at the chip level. Limitations of current supply in the circuit environment can play a relevant role in these criteria. Soft and hard breakdown events are associated (e.g., they have the same Weibull slopes97), but soft breakdown is, in general, not a precursor of a hard breakdown path, as their occurrences are spatially uncorrelated98; also the ratio of soft to hard breakdown events varies with the test area, as it does with stress and with oxide thickness98,99. The actual precursor100 of SBD and of HBD is socalled Progressive Breakdown (PBD), characterized (at least in SiO2 films thinner than about 2.5 nm) by an increase in the noise level101. Figure 12 illustrates these three breakdown modes; they occur in SiO2 as well as in high-k dielectrics102,103,105,104. Interestingly, although PBD and SBD

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events follow Weibull statistics, their Weibull slopes differ102,105, whereby PBD has a smaller slope. Comparing the Weibull slopes to those known for SiO2 analysing the dependence of PBD and SBD slopes on the HfO2/SiO2 stack structure, Ribes102 concludes that PBD is most likely associated with the interface layer, while SBD is linked to the high-k layer. According to an opinion poll conducted during International Integrated Reliability Workshop in 2005, half of the responders used SBD for reliability prediction, and most of them used a critical number of breakdowns on the same transistor as the criterion106. Nevertheless, we should note that the character of breakdown may depend on the gate material107,108; the information on the gate material is not always provided in published papers. As a matter of fact, the introduction of metal gates brought the HBD issue again into the discussion: it seems that whenever a polysilicon gate is substituted by a metal gate, hard breakdown events appear again104,109,110; all this indicates at least that the interaction between the dielectric and the metal cannot be ignored in reliability physics. In addition, the observed Weibull slopes of those HBD events are – surprisingly – dependent on voltage110,111 and also on the area of the test oxide; the latter means that HBD is not Weibull distributed and that reliability predictions based on Weibull statistics of HBD will in this case be wrong. The problem appears because HBD events are difficult to distinguish from some SBD events, so that the obtained breakdown statistics is actually bimodal, and not described by a single Weibull mode. But if the separate events (SBD responsible for the creation of the percolation path and the final HBD) are identified, a correct reliability prediction may be achieved110. 3.5. Stress dependence and prediction of lifetime at device operation Any successful physical model of defect generation must account not only for the fact that TBD depends on the integral charge transported across the oxide (that is, on the product of stressing current and stress time) and for the dependence of the time to breakdown, TBD, on the applied voltage (or electric field); usually, TBD depends also on bias polarity, being much different for pMOSFETs in inversion and for nMOSFETs in inversion. For instance, strong dependence on polarity has been observed112 in TaN/HfO2/SiO2/Si: NBD was about 10 times higher for pMOS (positive gate bias, electrons tunnel from substrate) than for nMOS (negative gate bias, electrons tunnel from gate). Similar results have been reported for nitrided oxide and explained by non-uniform defect distribution under the substrate113,114. As seen from historical perspective, the major controversy between physical models has traditionally been along the division line separating two classes: so-called 1/E class of models and E class of models, where the symbol E stands for the electric field. These names stem from the exponents in the predicted dependence of TBD on the electric field Eox in the dielectric film: E model: 1/E model:

H   Eox , k BT H 1  G( ln(TBD )  ), k BT Eox

ln(TBD ) 

(19) (20)

where ΔH is an activation energy. The symbol G stands originally for the exponent in the generation probability of electron-hole pairs115. This generation probability is proportional to the electron current, which – in Fowler-Nordheim (FN) tunnelling regime – is in turn exponentially proportional to 1/Eox: B ), J  AE ox2 exp(  (21) Eox

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Fig. 13.(Left) Noticeable correlation (R²=0.81) between the field to breakdown and the dielectric constant. (Right) This is recovered by the thermochemical model. After Ref. 122.

where A and B are material-dependent constants (the exact FN formula49 is more complex than that, but retains this 1/Eox dependence to a satisfactory degree). The 1/E dependence thus stems from the exponent in the tunnelling current. At low oxide voltages the linear dependence expressed by the E model appears to be a more exact description of the experimental breakdown data. This dependence is, however, not reproduced in the exponent of the direct tunnelling current. (As a matter of fact, the field dependence revealed by long time stress experiments116 is neither 1/E nor E; on the other hand, the exponential form of the acceleration factor is not exact and a better description of the available data is obtained by a power law117.) The linear dependence on E was recovered in the famous thermo-chemical model118,119, according to which a temperature-independent γ and a field-independent ΔH are due to the presence of weak spots in the oxide (attributed to Si-Si bridges, i.e., fully reconstructed oxygen vacancies) which are transformed into electrically active defects by the combined action of temperature (ΔH / kBT) and electric field (γ Eox). This model was widely accepted, but was later criticized for its inability to account for the experimentally observed fact that different values of TBD can be observed in SiO2 at the same oxide field but at various oxide thicknesses, voltage polarities, and substrate biases120. In response to this critique, the authors re-formulated the model, including a hole-catalysed mechanism, according to which a SiO bond can be broken in the presence of a hole121. It seems that this model does capture some important physics of high-k dielectric failures, as illustrated by its prediction of the trend observed in the breakdown strength of high-k materials122 (Fig. 13). This prediction is founded on the fact that the local electric field seen by a given atom (or defect) in a material depends on the dielectric constant and on the molecular dipole moment that is associated with the atomic structure, while the bond strengths are expected to be proportional to the melting temperature of the material.

4. Point Defects: Their Role in Dielectrics Containing Pr Oxides 4.1. Defect formation energies and parameters that control them Defect formation energies in a compound (and, generally, impurity formation energies) depend on the chemical potentials of the components. In particular, for native defects in Pr oxides we have, for X = (Pr, O): X interstitial: Gf (X I )  Gfo (X I )   (X) ,

(22)

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Fig. 14. Pr oxides. Each O atom (light grey) has four equidistant Pr (dark grey) neighbours.

(Left) Pr2O3, fluorite structure. Each Pr4+ has 8 equidistant O2- neighbours. (Middle) Cubic Pr2O3 is obtained from the fluorite structure by removing every fourth atom in each (001) row of oxygen. Each Pr3+ has six equidistant O2- neighbours. (Right) Hexagonal Pr2O3. Each Pr3+ has six equidistant O2- neighbours and one O2- neighbour at a larger distance. X vacancy: Gf (X I )  Gfo (X I )   (X) , equilibrium with Pr2O3:  (Pr)  1.5 (O)  Gfo (Pr2 O 3 ) ,

(23) (24)

where Gfo (X) is the standard (room temperature, atmospheric pressure) free energy of formation for species X. Since we compute total energies at zero Kelvin, we use for calibration and comparison with experiment the corresponding formation enthalpies rather than free energies. The important regimes of the chemical potential of oxygen are:

1 Pr2O3 in contact with Pr metal:  (O)  Gfo (Pr2 O 3 ) , 3 1 Pr2O3 in contact with SiO2 on Si:  (O)  Gfo (SiO 2 ) , 2 1 Pr2O3 in contact with PrO2:  (O)  2Gfo (PrO 2 )  Gfo (Pr2 O 3 ) , 2 PrO2 in contact with air:  (O)  0 .

(25) (26) (27) (28)

Since point defects are usually charged, we must also consider the dependence of the defect formation energy on the electron chemical potential, that is, on the Fermi energy: positive charge, n  0 : Gf (n , EF )  Gf (n , 0)  n EF ,

(29)

negative charge,  n  0 : Gf (n , EF )  Gf (n , 0)  n EF .

(30)

This means that the formation energy of charged defects in a dielectric in electrical contact with the Si substrate is determined by the position of the Fermi level in the substrate and by the valence band offsets between Si and the dielectric. Since the latter is affected by the electrical dipole moment at the interface between the dielectric and the substrate, the chemical character and electrical quality of the interface may have a noticeable effect on the defect formation energies and, consequently, on the defect population in the dielectric film.

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4.2. Pure Pr oxides: multivalence, native defects, moisture Praseodymium oxide is a rare earth metal oxide, once considered – among other lanthanide oxides – as a potential candidate for high-k replacement of SiO2. It is stable against Si in critical reactions. In oxides, Pr atoms can appear as Pr3+ or Pr4+ oxidation states; the oxidation number is approximately equal to charge state and is associated with the number of 4f electrons: Pr3+ has one f electron, while Pr4+ has none. A typical Pr oxide crystal has the composition of PrOx with 1.5 ≥ x ≥ 2 corresponding to various y = (2-x)/(x-1) in (Pr2O3)y(PrO2)1-y mixture. Three basic structures are known for praseodymium oxide. PrO2 exhibits the cubic calcium fluoride structure (Fig. 14, left). Pr2O3 crystallizes usually in the cubic manganese oxide (or bixbyite) structure (Fig. 14, middle). This structure is based on the calcium fluorite structure, where ¼ of the oxygen atoms have been removed from specific lattice sites. At high temperatures, Pr2O3 exists in the hexagonal lanthanum oxide structure (high temperature phase, Fig. 14, right), which is suitable for epitaxy on Si(111) substrates123. As for the band gap width of Pr2O3, the values reported in literature124 vary from 3.9 eV to 5.6 eV. Ab initio calculations tend to underestimate the gap due to the approximations needed to make the calculation feasible. In the calculations reported in this paper we use the cubic structure of Pr2O3 and the band gap corrected to the value of 5.3 eV measured by us125. A similar correction was applied to the theoretical analysis of Pr silicates and Pr aluminates. We begin with an overview of native point defects in Pr oxides. The computed total energies of defects are the same as reported previously by us126, but the band offset between Si and the topmost non-f valence band of Pr2O3, assumed in Ref. 126 to be equal to 1.3 (i.e., the offset measured to the topmost non-f valence band of Pr2O3 was taken as 1.8 eV), is now set initially to the value of 2.2 eV, as computed125 by ab initio Charge Neutrality Level approach127 with the band gap adjusted to match the experimental value of 5.3 eV. The conditions discussed in Ref. 126 correspond to the situation after the point defect concentration approached equilibrium under the influence of the environment (Si substrate and ambient atmosphere). Against that, the band offset given by CNL approximates the situation when atomically perfect Pr2O3 is brought in contact with atomically perfect Si substrate. The native defects in Pr oxides are oxygen and praseodymium interstitials and vacancies: OV, PrV, OI, and PrI. In addition, valence alternation (VA) defects may be possible in amorphous material or at extended defect sites (grain boundaries, dislocations). Most of these defects usually trap charge, hence their presence in a significant concentration is hazardous. We will discuss the dependence of defect formation energies on the chemical µ(O) of oxygen and on the Fermi level. The chemical potential µ(O) may be viewed as the (total) energy of each oxygen atom that must be added or removed from the film during the chemical reaction of interest. For example, when Pr metal is oxidized to Pr2O3, for each two Pr atoms three oxygen atoms must be taken from some external “reservoir” of atoms, usually from the ambient atmosphere containing O2 molecules. The energy gained in this oxidation process depends on the energy µ(O) of oxygen in the reservoir: it decreases when µ(O) decreases and it reaches zero when oxygen in the reservoir is in equilibrium with PrO2. Conversely, when an oxygen vacancy is created in Pr2O3, oxygen must be returned from the film to the reservoir (usually to a metal overlayer or to the substrate). The energy gain now decreases when µ(O) increases, and such a reaction is unfavourable when oxygen must be returned to the air. The dependence of defect formation energies on the Fermi level is conceptually identical to the dependence on the chemical potential of oxygen; indeed, Fermi level is simply the chemical potential of electrons. In order to satisfy the charge conservation rule, we must always exchange electrons

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Fig. 15. Formation energies of various charge states of isolated oxygen vacancy and oxygen interstitial in Pr2O as a function of the chemical potential of oxygen, µ(O). Valence band offset to Si measured from the topmost occupied non-f state of Pr2O3 is set to 2.7 eV. (Left) The Fermi level corresponds to intrinsic Si. This approximates the unrealistic but illustrative initial condition when atomically perfect Pr2O3 is brought into contact with Si substrate at a temperature typical for MBE growth. (Right) The Fermi level corresponds to the value at which the formation energy of O I2- is zero at the equilibrium between Pr2O3 and PrO2. This approximates the situation when no more oxygen enters from the ambient atmosphere into Pr2O3 protected only by an oxidized (PrO2) layer.

with the reservoir (in which the energy of each electron is equal to the Fermi energy) when we create a charged defect from uncharged components. Therefore, when a positively charged oxygen vacancy is created, we must not only transfer one oxygen atom to the reservoir of oxygen, but also one electron must be moved to the reservoir of electrons. Consequently, the formation energy of the positively charged vacancy increases with the Fermi energy EF, just as it does with the chemical potential µ(O). The dependence of the formation energy on the band offset stems from its dependence on the Fermi energy. The absolute value of the latter is imposed by the substrate, which acts as the electron reservoir. The Fermi energy entering the energy balance in the defect formation reaction is the distance between the absolute Fermi energy and the absolute position of valence band of the film, and precisely this value follows the change of the valence band offset. The discussion that follows is quantitative, but since it involves a number of estimated values, its value is perhaps more of qualitative than quantitative kind. An important issue here is related to the fact that Density Functional Theory calculations severely underestimate the forbidden band gap; in our case, the band gap of Pr2O3 had to be corrected by 1.6 eV. This means that the computed electron transition states in the gap may also have to be corrected. From the analysis of the wave function of OV states in the gap it follows that the energies of electron transition states should be corrected by the same amount as the conduction band125. The formation energies of oxygen vacancies have been adjusted assuming that this approach is the right one. Further, the calculations can provide only a rough estimate of the location of the f-type valence band edge, from which the experimental band gap begins; this adds uncertainty to the band gap correction and, consequently, also to the calculated ideal band offsets. Last but not least, the measured band gap of Pr2O3 may be underestimated; still, there is a wide range of experimentally obtained band gaps of Pr2O3, including values as low as 3.9 eV. The dependence of the defect formation energies on the chemical potential µ(O) of oxygen is given in Fig. 15. The Fermi level in the left panel is aligned with its position in intrinsic Si. Slightly doped

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Si (1016 cm-3) is nearly intrinsic already for temperatures around 300°C, that is, Fig. 15 (left) corresponds to the situation when a perfect Si is brought into contact with a perfect Pr 2O3 at the temperature at which Si is intrinsic. In the right panel, the Fermi level is at the position at which the formation energy of negatively charged oxygen interstitial vanishes on a thermodynamically stable boundary between Pr2O3 and PrO2. (Note that this is an additional approximation, because in reality the transition between Pr2O3 and PrO2 occurs through a complicated series of intermediate oxidation states, and the phase stable at standard conditions is not PrO2, but Pr6O11.) Before we analyze the data in Figure 15, let us first explain the physical conditions described by some regimes of µ(O). The leftmost limit of µ(O) corresponds to the equilibrium between Pr2O3, oxygen and Pr metal. The vertical line labelled SiO2 marks the value of µ(O) at which SiO2 is in equilibrium with Pr2O3, Si, and oxygen. Between these two lines there is equilibrium between oxygen, aluminium (e.g., when Al contact has been deposited on the film) and Pr2O3, while the region extending to approximately 1 eV above the equilibrium with SiO2 corresponds to equilibrium with strained SiOx interfacial layer. At the rightmost end of the scale, Pr2O3 is oxidized to PrO2. Approximately, this is also the value of µ(O) in a vacuum chamber. Zero of µ(O) is set roughly to the chemical potential of oxygen in air. The left panel of Fig. 15 shows that intrinsic silicon does not reduce Pr2O3 by producing oxygen vacancies there, or at least that such a reaction does not happen directly: the formation energy of oxygen vacancy in any charge state is strongly positive (energy loss) when the chemical potential of O is comparable to in SiO2. On the other hand, the formation energy of double negatively charged oxygen interstitial, OI2-, is then negative, meaning that Pr2O3 may decompose SiO2 film grown on Si into silicon (re-grown at the silicon surface) and negatively charged oxygen interstitials, OI2- (injected into the Pr2O3 film) if the temperature is high enough so that the kinetic barriers on the reaction pathway can be overcome. The inserted interstitials are double acceptors; neutral interstitials are stable only if the Fermi level is very close to the valence band of Pr 2O3, and positively charged interstitials are unstable, as typical for this kind of defect in metal oxides128,129. These acceptors build up negative charge, which bends the bands of Pr2O3 upwards, reducing the valence band offset, bringing the Fermi level closer to the valence band of Pr2O3, and making the formation of OI2less and less favourable. Significant injection of the interstitials continues until the energy of the interstitial becomes positive at the end of the strained SiOx regime. This happens when the bands of Pr2O3 move upwards by approximately 0.5 eV. If a dipole moment of this magnitude would be generated across a 1 nm SiO2 interface layer between a poor SiO2/Si interface and oxygen interstitial atoms located in Pr2O3 close to this interfacial layer, it would require the interfacial defect density of about 11013/cm², a concentration about one order of magnitude higher than the interface defect density directly after thermal oxidation of Si. The formation energy of OI2- drops inevitably with increasing µ(O) and is strongly negative in the UHV region. This means that any oxygen molecule from the MBE chamber that is not necessary to oxidize Pr to Pr2O3 and dissociates on the surface of the film will be used to form negatively charged oxygen interstitials. In the right panel of Fig. 15 we depicture the situation corresponding to the case when the surface of the film is either exposed long enough to vacuum with the residual concentration of oxygen in the minimal achievable range, or covered by a surface layer fully oxidized to PrO2 and serving now as the reservoir oxygen at equilibrium with Pr2O3. No more OI2- is inserted in this case when the bands of Pr2O3 move upwards by 1.9 eV with respect to the initial position (defined by the hypothetical band structure obtained by bringing defect-free Pr2O3 and Si together). This corresponds to a negative fixed charge in Pr2O3 equivalent to an interfacial dipole moment of 1.9 eV. If this dipole moment were generated across a 10 nm film with the effective dielectric constant of about 12, it would again require the area defect density of about 11013/cm².

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+ ++

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--

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Fig. 16. Electron transition states of oxygen vacancy and oxygen interstitial in Pr oxides. The black edges of the band diagram of Pr2O3 and PrO2 mark the position of topmost occupied non-f states of the perfect crystal. The dark grey edge in Pr2O3 is the estimated position of the topmost occupied f band, and the light grey edge in PrO2 is the estimated position of the topmost empty f band.

At this moment the formation of oxygen vacancies in the upper part of the film (in the reaction in which an O2 molecule desorbs to the ambient vapour) is, naturally, still unfavourable (Fig. 15, right). But if the oxygen atom released from the lattice site when the vacancy is formed may move to the silicon substrate and oxidize it there, then energy is gained. This can be easily achieved if an oxygen interstitial close to the interface moves into silicon, its neighbour sitting further from the interface moves into its place, and so on, until the last of the interstitials in the chain is replaced by the oxygen atom released from the site at which the vacancy is created. In this way, oxygen is transported from the surface region of Pr2O3 into the Si substrate until both materials are separated by a SiO2 or SiOx interfacial layer that efficiently separates both materials chemically. The reduction of the surface SiO2 layer which may take place in the initial phase of growth thus reverts eventually into substrate oxidation. All this means that any contact to oxygen vapour, even if this is residual oxygen in an UHV chamber, results in oxygen incorporation and creation of significant negative fixed charge in the film. Indeed, even the samples protected in situ from the influence of air by Al gate show negative fixed charge, with the flatland voltage shift of the order of +1 V. Negatively charged Pr vacancies, PrV3-, are also stable at higher µ(O), already under UHV conditions129. In other words, when Pr vacancies are created during deposition, they cannot be annealed out by Post Deposition Annealing (PDA). Their presence may, on the other hand, stabilize the presence of oxygen vacancies, which have the opposite charge state and may also be produced during growth. The computed (ab initio) formation energy of Frenkel pairs in the oxygen sub-lattice of Pr2O3 is low, only 1.7 eV. Although OI and PrV do not introduce deep charge transition levels in the region of the Si band gap nor in the region of about 1 eV above and below, they are multiply charged. As noted in Section 2.4, Coulomb potential binds free charges more strongly in dielectrics than in semiconductors. The binding energy of a carrier trapped by a single charged centre may be tenfold higher than in Si. Since the binding energy increases as the square of the charge Z of the centre, a double (and particularly a triple) charged defect is likely to have "shallow" states which are located close to or even within the energy range of the band gap of Si.

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Pr2O3 - Tgrowth: 200°C 2000 Pr2O3 14 d on air

hydroxide

Pr oxide 1800

Pr2O3 10'700°C vacuum

intensity [cps]

1600 1400 1200 1000 800 600

XPS: O1s

525

-- 532,3 eV

200

-- 529,4 eV

400

530

535

540

energy [eV]

Fig. 18. Moisture adsorption in Pr2O3. (Left). XPS signal from oxygen after exposure to air and after subsequent annealing in UHV. (Right) Atomic configuration of OH groups trapped in Pr2O3 matrix: interstitial (OH)I- and substitutional (OH)O+ . After Ref. 132.

In unbiased Pr2O3 films in contact with Si substrate, OV may exist only as OV2+. But when the Fermi energy (or imref for electrons) increases above the conduction band in Si, that is, when negative voltage is applied to the metal gate, OV may trap electrons on a deep state and change to OV+, OV0, or even OV-. In the latter case, the electron trapped on the vacancy is localized on d orbitals of the neighbouring Pr atom. Figure 16 shows the computed energy position of the corresponding transition states of OV and OI in Pr2O3 and PrO2. When µ(O) approaches that of O2 under atmospheric pressure, Pr2O3 begins to oxidize and the defect energies change. Detailed discussion of native point defects in PrOx and PrO2 is beyond the scope of this paper; it can be found in Ref. 125. Here we only note that from this analysis it follows that the film should remain negatively charged even if it is partially oxidized to PrOx with x increased towards 1.75, i.e., even when the oxide becomes a mixture of the majority component Pr2O3 (with Pr+3 ions) and the minority component PrO2 (with Pr+4 ions). Such a charge, typical for Pr2O3/Si(001) MBE films grown by us, is also consistent with the fact that PrOx crystals are usually130 p-type for x below approximately 1.75. Next, we turn our attention to the problems associated with the chemical activity of the dielectric. As other rare earth oxides131, Pr2O3 readily absorbs water (Fig. 17, left), to the extent that it is easily converted to a hydroxide132,133. The oxide film can be protected against moisture by, for example, a polysilicon capping layer (Fig. 17, right). When the cap thickness is 3 nm, the amount of adsorbed water is reduced tenfold and storage time of about half a year can be guaranteed. Also UHV anneal 6

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uncapped Pr2O3 Si OH SiO2

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M697 2000

15.06.04 ToF-SIMS 2890 Cs 0.7kV, Ar10

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M697 2000

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Fig. 17. SIMS profiles illustrating moisture adsorption in Pr2O3 films grown on Si(001) by MBE. (Left) Uncapped film. (Right) The same film covered by 3 nm of Si before exposure to air.

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reduces the amount of absorbed water (Fig. 18, left). When a water molecule is dissolved in Pr2O3, it dissociates into (OH)I- interstitial and H+. The latter becomes attached to a lattice oxygen atom, forming a defect which may be termed a substitutional OH group, (OH)O+. These defects (Fig. 18, right) do not introduce any "deep", strongly localized states in the gap of Pr2O3 and, since they have the opposite charge, a dissolved H2O molecule cannot act as a fixed charge. Nevertheless, each of the two components is charged and can trap carriers on its hydrogen-like Coulomb state. This means that the presence of adsorbed moisture does lead to states in the gap (“shallow” states) and for that reason contributes to Poole-Frenkel leakage current (the traps are charged when empty). Furthermore, it is possible that defect reactions with moisture affect the charge balance. For example, if the oxygen atom from dissociated H2O oxidizes the silicon substrate, then (OH)I- becomes converted to (OH)O+. Two positive fixed charges are thus created by each H2O molecule. If the overall dipole moment across the film is similar to that suggested by the discussion in the previous Section and caused by the presence of oxygen interstitials, this oxidation by (OH)I- may occur at the interface in a manner analogous to that discussed for the oxidation by OI2-, and with similar energetics. This means that, in principle, one cannot exclude that such processes take place in ultrathin Pr2O3/Si films exposed to moisture. On the other hand, the calculated formation energy of (OH)I- in Pr2O3 is also negative within a broad range of O potential in the oxidizing regime (we assume here that the chemical potential of H corresponds to that in H2O remaining in thermodynamic equilibrium with H, that is, that the sum of 2µ(H) and µ(O) yields the formation energy of water), meaning that water from air would be a source of negative fixed charge in Pr2O3. The formation energy of (OH)O+ is sufficiently small only when the chemical potential of oxygen approaches the UHV range. Although the formation energy of (OH)O+ is negative in equilibrium with SiO2, this does not seem to have a direct relevance to the overall sign of the fixed charge in the film. Still, a noticeable fraction of positively charged defects might be formed in this way if, for example, a watercontaminated oxide is sealed with a Si layer and then annealed. Our experimental data indicate that (OH)- may be incorporated into the interfacial SiOx. Figure 19 compares TEM images taken from two parts of the same sample; one part was exposed to air after deposition, the other part was first sealed with a Si cap and only then removed from the deposition chamber. A bright interfacial layer develops in the uncapped part of the layer. The density of this layer, estimated from XRR, is lower than the density of SiO2, indicating that there are many Si dangling bonds saturated with OH.

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Pr2O3

silicon

interface Pr2O3

Si(001)

5nm interface 5nm

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Fig. 19. Cross-sectional TEM of two portions of the same Pr2O3/Si(001) film after exposition to air. (Left) This part of the film was unprotected. After air exposure, an interfacial layer develops. (Right) This part of the film was protected by Si capping layer. The interface to Si remains sharp.

Last but not least, we consider the issue of multivalence. A characteristic feature of rare earth metal (or lanthanide) atoms is their open 4f shell, a property similar to the open d shell of transition metal atoms. An electrically neutral Pr atom has two 4f electrons. One of these electrons is easily lost, so that Pr-1 ion has only one f electron. The second 4f electron is, however, more strongly bonded and the ion first gives away its two 3s electrons. In Pr-3 charge state, which is the charge state of Pr in Pr2O3, there is thus one 4f electron localized on each Pr atom. These electrons form a narrow hopping band which is completely occupied because of strong correlation effects: if an electron is added, it becomes localized on one of the Pr atoms and the energy of the f orbital strongly increases, so that a wide correlation gap is opened. In spite of its odd number of electrons in the unit cell, Pr2O3 is thus an insulator. (The electronic structure of hexagonal Pr2O3 has been recently computed within the LSDA+U approximation134; LDA data have also been reported135). Oxidation of Pr2O3 to PrO2 removes the single 4f electron from the metal atom altogether: in PrO2, the 4f shell of Pr is empty, so that PrO2 is an insulator as well. Intermediate oxides, e.g., Pr6O11, are mixtures of Pr2O3 and PrO2. Hopping conductivity is therefore possible in this material: f electrons may jump between Pr atoms. Indeed, it is known that the conductivity of PrOx crystals strongly increase when x approaches the intermediate value of 1.75. It is therefore clear that oxidation of Pr2O3 to any higher oxide is detrimental to the dielectric. 4.3. Pr Silicates on Si: silicon, Ti and interface quality While with high-k dielectrics deposited directly on Si one can reduce the gate leakage several orders of magnitude below that for oxynitride dielectrics, the transistor channel mobility is degraded and as a consequence, so is MOSFET performance136. The mobility reduction is caused mainly by a high density of interface states and remote phonon scattering. This can be minimized by separating the high-k layer from the Si substrate by a thin SiO2-based layer137. However, such configuration clearly sets a limit for a minimal achievable EOT. Therefore, to avoid a trade-off between the EOT scaling and the channel carrier mobility, it is important to improve the dielectric constant of the interfacial layer with a minimal impact on the interface state density. Following this approach we prepared compositionally graded Pr silicates using solid state reaction between metallic Pr and thin (~ 2 nm) SiO2 layers on Si(100). The structure of the resulting film (Fig. 20) can be approximately described as a bi-layer composed of a high-k layer acting as a barrier for

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Fig. 20. TEM image of Pr silicate prepared by reaction of metallic Pr with SiO2. After Ref. 138.

tunnelling, and an SiO2-based buffer layer with a moderately increased dielectric constant ensuring a good interface quality138. The preparation procedure includes deposition of a thin Pr metal layer at RT onto SiO 2/Si(100), oxidation in air, and a high temperature (600 – 900°C) annealing in N2 ambient138. We have found that the deposition of Pr under UHV conditions leads to a reduction of SiO2 and formation of Pr silicide, Pr oxide and Pr silicate139. During the subsequent air exposure metallic Pr-Si bonds are oxidized resulting in the formation of a Pr silicate. The annealing in N2 then transforms the residual Pr oxide into a Pr silicate. At the same time, an SiO2-based interface layer is formed between the Si substrate and the Pr silicate layer. The properties of native point defects in Pr2Si2O7 have been discussed on the basis of ab initio pseudopotential DFT-LDA calculations in Refs. 125 and 129. We now summarize the major results of this analysis. A remarkable difference between Pr2O3 and Pr2Si2O7 is that the formation energy of OI-2 is markedly higher in Pr2Si2O7. The reason is similar to that in PrO2: in contrast to Pr2O3, there is no interstitial site in Pr2Si2O7 that is natural for oxygen to fill. Another noteworthy difference between native point defects in Pr2O3 and in Pr2Si2O7 is that a regular oxygen vacancy is not a charged defect in crystalline Pr2Si2O7; nevertheless, the vacancy created by taking away an oxygen atom from between two Si atoms is expected to act as a precursor of the family of defects similar to the E' family in SiO2. When oxygen is removed from a site where it had a Si neighbour and Pr neighbours, a Si dangling bond is formed. The electron captured there comes locally from the metal neighbours and is strongly bound in the electric field of positively charged Pr atoms. It occupies an orbital located about 1 eV below the valence band of Si (given the computed valence band offset between Si and Pr2Si2O7 of 2.7 eV). Typical dangling bond transition states are produced only if an isolated Si dangling bond Si(db) is created far enough from Pr atoms. In general, oxygen vacancies in Pr2Si2O7 are not expected to dissociate into isolated Si(db) dangling bonds. The vacancies may be created when the silicate is in chemical contact with a strongly reducing medium such as Pr or Ti metal layer. An interesting defect having a potential impact on the electrical behaviour of the silicate is an interstitial SiO associated with valence alternation on the oxygen sub-lattice. In SiO2, such defects are denoted as O3+, indicating the over-coordination (3 instead of 2) of the oxygen atom and its donor character. References 125 and 129 use the name Nitrogen Coordinated Oxygen (NcO) for this defect; the abbreviation SiNcO indicates a NcO atom associated with Si dangling bonds. The computed (0/+) electron transition state of SiNcO is approximately one eV above the (0/+) transition state of the free dangling bond; in Pr2Si2O7 films on Si, the latter probably lies above the middle of

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Si band gap. This silicon-related defect, (SiNcO)+, is therefore a Poole-Frenkel centre and a potential TAT centre. If the silicon substrate is oxidized during a post-deposition anneal, the silicate has the ability to steal SiO moieties from the substrate, developing a positive charge in form of (SiNcO)+ and deteriorating its own dielectric quality. There exists a mechanism counter-acting this process: SiNcO may itself be oxidized, producing electrically inactive (SiNcO)O-. On the other hand, the energy gain through oxidation of the substrate to SiO2 is much higher than the energy gain through oxidation of SiNcO and the concentration of surface Si atoms at the interface to the substrate is much higher than SiNcO concentration in the film. Therefore, it is not clear if efficient oxidation of SiNcO is possible without being accompanied by a substantial oxidation of the substrate. A practical problem that we encountered with the silicate stack described above was that although a significant improvement in EOT values without a strong increase of leakage can be achieved by reducing the thickness of the interfacial SiO2-rich Pr silicate layer, the price is an increased interface state density. As a consequence, Pr silicate dielectrics with CET below 1.8 nm and an interface state density of the order of 1011 cm-2 eV-1 are hardly attainable. This is associated with the constrained formation process and properties of the interfacial SiO2-rich Pr silicate layer in the context of the quality of the interface when the substrate is oxidized during epitaxial growth. We confirmed by XPS and TEM that this interfacial layer is formed in the process of Si substrate oxidation and subsequent intermixing of the released SiO2 (SiOx) moieties with the Pr-rich silicate layer. The thickness and the chemical composition of this layer depend strongly on the PDA temperature. While higher annealing temperatures result in a thicker interface layer whose bottom part chemically closely resembles SiO2, PDA at lower temperatures produces a gate stack with a thinner interface layer which has a relatively high concentration of Pr atoms in the direct vicinity of the Si substrate. It is the increased concentration of Pr at the dielectric/Si interface that results in a higher density of interface defects which can not be healed by forming gas annealing (5% H2/N2) as effectively as in case of thicker interface layers (dphys > 1.5 nm). For example, if the film is annealed at 700°C, its CET may be as low as 1.3 nm, but at the cost of completely unacceptable interface state density exceeding 1012 cm-2 eV-1. Analysis of the conductance peak associated with these states shows that the defects are distributed in the interfacial layer with varying distance from the interface. Ti added Pr silicates offer a greater potential for EOT scalability. These dielectric layers prepared by the deposition of a thin metallic Ti layer onto Pr silicate, in-situ annealing under UHV conditions, oxidation and a subsequent annealing in N2 ambient exhibit EOT down to 1.2 nm and interface traps density on the order of ~1011 cm-2 eV-1. The interface trap density is reduced possibly because the presence of Ti in the upper regions of the dielectric promotes the re-growth of a good interface by adsorbing weakly bonded oxygen from the interfacial region and ejecting Si atoms from the silicate, which are transported towards the interface and heal the damaged spots. A certain drawback is that the addition of Ti results in an increase of the leakage current. Nevertheless, the Ti-added Pr silicate layers still have leakage currents 100 times lower than SiON reference films. But a more troublesome and up to now unresolved issue is the thermal stability of these dielectrics. The films are stable only up to ~700°C, which is much worse than the stability of pure Pr silicate dielectric layers140. 4.4. Pr Aluminates on TiN: O vacancies and Ti contamination Pr aluminates have been examined by us in the context of their possible application in MIM trench capacitors for DRAM cells in front-end integration. In this case the critical parameters are: high capacitance density (low EOT), extremely low leakage, and high temperature stability. The oxide was requested to survive for a certain time at nearly 1000°C.

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Fig. 21. Computed transition states of oxygen vacancy and of substitutional Ti in PrAlO3. The band alignment corresponds to that of perfect materials brought into contact (cf. Fig 15, right). TiN work function is assumed as 4.5 eV; the exact value depends on details of the deposition process.

PrAlO3 samples deposited at room temperature are amorphous and remain amorphous after 30 seconds of 900° RTA. RTA of the same duration conducted at 1000°C causes some crystallization, but the XRD peak from the crystalline PrAlO3 is weak. The effective dielectric constant of our amorphous PrAlO3 is insufficient to achieve the requested low leakage at the target EOT. The same samples may be forced to crystallize when they are annealed in conventional oven; unfortunately, this is associated with an unacceptable increase of leakage; the leakage mechanism changes then from Poole-Frenkel to ohmic, but remains defect-related. PrAlO3 thus appears to be an example of the case where the requirements of high dielectric constant and low leakage are contradictory if the processing is far from optimum. This troublesome behaviour may have various physical reasons. If the film begins to crystallize above 700°C, the formation of imperfect crystallites or of grain boundaries between otherwise good-quality crystallites may be responsible for the problem. If the film mixes with the substrate material, titanium contamination may be blamed. Alternatively, macroscopic defects associated with the contamination of TiN surface (cf. Section 2.5) may be at the origin of the observed increase of leakage current after conventional anneal. One might also suppose that – since compounds containing lanthanide oxides have a high affinity to moisture - the annealing process increases the sensitivity of the film to atmospheric influence. However, we have observed just the opposite tendency: after annealing, the film adsorbs moisture less efficiently than before the temperature treatment. This is in accordance with the reported141 behaviour of Y2O3. We did not find any clear-cut correlation between the crystallinity of the film observed by XRD and the leakage current. Moreover, as we mentioned in Section 2.5 (see the discussion of Fig. 9), no spatial correlation between grain boundaries and high leakage current areas was seen in C-AFM images. For that reason we suppose that crystallization itself is not the real source of the observed degradation of the electrical quality of the film. Let us now consider the possibility of titanium contamination. We have observed that Pr-rich samples are generally much leakier than stoichiometric samples. This is not associated with the difference in the tunnelling barrier. The band width (as measured by XPS) of Pr-rich aluminate is smaller by only about 0.5 eV than that of the stoichiometric material. This means that even if the whole band width difference was due to the lowering of the conduction band edge, this would decrease the barrier for electrons from about 2.5 eV (PrAlO3 value) to 2.0 eV, that is, the barrier would still re-

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Fig. 22. Profile evolution of TiO, as obtained by ToF SIMS in a Pr-rich aluminate (Pr1.4Al0.6O3) grown on TiN and subjected to RTA treatment. The distance is measured from the maximum of the TiO peak; the aluminate film is on the left and the TiN substrate layer extends to the right. Squares: the profile of TiO after aluminate deposition at room temperature Circles: the profile after 20 seconds RTA at 900°C. The solid line shows the solution of the diffusion equation with the diffusivities of TiO indicated by the dotted line (arbitrary units). The three regions characterized by various diffusivities correspond to: Pr1.4Al0.6O3 (D1, the highest effective diffusivity of TiO), interfacial layer (D2, intermediate effective diffusivity of TiO) and TiN (the lowest effective diffusivity of TiO).

main high. As a matter of fact, the barrier for electrons is about 2.05 eV in Pr2O3, so one would rather expect that both conduction and valence bands of the aluminate are affected by the addition of Pr2O3 and the barrier in Pr-rich material remains well above 2 eV. Therefore, there is either a significant build-up of positive interfacial charge that produces a dipole moment bringing down the barrier to a very low height at least at some defective spots, or the concentration of defects located in the bulk of the film and promoting leakage increases significantly with the addition of Pr2O3. Can this interfacial charge or these bulk defects be associated with Ti contamination? Results of ab initio calculations indicate that the answer to this question is: yes. Figure 21 shows the computed electron transition states of three defects (oxygen vacancy, Ti substituting Al, and Ti substituting Pr) in crystalline PrAlO3 (space group 167, R -3 2/c). All these defects have transition states in the gap. OV and TiAl are positively charged at Fermi level coinciding with that of TiN. The (0/+) transition state of TiPr is nearly at the TiN Fermi energy. Both substitutional Ti atoms may become negatively charged; of the two, the (-/0) transition state of TiPr is lower in the gap, approximately at the same energy as the (0/+) transition state of TiAl and about 1.4 eV above the Fermi level of TiN. This diagram indicates that titanium – if it is incorporated into the lattice of PrAlO3 – is primarily a donor, although it is intrinsically amphoteric and may also act as an acceptor trap. As we noted by the end of Section 2.4, charged defects in high-k materials are likely to act as Poole-Frankel centres due to strong bonding by electrostatic Coulomb potential there. In order to learn experimentally about Ti diffusivity in Pr aluminates, we have analyzed ToF SIMS (Time of Flight Secondary Ion Spectroscopy) profiles. Below we compare the results for Pr-rich aluminate (Pr1.4Al0.6O3) and for stoichiometric PrAlO3. The SIMS profiles were obtained before and after annealing, and the evolution of TiO profile was simulated by solving the diffusion equation for a single diffusing species (Fig. 22). We estimated the activation energies and the pre-exponential factors from the Arrhenius plot of the diffusion coefficients fitted in this way to the experimental data.

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TiN films oxidize when exposed to an environment containing O2 vapour142. The interface between the aluminate film and the TiN substrate contains oxidized titanium in a high concentration. Figure 22 shows a typical profile evolution of this titanium oxide layer (measured by TiO signal in ToF SIMS) after thermal treatment. It is apparent that there are two regions of different diffusivity in the film. The diffusivity D1 in the body of the film is higher than the diffusivity D2 in the interfacial layer, and the latter exceeds the diffusivity in the substrate, so that nearly all oxidized Ti is transported into the dielectric. The absolute values of D1 and D2 are moderate, in the range 10-14-10-15 cm²/s. They are comparable, for example, with the diffusivity of Si in epitaxial GaAs143. However, the exponential prefactors D01 and D02 obtained from the Arrhenius plot (Fig. 23) are small, on the order of 10-14 cm²/s. Such small prefactors show that the diffusion is not governed by a single diffusing species in either region. Indeed, single species diffusivity D can be represented as:

 E   E  a² exp   a  , D  D0 exp   a    k BT  t jump  k BT 

(31)

where the activation energy Ea is the diffusion barrier and a is the effective jump distance covered in a single jump which happens every time tjump seconds if the barrier Ea is absent. The reverse of tjump is thus the jump attempt frequency f. Assuming jumps of a = 1 nm, we obtain for the measured values of D0 (cf. Fig 23) attempt frequencies close to 1 Hz. This is completely unrealistic: f is expected to be the range of phonon frequencies. Although the experimental uncertainty in the determination of D0 is significant, it is by far not sufficient to explain the missing ten orders of magnitude or more. The small magnitude of D0 reflects the small temperature dependence of the diffusivities, that is, small activation energies of the diffusion itself. According to Fig. 23, the activation energies are 0.5 eV for D1 and 0.3 eV for D2. Such barriers – even if corrected for inaccuracy – would be surprisingly small for diffusion of a TiO particle.

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This type of behaviour is readily explained by defect-mediated diffusion144,145: the diffusing particle cannot move by itself, but needs mobile point defects to move it around. Usually, native interstitials or vacancies act as such diffusion vehicles. The concentration of these vehicles may become supersaturated, particularly after processing associated with lattice damage145 or in low-temperature epitaxial films. For example, MBE Si/Si(001) films may contain about 1017 cm-3 open volume defects146, and about one tenth of them may be single vacancies147. In slightly As-rich GaAs epitaxial layers grown at ~300°C, Ga vacancy concentration may approach148 1019 cm-3. When the vehicles are supersaturated, the activation energy of diffusion becomes equal to the difference between the vehicle diffusion barrier and the particle-vehicle binding energy; this can be a small number. At this point we thus conclude that the diffusion of oxidized Ti appears to be mediated by point defects. These defects are highly supersaturated after deposition, and this saturation is sustained during annealing. According to our ToF (Time of Flight) SIMS data, the diffusivity of oxidized titanium is much smaller in stoichiometric PrAlO3 than in Pr-rich Pr1.4Al0.6O3; hardly any changes are visible in TiO profiles after RTA, even though longer anneals in conventional ovens lead to profile broadening. This observation correlates with the afore-mentioned fact that praseodymium-rich material is leakier than PrAlO3 and with the conclusion from ab initio calculations that substitutional Ti is expected to promote leakage. The detrimental role of titanium in Al2O3 has been reported in literature149. At first glance, this might be viewed as an argument that low yield at high annealing temperatures is caused by Ti contamination. The explanation is, however, not so straightforward. Indeed, even short exposure to high temperature suffices to damage the stoichiometric film electrically, although long exposure is needed for titanium in-diffusion. RTA for 30 seconds at 1000°C does not result in any noticeable broadening of TiO profile into the dielectric, but similar treatments conducted at a much lower temperature of 800°C result in remarkable decrease in the yield, measured as the percentage of capacitors exhibiting excessive leakage. Similar yield losses appear after 800°C anneals in conventional oven. The critical temperature is around 700°C, independently of the anneal method. This means that the leakage does not correlate with the amount of titanium diffused into the bulk of the film, at least when the diffusion occurs by a mechanism similar to that revealed by the above mentioned study. In order to gain more insight into what may happen in the annealed samples, we now return briefly to the analysis of ab initio data. If Ti from a TiO2 moiety of the interfacial oxide substitutes a metal atom in PrAlO3, the reaction products are: a metal atom M (M = Pr or Al) and two oxygen atoms. These products must be somehow accommodated. The metal atom can be oxidized to the oxidation state it has in M2O3; this requires mass transport to the place where there is sufficient room for a new piece of material, and uses 1.5 oxygen atoms per metal atom. The remaining 0.5 of oxygen atom (statistically speaking, of course) is still unused and may be either returned to the reservoir of oxygen (which determines the chemical potential of oxygen) or be built somewhere into the material as a defect or at an already existing defect site. Moreover, when titanium atom substitutes aluminium atom in the film so that TiAl is created, the resulting defect becomes single positively charged (Fig. 21), which means that one electron must be placed on the Fermi level (that is, moved to TiN substrate). The energy balance taking into account all these three effects (oxidation of metal, disposal of remaining oxygen, and disposal of electron) shows that such reactions are not expected to produce TiPr. As for TiAl, its production is energetically favourable when the remaining oxygen fills pre-existing oxygen vacancies. When the oxygen is returned to the MBE chamber (that is, when µ(O) is around -1 eV with respect to standard reference, which is 1 atmosphere partial pressure at room temperature), the formation energy of TiAl+ becomes positive. The magnitude of the formation energy is moderate (about 1.0 eV), provided that the oxidized aluminium that is produced in the process combines with a

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PrO1.5 unit, making a PrAlO3 unit. Formation energy of about 1.0 eV corresponds to the equilibrium concentration of approximately 1017/cm³ defects at 800°C. The conclusion from ab initio results is thus that TiAl donors may be created in substantial quantities either when there is a high concentration of oxygen vacancies in the dielectric, or when the dielectric is Pr-rich (has more Pr2O3 than in stoichiometric PrAlO3). In both cases, the necessary condition is that Ti must be transported (possibly in the form of TiO) to the reaction site, and Al (possibly in form of AlO) must be transported away to the site where it may be used to build a new PrAlO3 unit. Given that Ti transport is difficult in PrAlO3 and that the deposited films are likely to contain a high concentration of oxygen vacancies, one expects that detrimental contamination of PrAlO3 with Ti may occur, but in the chemically and structurally homogeneous regions of the film it should be limited to its interfacial part, where there is a lot of TiO available. Indeed, one observes the presence of positive traps spread within a certain distance in vicinity of the TiN substrate (cf. Fig. 7). Contamination may also take place in those more distant regions of the film, where the stoichiometry deviates towards praseodymium rich. In such regions the transport of TiO is strongly enhanced in comparison to that in stoichiometric PrAlO3, and the formation energy of TiAl+ is lowered. The spread of electrical properties indicates that the most critical hot spots are macroscopic, sparsely distributed over the surface (so that even in a sample that is in average completely useless electrically, one can often find a dot with surprisingly low leakage). On the basis of the above discussion, one can postulate that these hot spots have their origin in the interaction between the TiN substrate and the film. We suspect that at certain macroscopic areas there is a significant build-up of positive interfacial charge due to TiAl+, producing a dipole moment bringing down the barrier locally to a very low height. Alternatively, after deposition there are certain regions, perhaps richer in praseodymium and/or containing a locally higher concentration of open volume defects, where indiffusion of Ti and the formation of TiAl+ is significantly facilitated, so that local leak paths develop after annealing.

5. Nitrogen Incorporation: Influence on Electrical Parameters of HfSiON 5.1. Hafnium-based oxides Hafnium-based oxides such as hafnium silicates and hafnium aluminates have been intensively studied as the most promising alternative gate dielectrics150,151 because of their reasonably high dielectric constants, favourable band alignments to Si(100) resulting in sufficiently high energy barriers for electrons, and relatively good thermal stability. Although the industry is cautious with providing too specific information on new solutions, the material that will be used in first commercial high-k MOSFET announced by Intel in January 2007 (and shortly afterwards also by AMD and IBM) for 45 nm technology node9 would be HfO2/SiO2 or HfSiON/SiO2. In the meantime, the chips are already on the market. Given the stringent industrial specifications concerning such the properties of the film as its suitability to impair diffusion of impurities and oxygen atoms and its thermal stability against crystallization and phase separation during annealing at temperatures as high as about 1100°C in N2 ambience152,153, nitrogen incorporation into Hf silicates and aluminates has recently received much attention. Researches have also reported other welcomed effects of nitrogen incorporation: an increase of the dielectric constant153 and improved overall reliability154. Still, there is a concern that excessive nitrogen incorporation leads to increased gate leakage current and/or fixed charge density. For these

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reasons, controlled nitrogen incorporation into Hf silicates is of great importance to achieve good performance of the transistor. A lot of questions remain open in this context. For example, in order to achieve a quantitative understanding of the leakage current and its mechanism, the impact of nitridation on the energy band alignment between Hf-silicates and Si(100) as well as the defect state density has yet to be studied in detail. In this part of the Chapter we discuss the results of a systematic study of chemical and electronic structures of HfSiOxNy (Hf/(Hf+Si) ≈ 43%) films as a function of nitrogen content. The films were 5 nm thick. In particular, we have used total Photoelectron Yield Spectroscopy (PYS) to evaluate the energy distributions of filled defect states in the dielectric and at the interface. We demonstrate a correlation with the electrical results obtained for HfSiOxNy MOS capacitors with aluminium gate. The electrical characterization was carried out by IV and CV. X-ray Photoelectron Spectroscopy (XPS) of the samples before and after N2 annealing at 1050°C shows that Hf-Nx bonds generated by plasma nitridation are markedly reduced by 1050°C annealing and Si-N bonding units are increased especially at the interface between HfSiOxNy and Si(100). The energy band gap (Eg) of the HfSiOxNy films, determined by analyzing the energy loss spectra of O1s photoelectrons, decreased gradually with increasing nitrogen content. As the nitrogen content increased up to 17.8 at.%, the Eg value was reduced by 1.4 eV. Since a decrease in valence band offset is almost the same as that in Eg, the conduction band offset is almost constant at ~1.5 eV. In our opinion, the reason for this behaviour is that the valence band top of HfSiOxNy is derived from non-bonding N2p states instead of non-bonding O2p states, while the conduction band bottom is built mostly from Hf5d states, independently of nitrogen incorporation. An increase in the defect state density with the N content was evaluated from total PYS. Depth analyses by XPS and PYS measurements indicate that defect states are closely linked to the oxygen deficiency in the near-surface region. For annealed samples with N content exceeding 4.5 at%, an increase of the defect states can be responsible for increased fixed charge density and leakage current (presumably due to the Frenkel-Poole emission). Also, a significant increase in the defect states observed in the sample with an N content of 17.8 at.% may play a role in marked decreases in time-to-soft breakdown and the Weibull slope. 5.2. Experimental Details After standard wet-chemical cleaning steps of 300mm p-Si(100) wafers, ~5nm-thick HfSiOx films with a Hf content of ~43% in Hf/(Hf+Si) were deposited on Si(100) by an atomic layer chemical vapour deposition (ALCVD) method. Subsequently, the nitridation of the films was carried out by microwave-excited plasma using a gas mixture of N2 and Ar, and followed by N2 annealing at 1050°C. The chemical and electronic structures of the samples so prepared was characterized by measuring core line spectra such as Hf4f, Si2p, N1s and O1s and valence band spectra excited by monochromatized AlKα radiation (1486.6 eV: S-XPS). The energy band gaps of the HfSiOxNy layers with different N contents were determined from the analyses of energy loss spectra of O1s photoelectrons measured by hard x-ray photoelectron spectroscopy (H-XPS) excited synchrotron radiation (~6keV) at a beam line of BL47XU in SPring-8 as well as by S-XPS. For each sample, the energy distribution of filled defect states in the dielectric layer was evaluated by total PYS in the photon energy range of 4-6eV. For the depth profiling of the chemical composition and the defect state densities in the dielectric, S-XPS and PYS measurements were conducted repeatedly at each thinning step of the dielectric layer in a dilute HF solution. The experimental details for PYS measurements were described elsewhere155. For electrical characterization, Al gate MOS capacitors were formed by thermal evaporation of Al through a stencil metal mask.

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Fig. 24. (a) Hf4f(7/2), (b) Si2p(3/2), (c) N1, and (d) O1s spectra for ~5 nm thick HfSiOxNy (Hf/(Hf+Si)≈43%,y=020.5 at.%)/Si(100) before N2 annealing at 1050°C. The binding energy was calibrated by the Si2p(3/2) peak at 99.3 eV for the Si(100) substrate and the photoelectron intensity was normalized by the peak intensity of Si2p(3/2) signals from the Si(100) substrate.

5.3. Chemical Composition The chemical binding features in the samples before and just after plasma nitridation, namely in which N2-annealing at 1050°C was not performed, were evaluated from Hf4f(7/2), Si2p(3/2), N1s and O1s spectra as shown in Fig. 24. All the spectra were normalized with Si2p0+(3/2) peak at 99.3eV originating from the Si(100) substrate. With an increase in N content in the dielectric, the chemically-shifted Si2p signals shifted and broadened toward the lower binding energy side while no significant increase in the total intensity was observable. A similar change in the Hf4f spectrum with increasing nitrogen content was observed. In these measurements, the electrostatic potential drop through the dielectrics, if any, was almost unchanged, which was confirmed from no change in C1s binding energy for surface CHx contaminants on the dielectrics. Thus, the observed spectral changes in Si2p and Hf4f are attributed to the formation of Si-N and Hf-N bonding units, that is, a substitution reaction between O and N atoms. Such a substitution reaction is consistent with the fact that a decrease of O1s signals is the same as an increase of N1s signals in consideration of a slightly small escape depth of O1s photoelectrons compared with N1s photoelectrons. From the spectrum analysis of Hf4f signals, it is found that the observed spectra for the samples with N contents of 12.5 and 20.5 at. % consist of four components with the same spectral width as the spectrum of the sample without nitridation but the energy shifts by 0, 0.45, 0.95 and 1.5 eV towards the lower binding energy side from the peak of the sample without nitridation. It is likely that the increase of the binding energy shift is attributable to an increase of the number of coordinate N atoms for one Hf atom. Notice that, in the sample with an N content of 20.5 at%, a percentage of the Hf atom coordinated with three N atoms, is 36.6%, but in contrast only ~1.4% in the sample with an N content of 12.5%. Also, N1s spectra peaked at ~397.5eV contain components at the higher binding energy side, which suggests the formation of N-O bonding units. N1s signals peaked at ~404 eV are attributable to NOx units presumably being trapped in voids in as-deposited films, considering the fact that no such signals were detected for the samples after N2-annealing at 1050°C.

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Fig. 25. (a) Hf4f(7/2), (b) Si2p(3/2), (c) N1s, and (d) O1s spectra for ~5 nm thick HfSiOxNy (Hf/(Hf+Si) ≈ 43%, y = 17.8 at.%)/Si(100) after N2 annealing at 1050°C.

Figure 25 shows the core line spectra for the samples after the N2-annealing at 1050°C. Obviously, the Hf4f signals in the lower binding energy side were decreased markedly by N2-annealing so that the component due to the Hf atom bonded with one or two N atoms became dominant. Even for the annealed sample, in which the N content was decreased from 20.5 to 17.5 at. %, the component originating from the Hf atom with three N atoms was not detected in the Hf4f spectrum. On the other hand, the chemically-shifted Si signals due to nitrogen incorporation were increased by 1050°C annealing and the increment of the Si2p signals was more pronounced for the samples with higher N content. These results indicate preferential attachment of N atoms to Si atoms by annealing in N2, and also imply a nitridation reaction at the interface between the HfSiOxNy and Si substrate, as discussed later, which can be promoted with nitrogen atoms dissociated from Hf-nitride bonds during the N2 anneal. For the sample without N atoms, the narrowing of the Hf4f spectrum and the spectral separation in O1s spectrum caused by the N2 annealing can be interpreted in terms of micro-crystallization accompanied with phase separation as confirmed by TEM observations. To examine the progress on the interfacial reaction by the N2-annaling, the XPS measurements were carried out at each step of wet-chemical etching of the HfSiOxNy layer as shown in Fig. 26. No change in surface micro-roughness by the oxide thinning was confirmed by AFM measurements. With progressive thinning of HfSiOxNy, the chemically-shifted Si2p signals and O1s signals in the higher binding-energy side of the spectrum become dominant as a result of a decrease in main component, indicating the presence of an interfacial silicon oxide layer. For the sample with a nitrogen content of 17.8 at.%, nitrogen incorporation into the interfacial layer was confirmed by a dilute HF

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Fig. 26. (a) Hf4f(7/2), (b) Si2p(3/2), (c) N1s and (d) O1s spectra of 1050°C annealed HfSiOxNy (Hf/(Hf+Si) ≈ 43%,y =17.8 at.%)/Si(100) with progressive oxide thinning by dilute HF etch.

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Fig. 27. Depth profile of the chemical compositions measured for 1050°C annealed HfSiOxNy (Hf/(Hf+Si) ≈ 43%, y = 17.8 at.%) films grown on Si(100).

etching for 45 sec, in which no Hf4f signals were detectable but N1s signals were still observable. In the depth profile of chemical composition determined from the change in the intensity at each thinning step, we found that the oxygen content reaches its minimum at the distance of approximately 1.0 nm from the surface, while the nitrogen content reaches its maximum around a slightly deeper region (within approximately 1.5 nm from the surface), as illustrated by Fig. 27. This result suggests that the surface re-oxidation after nitridation counteracts desorption of nitrogen atoms during the N2 annealing. 5.4. Electronic Properties The width of the energy band gap (Eg) in thin oxide films can be determined from the onset of energy loss signals of O1s photoelectrons156,157,158: the electrons excited from oxygen atoms lose their energy by exciting electron-hole pairs across the band gap, and this is reflected in the XPS spectrum. For hafnium-based oxides, Hf4s core-line signals are superimposed on the energy-loss signals of primary O1s core line signals and make it difficult to determine the onset of intrinsic energy loss signals. To overcome this difficulty, we first determined the Hf4s spectrum by using H-XPS measurements since the ratio of the photoionization cross section of Hf4s core line to that of Hf4f core line is increased significantly with the excitation energy159. Taking into account the energy separation between Hf4s and Hf4f, the Hf4s spectral shape and the intensity ratio of Hf4s to Hf4f signals measured for metal Hf under the AlKα radiation, the Hf4s component was subtracted from the measured spectrum of each sample (Fig. 28a) to obtain the inherent energy loss spectrum (Fig. 28b). And then, in each energy loss spectrum, the onset was defined by linearly extrapolating the segment of maximum negative slope to the background level within an accuracy of 0.1 eV. As a result, we observed that the energy gap, Eg, decreases gradually with increasing nitrogen content in the HfSi-

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Fig. 28. (a) O1s energy loss spectra as directly measured by XPS for a HfSiOxNy film deposited on Si(100) substrate. (b) The same spectra after subtraction of Hf4s contribution from the measured data. The onset of the energy loss signals for each sample can be determined with an accuracy of ±0.05 eV.

OxNy film. The nitrogen content dependence of Eg is the same in samples before and after annealing in N2. The valence band (VB) offset between HfSiOxNy and Si(100) was determined from the analysis of valence band spectra of ultrathin HfSiOxNy films on Si(100) substrates. For this purpose, the measured valence band spectrum of each sample was deconvoluted into two components: the one that originates from the dielectric layer, and the one coming from the Si(100) substrate. In the spectral deconvolution, we used the valence band spectrum obtained in a separate measurement done for hydrogen-terminated Si(100) sample prepared by a wet-chemical process. As shown in Fig. 29, the VB offset value is gradually decreased with increasing nitrogen content in common with the band gap shrinkage. The offset was determined from the energy separation between the tops of the deconvoluted VB spectra.

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Fig. 29. Deconvoluted valence band spectra for the samples shown in Fig. 28, where the photoelectron take-off angle was set at 90º. In the spectral deconvolution, the valence band spectrum separately measured for wet-chemically prepared H-terminated Si(100) was used.

The conduction band (CB) offsets between HfSiOxNy and Si(100) were estimated based on the re-

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Fig. 30. (a) The conduction band and valence band offsets between HfSiOxNy and Si(100) as a function of the N content in HfSiOxNy. (b) Total photoelectron yield spectra for 1050°C annealed samples. Ev denotes the Si valence band top measured from the vacuum level.

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Fig. 31. (a) Total photoelectron yield spectra measured with progressive oxide thinning of the 1050°C annealed sample with an N content of 17.8 at.%. In the oxide thinning, a 0.1% HF solution was used. (b) Depth profiles of filled defect states at different energy positions, which were determined from PYS spectra shown in panel (a) using the same method as described in Ref. 155

sults of Figs. 28 and 29. The values of these offsets are summarized in Fig. 30a as a function of nitrogen content. Since a decrease of valence band offset is almost equal to that of Eg, the conduction band offset remains almost unchanged at ~1.5eV. A similar trend was reported for HfSiOxNy with a Hf contents as high as 60% and 80% prepared by co-sputtering at room temperature, in which the conduction band offsets were derived from the combination between Eg determined by reflection electron energy loss spectroscopy (REELS) for ~100 nm thick films and VB offset by XPS for ~5 nm thick films160. The result shown in Fig. 30a is interpreted in terms that the top states of the valence band of oxynitrides are derived from non-bonding N2p states instead of non-bonding O2p states for oxides and the conduction band bottom is attributed to Hf5d states independently of nitrogen incorporation. The energy distribution of electronic defect states in ultrathin dielectrics and at dielectric/Si(100) interfaces can be evaluated without gate fabrication by total photoelectron yield spectroscopy (PYS) being unconstrained by the leakage current. Figure 30b shows photoelectron yields from the samples after N2 annealing at 1050°C measured as a function of photon energy in the range from 3.9 to 5.9 eV. Since valence electrons in the HfSiOxNy layers can not be emitted by irradiation of photons in this range, the photoelectron yields in the energy region below 5.15eV, corresponding to shallower than the Si VB edge, are attributed to the emission from filled defect states distributed in dielectric layers and at the interfaces. The photoelectron yield, namely defect state density, near the Si VB edge, was increased with the N content up to 8.0 at.% and tend to be saturated in the range of 8.0-12.5%. Notice that, at 17.8 at.%, a dramatic increase in the photoelectron yield was observed. The microcrystallization in the sample without N content may involve in the generation of defects and might be responsible for a large yield in the energy region deeper than the Si VB edge. To gain an insight into the increase in defects with N incorporation, we conducted the PYS measurements repeatedly with progressive thinning of the HfSiOxNy layer (Fig. 31a) and evaluated the depth profile of the defect states (Fig. 31b) by using the same procedure as described in Ref. 155. As shown in Fig. 31a, the photoelectron yield was increased in the early stages of oxide thinning and then decreased with further progressive thinning except that the yield due to valence electrons from the Si substrate became significant with etching longer than 8sec. From the depth profile of the defect states (Fig. 31b) derived from the change in the yield, it is found that the defect state density becomes its maximum in the near-surface region where oxygen deficiency becomes significant as represented in Fig. 27.

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Fig. 32. (a) IV characteristic of 1050°C annealed HfSiOxNy with different N contents, taken at room temperature for capacitors with Al gate. Currents at oxide voltages of 1.0 V and 2.0 V plotted as functions of the N content are shown in the inset. (b) Temperature dependence of the leakage current through 1050°C annealed HfSiOxNy with different N content at an oxide voltage of 2.0 V. Thermal barrier ΦB corresponds to the barrier measured at the oxide voltage of -2.0 V.

From capacitance-voltage characteristics of Al-gate MOS capacitors with HfSiOxNy, it is found that, with increasing N content, negative flat-band voltage shift caused by positive fixed oxide charges becomes significant at a rate of ~10 mV/at.% in the N content ranging from 5.2 to 12.5%, while at 17.8 at% it reaches a value as high as 350 mV. As shown in Fig. 32a, the leakage current flowing through HfSiOxNy from Al gate at room temperature was increased markedly with increasing N content. An increase in the N content by about 6 at% results in the leakage current higher by one order of magnitude (cf. the inset in 32a ). The temperature dependence of the leakage current at a constant oxide voltage shows that the leakage current can be characterized by Poole-Frenkel emission. From the slope of the Arrhenius plot one obtains the energy level of traps responsible for the PF emission at the applied bias asequal to about 0.5 eV, independently of the N content (Fig. 32b); note that the same value is measured in nominally nitrogen-free samples. In addition, time dependent dielectric breakdown (TDDB) characteristics evaluated under constant voltage stress show that time to soft breakdown (tSBD) is reduced with the N content, and that the Weibull slope degrades down to ~1.0 for the sample with a N content of 17.8 at.% although it almost remains unchanged for the samples with N contents of 12.5% and below (Fig. 33). It is likely that pre-existing defects such as fix charges and deep traps play a role in the dielectric breakdown. For the sample with no nitrogen content, microcrystallization may be responsible for relatively short tSBD. In summary, chemical bonding features and electronic states were evaluated from XPS and PYS measurements for ~5 nm thick HfSiOxNy (Hf/(Hf+Si)=43%) on Si(100). The analysis of core line spectra show that Hf-Nx (x≥2) bonding units are generated by plasma nitridation and markedly reduced by 1050°C annealing to form Si-N bonding units together with the oxynitridation of Si(100) substrate. For the annealed sample with the nitrogen content of 17.8%, an oxygen deficient region is formed in the near surface region. The determination of the energy band alignments between HfSiOxNy and Si(100) was demonstrated by combination of the oxide band gap values determined from O1s energy loss spectra and the band offsets obtained from valence band spectra. The PYS analysis shows that, for the annealed samples, the defect state density is increased with the N content and becomes its maximum in the oxygen deficient region. For annealed samples with N content higher than 4.5 at%, fixed charge density and leakage current presumably governed by the FP emission were also increased with increasing the concentration of nitrogen. A significant increase in the de-

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Fig. 33. Time-to-soft breakdown (tSBD) at 63% in cumulative failure and Weibull slope for soft breakdown as functions of the N content in the annealed HfSiOxNy.

fect state density observed in the sample with the nitrogen content of 17.8 at. % is likely to be related to decrease in time-to-soft breakdown and the Weibull slope.

6. Summary and Conclusions We have presented a study of the issues associated with the influence of defects and impurities on electrical quality of high-k dielectrics. Particular attention was paid to the responsibility of defects for leakage currents and reliability deterioration. At the beginning we noted that it is conceivable that a material with quite modest parameters might fulfil technological requirements for most applications - but only if this material were free of defects and a dielectric film completely free of defects is probably impossible to grow. On the other hand, we noted that it is not straightforward to take over the electrical results of materials screening in research labs as directly representing the behaviour of these materials when produced in a fully qualified commercial process. While such parameters as crystallographic structure, chemical and thermal stability, and electronic structure of the films are likely to be properly described, the essential details determining the leakage and reliability are likely to be distorted due to the fact that the conditions of film growth in a research lab performing a materials scan are, in general, far from optimal for a given system. Value of electrical characterization of such films comes mostly from attempts to estimate the influence of imperfections and from that – to estimate the electrical behaviour of the ideal film, that is, the limits which can be asymptotically approached by process optimization. Not only leakage currents but also Weibull slopes may drastically improve during optimization; this strongly indicates that dramatic changes may take place in the film when growth and processing conditions are varied. After browsing through the mechanisms (viewed from statistical and from physical point of view) of gate oxide breakdown in SiO2 and high-k films and after a brief journey into the problems related with Bias Temperature Instability, we listed the similarities and differences between SiO2 and highk gate dielectrics, mostly in the context of reliability concerns. In both materials, dielectric breakdown is a "weakest link" problem. In both, progressive breakdown is the initiator of soft and of hard breakdown, while soft breakdown event does not evolve into hard breakdown event; in this context we noted that distinction between a hard and soft breakdown may be difficult to make but is crucial for a correct lifetime prediction. Further, we recalled that TDDB in SiO2 and in high-k is correlated to charge fluence, but there is also an intriguing correlation to local electric field; this correlation allows one to link breakdown strengths of all (or many) dielectrics. As the next similarity we listed the observation that breakdown often originates in interfacial SiO2, although this is not necessarily

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always as clear-cut as it may seem from some publications. Last but not least, Negative Bias Temperature Instability is an issue in both types of materials, yet it is more complicated in high-k dielectrics, where there may be more behind it than mere creation of defects at the interface by hydrogen release from passivated bonds. Among the differences we listed much smaller Weibull slopes observed for high-k materials. But we noted that this is mostly an effect due to imperfect processing conditions during research phase; when the process is optimized, Weibull slopes increase to the same value as in SiO2 of the same thickness, i.e., become much better than for SiO2 with the same EOT. We also observed that hard breakdowns re-appear in high-k gate stacks. Again, this is not a real difference between high-k and SiO2, but an effect caused by the introduction of metal gate electrodes. A new reliability concern coming together with high-k gate dielectrics is Positive Bias Temperature Instability in nMOSFETs. In HfO2/SiO2 stacks it is associated with the presence of charge traps at energies close to the conduction band of silicon. These traps possibly originate from oxygen vacancies. We argued that although oxygen vacancies are unstable energetically, they are produced together with other defects (e.g., metal vacancies) under non-equilibrium conditions during film growth and cannot be annealed out because these different defects compensate each other electrostatically. As a most pronounced and consequential difference between SiO2 and high-k dielectrics we classified the transient currents which are very marked in high-k but hardly noticeable (under usual conditions) in silicon dioxide. These transient currents are due to the presence of many charge traps in high-k materials and to the layered structure of high-k stacks, where SiO2 interface layer acts as a barrier for trapping and de-trapping of charge. Due to these transient charging effects in high-k materials, the methodologies developed for SiO2 gate oxide characterisation may be not sufficiently accurate when applied to high-k gate oxides. A somewhat trivial remark on the level of simple IV measurements is that one should change the applied voltage stepwise and record the current only after the transient terminates. On a more sophisticated level, the consequence of transient charging is that pulsed measurement methods are recommended. Discussing specific examples from our research we noted that the interaction between the substrate and the film may readily lead to the formation of detrimental defects: point defects as well as extended defects, sometimes of true macroscopic character. This tendency may be enhanced by surface contamination and/or local variations in stoichiometry. We analyzed the microscopic properties (electrical activity and formation energies) of major point defects in three Pr-based dielectrics: in Pr2O3, Pr2Si2O7, and PrAlO3. We found that contamination with oxygen is a major problem in the case of Pr2O3, producing defects which act as charge traps and promote leakage. Although the energy location of oxygen vacancy levels in this material seems to be from the point of view of leakage and BTI less problematic than in HfO2, this does not counter-balance the practical processing problems, which are caused by the detrimental role of oxygen. For the silicate we noted that the fabrication process results in high interface trap density. This can be improved by a technique employing a deposition and subsequent oxidation of a Ti layer on top of the silicate: Ti helps to regrow the interface by gathering oxygen from the poor-quality interface and delivering silicon from the topmost silicate layer there. As for the defect chemistry in Pr2Si2O7/Si(001), we argued that the interaction with the silicon substrate leads to the formation of Poole-Frenkel centres in the form of over-coordinated oxygen (O3+). Finally, we argued that the interaction of PrAlO3/TiN films with the TiN substrate causes the appearance of hot spots, which are possibly associated with the presence of TiAl+ donors. We expect that annealing at temperatures above 700°C produces these donors at a high concentration in vicinity to the interface with TiN and preferably in regions where there is an excess of Pr oxide and a high concentration of open volume defects.

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The last example discussed by us was concerned with the influence of nitrogen on the leakage and reliability of hafnium oxide films grown on Si(001) substrates. We observed that although the conduction band offset (that is, the tunnelling barrier for electrons) is not affected by the nitrogen content and the whole effect of the band gap narrowing is contained in the valence band offset, the leakage current increases exponentially with the amount of incorporated nitrogen atoms, at least in the samples annealed at 1050°C. The measured leakage currents can be described by Poole-Frenkel formula and the effective trap depth is 0.5 eV independently of the nitrogen concentration, that is, they appear to be due to the same process that is active already in nominally nitrogen-free films. In the annealed samples, the defect state density as measured by photoelectron yield spectroscopy increases with the N content and has a maximum in the region deficient in oxygen. A significant increase in the defect state density was observed in the sample with the nitrogen content of 17.8 at.%; this increase is likely to be physically correlated with the observed reliability deterioration: a decrease in time-to-soft breakdown and a decrease of the Weibull slope. Acknowledgments. The authors wish to thank Dr. H. Murakami and Assoc. Prof. S. Higashi for their assistance, and the members of the research project “High-k Net” for their fruitful comments and discussion. Ab initio calculations have been performed on IBM Regatta cluster in Jülich, Germany, in the framework of the NIC project hfo06. Part of this work was supported by the MEGA EPOS project of the BMBF. 1 2

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A. K. Jonscher, Dielectric Relaxation in Solids, (Chelsea Dielectrics Press, London 1983), p. 284. A. K. Jonscher, “Non-Exponential Relaxation In Disordered Systems”, in Structure and Bonding in Noncrystalline Solids, ed. By G. E. Walrafen and A. G. Revesz (Plenum Press 1986) p. 101. H. Reisinger, G. Steinlesberger, S. Jakschik, M. Gutsche, T. Hecht, M. Leonhard, U. Schroder, H. Seidl, D. Schumann, “A comparative study of dielectric relaxation losses in alternative dielectrics”, IEDM Tech. Digest 2001, p. 12.2. S. Manzini and A. Modelli, “Tunneling Discharge of Trapped Holes in Silicon Dioxide”, in Insulating Films on Semiconductors, ed. By J. F. Verweij and D. R. Wolters (Elsevier 1983), p. 112. D. R. Wolters and J. J. van der Schoot, “Kinetics of charge trapping in dielectrics”, J. Appl. Phys. 58, 831 (1985) A. de Polignac and M. Jourdain, “Low frequency dispersion in evaporated silicon oxide films ”, Thin Solid Films 71, 189 (1908); H. Adachi and Y. Shibata, “Asymmetric two-site hopping model for highelectric-field-excited thermally stimulated current in evaporated silicon oxide films”, J. Phys. D: Appl. Phys. 8, 1120 (1975). M. Lenzlinger and E. H. Snow, “Fowler-Nordheim Tunneling into Thermally Grown SiO2”, J. Appl. Phys. 40, 278 (1969). Zhen Xu, L. Pantisano, A. Kerber, R. Degraeve, E. Cartier, S. De Gendt, M. Heyns, G. Groeseneken, “A study of relaxation current in high-k dielectric stacks”, IEEE Trans. ED 51, 402, 2004. H. Kliem, “Dielectric small signal response by protons in amorphous insulators”, IEEE Trans. Electr. Insul. 24, 185 (1989). R. M. Fleming and D. V. Lang,, “Defect dominated charge transport in amorphous Ta2O5 thin films”, J. Appl. Phys. 88, 850 (2000). B. Brar, G. D. Wilk, and A. C. Seabaugh, “Direct extraction of the electron tunnelling effective mass in ultrathin SiO2”, Appl. Phys. Lett. 69, 2728 (1996). J. G. Simmons, “Generalized Formula for the Electric Tunnel Effect between Similar Electrodes Separated by a Thin Insulating Film”, J. Appl. Phys. 34, 1793, (1963). The International Roadmap for Semiconductors, edition 2007, “Process Integration, Devices, and Structures”, pp. 11-14. S. M. Sze, Physics of Semiconductor Devices, 2nd edition (Willey, 1891), p. 403. A. Fissel et al., “Photoemission and ab initio theoretical study of interface and film formation during epitaxial growth and annealing of praseodymium oxide on Si(001)”, J. Appl. Phys. 91, 8986 (2002); J. Osten et al., “High-K Dielectrics: The Example of Pr2O3”, in Predictive Simulation of Semiconductor Processing, ed. by J. Dąbrowski and E. R. Weber (Springer 2004), p. 258. Y.-C. Yeo et al., “Effects of high-k gate dielectric materials on metal and semiconductor gate work functions”, IEEE EDL 23, 342 (2002); Y.-C. Yeo et al., “Metal-dielectric band alignment and its implications for metal gate CMOS technology”, J. Appl. Phys. 92, 7266 (2002). C. K. Maiti, S. K. Samanta, M. K. Bera, and S. Chattopadhyay, “Surface roughness and interface engineering for gate dielectrics on strained layers”, J. Mater. Sci: Mater Electron 17, 711 (2006). J. K. Schaeffer, C. Capasso, L. R. C. Fonseca, S. Samavedam, D. C. Gilmer, Y. Liang, S. Kalpat, B. Adetutu, H.-H. Tseng, Y. Shiho, A. Demkov, R. Hegde, W. J. Taylor, R. Gregory, J. Jiang, E. Luckowski, M. V. Raymond, K. Moore, D. Triyoso, D. Roan, B. E. White Jr, and P. J. Tobin, “Challenges for the integration of metal gate electrodes”, IEDM Tech. Dig. 2004, p. 287. H. Y. Yu, C. Ren, Yee-Chia Yeo, J. F. Kang, X. P. Wang, H. H. H. Ma, Ming-Fu Li, D. S. H. Chan, and D.-L. Kwong, “Fermi Pinning-Induced Thermal Instability of Metal-Gate Work Functions”, IEEE EDL 25, 337 (2004). C. C. Hobbs, L. R. C. Fonseca, A. Knizhnik, V. Dhandapani, S. B. Samavedam, W. J. Taylor, J. M. Grant, L. G. Dip, D. H. Triyoso, R. I. Hegde, D. C. Gilmer, R. Garcia, R. Roan, M. L. Lovejoy, R. S. Rai, E. A. Hebert, Hsing-Huang Tseng, S. G. H. Anderson, B. E. White, and P. J. Tobin, “Fermi-level pinning at the polysilicon/metal oxide interface-Part II”, IEEE Trans. ED 51, 978 (2004). K. Tse and J. Robertson, “Work function control at metal–oxide interfaces in CMOS”, Mater. Science in Semicond. Processing 9, 859 (2006). D. Vouilaume, J. C. Bourgouin and M. Lannoo, “Oxide traps in Si-SiO2 structures characterized by tunnel emission with deep-level transient spectroscopy”, Phys. Rev. B 34, 1171 (1986). H. Lakhdari, D. Vouilaume and J. C. Bourgouin, “Spatial and energetic distribution of Si-SiO2 nearinterface states”, Phys. Rev. B 38, 13124 (1988).

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R. O'Connor, R. Degraeve, B. Kaczer, A. Veloso, G. Hughes, and G. Groeseneken, “Weibull slope and voltage acceleration of ultra-thin (1.1-1.45 nm EOT) oxynitrides”, Microel. Reliability 72, 61 (2004). D. R Lamb, Electrical conduction mechanisms in thin insulating films (Methuen 1967); C. Hamann, Th. Frauenheim, and H. Burghardt, Electrical Conduction Mechanisms in Solids (J. A. Barth, Leipzig 1988). J. Frenkel, “On the theory of electric breakdown of dielectric and. electronic semiconductors”, Phys. Rev. 54, 657 (1938). R. M. Hill, “Poole-Frenkel Conduction in Amorphous Solids”, Phil. Mag. 23 ,59 (1971). J. R. Yeargan and H. L. Taylor, “The Poole-Frenkel Effect with Compensation Present”, J. Appl. Phys. 39, 5600 (1968). V. I. Kold’yaev, “Nonlinear Frenkel and Poole effects”, Phil. Mag. B 79, 331 (1999). R. Ongaro and A. Pillonett, “Generalized Poole-Frenkel (PF) effect with donors distributed in energy”, Rev. Phys. Appl. 24, 1097 (1989). R. Ongaro and A. Pillonnet, “Poole-Frenkel (PF) effect high field saturation”, Rev. Phys. Appl. 24, 1085 (1989). P. C. Arnett and N. Klein, “Poole-Frenkel conduction and the neutral trap”, J. Appl. Phys. 46, 1399 (1975). X. Blasco, J. Pétry, M. Nafría, X. Aymerich, O. Richard, and W. Vandervorst, “C-AFM characterization of the dependence of HfAlOx electrical behaviour on post-deposition annealing temperature”, Microelectron. Eng. 72, 191 (2004). U. Schwalke and Y. Stefanov, “Process integration and nanometer-scale electrical characterization of crystalline high-k gate dielectrics”, Microelectron. Reliab. 45, 790 (2005). M. Lanza, M. Porti, M. Nafria, G. Benstetter, W. Frammelsberger, H. Razinger, E. Lodermeier, G. Jaschke, „Influence of the manufacturing process on the electrical properties of thin (= T / Ts ,

(12)

where TN and TS are given from the reciprocal of the Capacitance matrix [7] as

k BT = (C% )-1 and k BTS = (C%SS )-1 ,

(13)

and the largest term of TN is simply the reciprocal of the electrostatic capacitance or

(

T ≈ e 2 /(k B C ) = 6eV / k B

1/ 3 a

),

(14a)

and

TS ≈ 2(δ + − J ) / k B

a

= 2.8eV / ( k B

a

),

(14b).

Now, recall that the fluctuations from Eq. (13) are purely thermal. The quantum numbers N and S are quantized such that the separation between the neighboring eigenvalues is 1 for both N and S.

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Therefore, when < (

−

o

) 2 > and < ( S − So ) 2 > become of order of unity, that is, when T

becomes of the order of or lower than Eq. (14), the quantum fluctuations dominate over the thermal fluctuations. This completes our analysis for the boundary between the quantum and thermal fluctuation domains on the parameter plane of the magnetic gate. From this boundary, we have the limits on the size for T0= 300K:

) )

a S

≤ (6 eV / k BTo )3 ~ 10

7

or a linear length of 77 nm.

2

≤ 2.8 eV / k BTo ~ 10 or a linear length of 1.6 nm. 10

1

10

0

Feature size, D(nm)

1

5

10

Soft

e,

Q

(~ D

- 1/

75 10

5

10

4

10

3

10

2

3

)

/3 -2

-3

~D

10

a rg

50

)

-2

25

-1

10

(~D e, S

10

-1

Ch

Mod

Fig.8 summarizes the quantitative results and gives the comparison of charge and spin based minimal feature sizes due to fluctuations, illustrating the feature size on top and the total number of atoms for a given device using a spherical gate. The room temperature line is also shown. Clearly the exact geometry of the gate electrode will change the capacitance and also affect the number. In addition, for realistic devices, the gate capacitance will also depend on the dielectric layer. But the number obtained should be close, at least in the order of magnitude. Different materials can be used and there will be different sizes as a result of using different atomic sizes.

T(K)

(

a

T(eV)

(

Room temp. Quantum capacitance effect

M u tua

l ca p a

citan c

e

0

Goldstone mode, S Z(~D )

10

1

10

2

10

3

10

4

10

5

10

6

10

7

10

8

Number of atoms,Na Fig.8: Domains of quantum fluctuations for three quantum numbers: N, S (soft mode), and Sz (Goldstone mode). The curves, TN, TS and TSz separate the areas of quantum (to the left and below) and thermal (to the right and above) behaviors of the corresponding quantum numbers. At 300 K, the fluctuations in magnetic quantum number S give the limiting

The above evaluation of the number of 102 atoms vs. the electronics counterpart of 107 charge-fluctuations based on the atoms. The blue line and arrows indicate the modification of consideration of an isolated spherical the T -line with a more realistic gate geometry. N gate can be improved by turning to a more realistic geometry. The electrostatic gate capacitance should acquire the gate-channel contribution, which is in the plane-geometry limit proportional to the area of the gate ( ∝

2/3 a

).

Accordingly, the TN curve from Fig.8 should shift to the lower-T and smaller-size direction, and its slope becomes steeper, indicating the behavior’s crossover from the linear in length ( T ∝ the linear in surface area ( T ∝

−2 / 3 a

−1/ 3 a

) to

).

Another correction to our simple model should come from the quantum capacitance effect due to the low density of states in semiconductors, which will lower the overall capacitance and shift the curve separating the quantum and thermal regions to the higher lengths (between T ∝

−1/ 3 a

and

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−2 / 3 a

147

lines). Thus the numbers need to be modified as illustrated in Fig. 8.

The physics of the difference of electronics and spintronics comes from the strength of the corresponding interaction, as in this case, exchange interaction. For spintronics, the exchange coupling is a defining factor such that the off-diagonal terms of the C matrix (exchange interaction) are sufficiently large. As a result, the alignment of spins will be in a preferred direction. As a result, the scalable factor and limits will have different geometry dependences. That the spin degree of freedom is more advantageous than the charge degree of freedom from the quantum fluctuation point of view has its origin in the locality of the interaction responsible for the magnetism (exchange interaction). On the energy scale the energy per “quantum unit” scales as 1/R for electronics (Coulomb repulsion), whereas it is size independent for spins (exchange). In the above discussion, we only limit ourselves to electron and spin based devices. For other cases, as in molecules and ferroelectric materials, there will, more or less, be similar geometric dependences of the scaling rules of correlated effects or many-body (collective) effects in nanoscale systems. The above simple analysis is based on a simple structure of a metallic gate. In practice, additional variability may also come from the dopant impurity fluctuations in the semiconductor channel of electronic FET. Since doping density of impurities is no more than 10-3 of the host (Si atomic density 1022 cm-3 and the doping density is of order of 10-19 cm-3) depending on the density of states and the solid solubility of dopants, the fluctuation may become more severe. The dopants, which give rise to carrier fluctuations, will also have a similar effect as the host atoms. The difference will be just the effective capacitance, which will depend on the location of dopants in the channel. This suggests that the use of metallic systems should be better than semiconductor systems since the carrier density of semiconductor systems is lower than that of metals. The fact that we used electrons in semiconductor is for the convenience and the ability to modulate the device by electric field in macro and micro scales. As we scale down further to nanometer and sub nanometer scale, it is obvious that we need higher carrier density, which can be achieved in metallic systems for minimizing the quantum fluctuations. Metallic ferromagnetism appears to be an excellent candidate. In particular, from the quantum fluctuation point of view, the controllability of magnetism may allow us to scale down to much smaller sizes as illustrated in Fig. 8. In the case of dilute magnetic semiconductors, the limit will be close to that of semiconductor electronics as the maximum doping of magnetic impurities will also be limited by the solid solubility. The question of controllability of metallic spintronics materials by electronic field in lieu of current to produce magnetic field, will be an issue. Thus, material research in the area of collective effects, as well as new concepts of controlling ferromagnetism for low power dissipation, will be important for low dissipation spintronics. Because of this, multiferroic materials which will allow for electric field effect to induce magnetic induction, or to afford effectively the electric field control of magnetism is of great interest. Likewise, material related many-body effects such as collective

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tunneling and ferroelectric effects will be important areas.

Minimum Size - Maximum Density. From the above discussion, it is clear that the spintronics has an advantage over conventional electronics in scaling to the ultimate size if the energy dissipation is not the limiting factor as in the case of memory. From Fig. 8, we can conclude that for room temperature operation, we will need to have No be 6x104 atoms (25 nm) for electronics versus 102 atoms (3-10 nm) for spintronics from the quantum fluctuation point of view. (It should be noted that the latter number was put to 10 nm as Tc of ferromagnetism may decrease when the total number of atoms is reduced.). From the energy dissipation point of view, the minimal energy for a single electron as compared with the single collection of correlated spins (nanomagnet) will have the same Landauer limit, kTln 2. If none of energy dissipation and quantum fluctuations were the limit, we could estimate the ultimate density of the electron-based logic devices in semiconductor as follows. We will proceed with a simple electron in a well model. Quantum mechanics immediately gives an answer for the smallest size of the switch possible. For the quantum well in one and two dimensions, there is always a bound state. However, for the quantum well in three dimensions with a finite energy barrier, the existence of the bound state is governed by the relation between the well width a and energy barrier height Ebarrier , and the minimum size of the well for the given barrier height is given by a = π
/(2 2 Ebarrier me ) . (At the minimum size the wave-function is delocalized and the electron spends most of its time outside the well (see Fig.3c), which can probably lead to some undesired (or even unexpectedly benign) features from the technological point of view. For semiconductors the typical energy scale of 1eV and the electron effective mass of meff = 0.2 ⋅ me ; one can estimate the minimal possible well size of 0.3nm. It is reasonable to assume that the minimal size of a device will be 3a. Likewise, the similar argument from the Heisenberg principle gives a =
/ 2mkT ln 2 , which yields 1.3nm (300K). It is reasonable to assume that the minimal size of a device will be 3a and thus the upper bound is about 4 nm per devices. From the energy consideration, assuming 300K and the dissipation energy of 100 Wcm-2, we have a corresponding integration density of 1/ a 2 ~ 4 x1012 devices / cm 2 . The anticipate frequency for the anticipated power dissipation of 100Wcm-2 is about 1 GHz. On the other hand, from the variability point of view, the density will be lower; given the number of (77 nm)3, we will have the density of 1.6x1010 cm-2, a lower density. In this case, the operating speed will depend on the On/Off ratio or the error probability. With the probability of the error of p, the energy dissipation per devices is kTlnp. Thus the functional throughput is: Ftp = P /(kT ln p ) .

For spintronics, we will have the feature size of 1.6 nm close to the energy limit data. That is we can have a potential of the approach the density of 4x1013 cm-2 if the energy issue can be resolved.

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Clearly, for semiconductor electronics, one needs to focus on the variability issue while for metallic spintronics, we need to focus on energy dissipation issue to reduce the energy dissipation in order to further increase the density and functional throughput. From the above discussion, it is clear that in practice spintronics has advantage in scaling to the ultimate size. The practical sizes and the ultimate numbers are listed in Table 1. Likewise, molecular electronics has advantages in scaling as well. For write operation

(

τ store ~ Ptun−1 = exp 2a
−1 2mU b

)

and

for read operation

tsw ~ L m

τ store = e / I off

,

,

Mechanism

Energy (eV)

Ultimate Size (nm3)

Practical Size (nm3)

Electronics

3KT

64 nm3

2x104 nm3

Spintronics

3KT

64 nm3

102~103 nm3

Table 1. Sizes for electronics and spintronics. The ultimate size of electronics was estimated from the quantum mechanical model. The

and

size of spintronics was also estimated from the quantum fluctuations. In practice, for spintronics, the size is limited by the

tsw = L / v = L m /(2U b ) . Clearly the

decrease of Tc due to the finite size effect. It is possible that quantum confinement of carriers may further improve the practical

store time can increase over that of electronic systems by a factor of

( ~(

size by increasing the carrier-mediated exchange interaction.

)

Petun / PMtun = exp aM / ae mM U M / meU e , or the size can be further scaled down by the similar factor: ae / aM

)

mM U M / meU e .

For an atomic mass of say, 20, this factor will be about 200. But this number may not be obtained eventually as the electron tunneling may occur first, in which case the ultimate factor will be however determined by electron tunneling from the molecule to the electrode. Thus the limit will follow the same expression as the electron device case, except that the barrier (U) for electron tunneling will be higher, close to that of ionization energy with the electron mass of close to 1. For logics as in the case of microprocessors and information processing, energy dissipation comes in as a limit earlier than the quantum fluctuations if we continue to use today’s von Neumann architecture in equilibrium. On the other hand, when the density is of primary interest as in the case of memory applications, the fluctuations post an upper bound. From the materials perspective, the variability is more important an issue for memory. Clearly in this aspect, spintronics will be advantageous due to the correlated electron effects forming magnetism to reduce the variability. Molecular devices like spintronics will have advantages from the variability point of view. Indeed the limiting size of the spintronics and molecular systems will share almost the same feature size limit if power dissipation is of little consequence (as in the case of memory and storage devices). From the point of view of nanomaterials, molecules are self assembled and the bond energy usually is quite high, and thus the variability of size variation may be smaller. If the device size is scaled to single molecule, molecules are a good choice from the variability point of view. Self assembly will be the preferred technique to fabricate the device with minimal variability.

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The above argument suggests that we should also study other materials to explore their correlated effects. This will include metallic ferromagnetic materials. For dilute semiconductors, the fluctuation will be larger, since ferromagnetic dopant density is usually 20%. CrossNets: Ultrafast pattern recognition (e.g., face in a large crowd 100 µ s vs 3 hours in µ P ). diffusion barriers of layered structures are of critical importance. For example, low thermal budget processing needs to be developed. On the other hand, for logic device, it will be limited by power dissipation before the feature size reaches the limit of variability.

For nonequilibrium systems, new materials are needed for exploiting many-body effects including ferromagnetism and multiferroics as well as other collective phenomena such as room temperature quantum spin Hall effect for low dissipation mechanisms. However, the latter types of mechanisms may be hard to utilize for the purpose of room temperature information processing. Indeed, most of the symmetry-breaking transitions, such as electron bunching into the Cooper pairs in superconductors, and accompanying appearance of the collective variables (order parameters), happen at low temperatures. For example, even in the so-called high-temperature superconductors the transition temperatures typically does not exceed 100K. For transistors using a molecular channel, the carrier bunching may lead to a reduced swing. When N carriers bunch together in a correlated manner and propagate to the drain, the subthreshold swing can be reduced by the factor of N, very much like the ferroelectric dielectrics discussed before, and the variability will be reduced. Thus molecular switches are of great interest. However, the issue is “Gain”. The gain of molecular switches may come from the two possibilities: one from polarization induced by an electric field, such as ferroelectric molecules, the other will be conformation changes, resulting in negative differential conductance behavior. The negative conductance is seen as energy

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supplied from a source, however.
anoarchitecture and scalability

It is clear that in order to resolve eventually the power dissipation and variability issues on the nanometer scale, one must visit new kinds of information processing architectures other than today’s serial von Neumann’s computer. As discussed above, when the feature size of devices is scaled down, the device current decreases, the number of carriers as well as the current drive is reduced and consequently the variability increases. At the same time, the device density increases and interconnects among those devices become a major issue as discussed above. The increase in interconnects prompts an increase in power dissipation. Likewise, the leakage increases as the size is reduced. Thus new kinds of architectures, specially suited for nanodevices are needed so as to take advantages of the unique features of nanoscale devices but to circumvent the shortcomings of these nanodevices, e.g., variability and small current drive. A fundamental change of information processing may be required or adapted. New architectures have been investigated recently; these architectures take advantages of nearest neighbors or proximity interactions, and aim to minimize long distance interconnects and can incorporate fault tolerance conveniently to form new information processing paradigms. A revisit of architectures such as cellular automata, cellular nonlinear network, cross net molecular computing and eventually quantum computing in the context of using new nanodevices has recently emerged [3, 40-47]. Some of these architectures have been shown to outperform the conventional computer in some specific tasks. As an example, cellular automata (cellular non-linear networks) can be superior for image processing applications. Advanced image vision chips [48-52] are highly desirable in real time high speed vision applications for manufacturing defect detection, defense and security recognition applications. For example, the Ace16K vision chip (hardware) implementation [53, 54] has a 128x128 cell array with a total of 3.7 million transistors (die size of 130mm2) consuming about 4 Watts operating at 32MHz and achieving an equivalent of 6 GIPS [48]. Other CNN based vision chips report up to 1.1GIPS [52] are known to perform significantly better than today’s general purpose computers using the von Neumann’s serial architecture [48, 55]. This new kind of paradigms of nanoarchitectures may be evolved from the trend of today’s multi-core and multi-thread processors in a single chip to eventually cellular blocks; these blocks may be fabricated via self-assembly from nanomaterials or combinations of these. In view of the recent development of multi-core systems, there seems to be a trend to increase the number of cores and at the same time to scale the size of a single core down. From the point of view of materials, we may look at the problem differently. The question is that how many parallel cores one can have. One may anticipate a new scaling law: scaling down the size of each core and scaling up the number of cores. (This will increase Fput or functional throughput.) The number of cores will ultimately approach to that of cellular automata. In addition, the heterogeneous integration of different cores may emerge. Indeed, the integration of different processors and signal processing units (such as graphic processing unit and speech units) has already emerged. The latter will be different from the original von Neumann’s cellular automata concept, which of course will be a subset of heterogeneously integrated systems. From the material point of view, we will need to investigate how to merge different kinds of materials, that is, to develop processing integration of different materials or work to adopting different kinds of materials. As pointed out before, the

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foremost requirement of memory is the density. Thus from the variability point of view (quantum fluctuations), spintronics and molecular memories are preferred. In spintronics, for example, spin torque memory may be used to replace SRAM and even cache memory in the processor. Likewise, cross bar molecular memory may be used to implement memory-intensive architecture such as CMOL [56]. Figures 9a and 9b show an implementation of an CMOL scenario. Such CMOL chip consisting of a CMOS platform in the bottom connecting to a nanoscale cross bar memory array on top will have superior performance in many tasks. While in electronics (electron charge as the state variable), quantum fluctuation is the limit, in contrast thermal fluctuations (including diffusion and others) will need to be considered and addressed in order to achieve the ultimate limit in spintronics. Low temperature processing needs to be developed to minimize the thermal effects of the interface and reliability due to the electro-migration and thermal migration, the latter of which will be important and need to be addressed in order to assure the robustness of the chip in spintronics. For heterogeneous integration, future chips may incorporate different materials such as carbon based material, spin based materials, and others for all sorts of new applications. With nanoscale materials, we may be free from our traditional chip concept of using crystalline substrate. Instead, different nanoscale, high quality crystalline materials may be put on a large area (perhaps flexible) substrate to enable still larger area integration, free from substrate constraints. This coupled with the advancement of bonding may push forward the realization of 3D integrated systems. Fig. 10 illustrates a potential scenario to integrate different CN, CNN & QCN processors together using various materials. The Bio-Inspired CMOL example shows the use of a CPU with several specialized processors in order to increase the total functional throughput. - ., CrossNet

Concluding remarks

Spin Wave Logic V= 0

31

Electron Wavefunction Density

V< 0 P

V< 0

Si

Electron Spin

molecular latching switch

Specialized automata: Games

-+ cell 

 + nanowire

CM OS “soma”

 -

-+ cell 

Image The critical challenges of continuing advances of Speech Power Point, etc. computing and information processing have been identified by ITRS (2007) for scaled CMOS and Fig.10: Heterogeneous integration beyond. Among them, the two stood out. One is scenario incorporating low Power CPU power dissipation due to both static leakage current and other special processors including and dynamic dissipation as discussed before. On one CMOL, FPGA, and spin wave processors. hand, the power dissipation of a single switch is continuously being reduced as the voltage and feature size are reduced. On the other hand, the chip power dissipation remains a major problem due to the increase of device density and operating frequency. The leakage current comes from tunneling through the gate and from the source-to-the-drain. The analysis was clearly based on the fact that the leakage was limited by single particle tunneling based on field effect control of conduction from the source to the drain and the fact that the operation of switches are in equilibrium with the environment (or thermal bath in a thermodynamic terminology). Si

Electron Spin In Ferromagnetic

Spin Wave In Ferrom agnetic

To further reduce the dynamic power dissipation of each scaled transistor, one may need to invoke non-equilibrium physical processes. Logic operation in non-equilibrium will dissipate negligible energy during the operation until the results are read by the outside (ambient). Computing and

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information processing using non-equilibrium physical processes to achieve close to reversible logics may take us to a new horizon of low power dissipation per operation. Such new materials as well as their new properties in exploiting non-equilibrium should be pursued. We need to engage materials research to the feature size of atomic scale related to the following working principles of quantum theory: (1) Quantum mechanical tunneling (2) Many body effects and correlated electron (and other) systems as well as the interface properties (3) Control of atomic scale properties of materials in order to understand, characterize, control and eventually attain high manufacture yield. Thus metrology at the atomic and molecular levels is of critical importance. Clearly, as we work toward to the atomic scale nanosystems, we need to be concerned about the variability issue of different materials. In this chapter, we limited the scope of our discussion to the fundamentals rather than the details of materials processing and technology for making such structures. We discussed the issues of continuously scaling CMOS, including those of source and drain junction depth and control of the doping profile, gate thickness oxide in accordance with the scaling laws of CMOS. Likewise the variability as result of statistical fluctuations of dopants as well as from the ambient or spurious charge will cause a variation of the threshold voltage. The latter was not discussed here as there are abundant literatures already exist. As the number of electrons is further reduced, the variability due to Coulomb self energy will become important, giving rise to added variability. There are three major classes of materials of different state variables: electron charge, collective spin and collective spatial electron coordinates such as molecules. That we discussed only collective electron effect is not a coincidence. Today’s devices do neither allow the use of a single electron spin, nor will it be possible in the near future, especially in solids for room temperature operation. Therefore, collective electron coordinates in either many-electron spin or spatial wavefunctions, may be the preferred state variables alternative to ordinary electron charge. To date, electrons in all electronic devices, including all field effect transistors, CMOS, HMET and Bipolar devices, work independently. The interactions among them are Columbic. There was no significant correlated energy, which can be used or taken into account at room temperature (300K). For spintronics, we show that nanomagnets as a representative of collective effects of spins give lower quantum fluctuations in comparison with today’s electronics systems. Other correlated materials systems will also have the potential of reducing variability by effects such as collective tunneling and molecular conformation changes. In addition, using correlated effects, the leakage current may be further reduced to minimize the overall power dissipation per switch. Other materials such as ferroelectric and multiferroic materials and others will need to be addressed, the latter of which can be used for electric field control of spintronics. From the system’s performance point-of-view, we also need to address nanoarchitectures and its scalability. In particular, we need to minimize the power dissipation and system variability for achieving robust systems using high variability components made in nanometer or atomic scales. We have discussed the recent development of processors. The serial processor is ideal for the

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today’s scaling of the feature size of CMOS. The trend is to use serial processors or multi-cores. The number of cores will continue. We believe that the core size may be further reduced in conjunction with the increase of the number of cores. Materials research using self-assembly will be important to achieve further scaling of cores and for further developing of multi-core systems. We are at the point that we need to explore the different cellular (or a combination of homogeneous and heterogeneous) parallel systems to work in conjunction with the serial processor. In contrast to the serial processors, it will be fruitful to investigate interactions and the proximity effects of nearest neighbors. These new architectures may incorporate different kinds of materials. Most evident is the integration of nanoscale memory to today’s processor in CMOL (CMOS at the Molecular scale) to achieve the high functional throughput.

Acknowledgements: The work was in part supported by Marco Focus Center on Functional Nano Architectonics at UCLA (FENA) and NRI Western Institute of Nanoelectronics (WIN).

n=1/2

1-n=1/2

1-n=0

Appendix. Low temperature operation.

E = −α t In this appendix we demonstrate the concept of the fundamental power dissipation limit in a system of two levels, representing a binary memory unit. The density matrix of the system is a Hermitian 2 × 2 matrix. Neglecting the quantum coherence between the levels, the density matrix is assumed diagonal ρ = diag (n1 , n2 ) ,

n=1

Heat quanta

Fig.11: The graphical representation of Write process in a binary bit. In our simple model the Write process is the shift of the energy of one level down. The occupation numbers (density matrix components) tend to become those of the equilibrium state by the exchange of heat quanta with the reservoir, ths heating it.

with a fixed norm n1 + n2 = 1 , so that the occupation numbers can be given as n = n1 , n2 = 1 − n . In our example, it is only the difference between the energies of the levels what matters, so that without loss of generality the energy of the first level, E, can be reckoned from the energy of the second level, whose energy is thus assumed zero. When the system is at thermal equilibrium with the thermal bath, the occupation number(s) are given by maximum-entropy distribution n0 ( E ) = (1 + e E / kBT )−1 . The control of the system is accomplished by the control of E, E → E (t ) . When E is being varied, the system jumps from one level to the other, thus changing the occupation, n, which, in turn, tends to reach thermal equilibrium with n = n0 ( E ) . The simplest approach to the out-of-equilibrium dynamics of n is through the Liouville (also referred to as master) equation:

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∂t n = −τ 0−1 (n − n0 ( E (t ))) , where

τ0

is

the

characteristic

time

of

the

thermalization.

(A1)

The

solution

is

∞

n(t ) = τ 0−1 ∫ G (t − t ')n0 ( E (t '))dt ' , where G (τ ) = θ (τ ) exp(−τ / τ 0 ) is the Green function of the −∞

homogeneous master equation or

(∂

+ τ 0−1 ) G (τ ) = δ (τ ) . The infinitesimal energy transfer from the

τ

system to the bath due the rearrangement of the occupation of the levels is given as dQ(t ) = − E (t )d (n(t )) and the total heat given away to the bath during the process is:

Q(tinital , t Final ) = − ∫

t final

tinital

E (t )∂ t (n(t ))dt .

(A2)

The process of Writing a bit of information can be mimicked by a simple E-driven evolution of the two-level system under consideration from the equally-occupied-levels state (entropy = kTln2): E = 0 , for t < 0 , n = n0 (0) = 1/ 2

to the pure-quantum–mechanical state; E = −∞ , for

t → +∞, n = n0 ( −∞) = 1 (entropy=0). The integration in Eq. A2 can easily be done with the use of Eq.A1 for the linear sweep of the energy difference E = −α tθ (t ) (see Fig.11):

Q (0, +∞ ) = ατ 0 + kT ln 2 . We see that the minimal energy transferred to the reservoir is achieved by a very slow quasi-equilibrium sweep ( α → 0 ). At this, the first term disappears, whereas the second term of the dissipated power is the fundamental Shannon and Landauer limits: the minimal energy dissipation is determined by the change of the entropy at the initial and the final states. The first term can be considered as a correction, being introduced by that the switch is actually an out-of-equilibrium process ( α is the measure of how fast the out-of-equilibrium process is). The out-of-equilibrium switch requires more work to be done on the system and this additional work eventually dissipates into the heat bath.

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Materials Science Forum Vol. 608 (2009) pp 159-179 © (2009) Trans Tech Publications, Switzerland doi:10.4028/www.scientific.net/MSF.608.159

Organic Materials for Large Area Electronics Richard Friend Cavendish Laboratory, University of Cambridge, CB3 0HE, UK [email protected]

Keywords: Organic semiconductor, FET, LED, photovoltaic diode

Abstract: Organic materials have been developed to operate as the active semiconductor in a wide range of semiconductor devices, including light-emitting diodes, LEDs, field-effect transistors, FETs, and photovoltaic diodes, PVs. The ability to process these materials as thin films over large areas makes possible a range of applications, currently in displays, as LEDs and as active matrix FET arrays, and solar cells. This article reviews developments in semiconductor physics of these materials and in their application in semiconductor devices Introduction: Current semiconductor technology uses inorganic semiconductors that require high temperature processing methods, generally require that devices be constructed within single crystals of semiconductor, and are restricted to small active areas. Though this technology delivers remarkable performance, the restrictions on large-area processing are well-recognised. Large area thin film silicon transistor technology has been built around the use of amorphous silicon-hydrogen alloys that can be deposited by decomposition of silane at temperatures compatible with deposition onto glass substrates. However, there are few inorganic semiconductors that show useful electronic properties when deposited as amorphous structures. Organic materials with semiconducting properties provide an alternative class of materials, and these have now been developed to provide useful large-area semiconductor devices that operate as light-emitting diodes (LEDs) and thin-film Field-Effect Transistors (FETs), and, though less developed, photovoltaic diodes (PVs). Organic molecular semiconductors need to be processed to form uniform thickness thin films, and this is now successfully accomplished in a variety of ways. Vacuum sublimation onto a cold substrate can allow deposition of amorphous films, that, with appropriate choice of molecular structure, can be sufficiently stable against recrystallisation. The pioneering work that set up this approach was due to Tang and co-workers at Kodak [1] who demonstrated that multiple layers of molecular semiconductors could be deposited, and that the heterojunctions between these layers could be used to control device operation, as discussed below. The second approach, as used in the author’s laboratory, is to use materials that are film-forming from solution in common solvents. Polymers, or composites containing polymers are generally required to achieve this, and the development of this class of materials has enabled this solutionprocessing route, starting from the finding of light-emission in polymer semiconductor diodes [2]. The electronic properties of organic molecules with semiconducting properties were first investigated in the 1960s with studies then principally of single crystals of molecules such as anthracene [3], with first measurements of electroluminescence from these crystals reported [4,5]. The ability of these molecular semiconductors to allow electronic transport, and to show charge

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photogeneration in appropriate structures was picked up and developed for use in electrophotography, initially as a replacement for the photoconductive selenium first used by Xerox. It was found possible to incorporate molecular semiconductors that were not directly film-forming within polymer hosts and in this way process the photoconductive layers onto the drum used for image writing and subsequent ink capture and transfer. The vast majority of laser printers and copiers now use these materials systems, and the underlying science is substantially mature, certainly in the context of their industrial application [6]. The current interest in semiconducting organic materials draws both on the developments of the molecular semiconductors used in electrophotography and also from the field of ‘conducting’ πconjugated polymers that started with the discovery of metallic conduction in charge-transfer complexes formed between polyacetylene and oxidising agents such as iodine [7]. The use of organic semiconductors, both molecular and polymeric, as the active materials within conventional semiconductor device structures forms the material for this article. Organic Semiconductor molecular and electronic structures Carbon-based molecular semiconductors have a common structural feature – that the carbon-carbon bonding within the molecule or along the polymer backbone can be described as the alternation of carbon-carbon single bonds and carbon-carbon double bonds. This feature is termed ‘conjugation’ and such materials are commonly described as conjugated polymers or molecules. Carbon-carbon double bonds are formed when carbon is bonded through sp2 hybrid orbitals which result to three covalent σ-bonds within a plane, leaving the out-of-plane pz orbital non-hybridised. Figure 1 shows a range of conjugated molecules and polymers.

N

N

TPD

Pentacene

O

O

S

O N

n

Al 3

n

PEDOT

PPV

AlQ3

Figure 1 Structures of some molecular and polymeric semiconductors. TPD is a holeacceptor/conductor developed for use in electrophotography; pentacene is an example of a crystalforming molecular semiconductor, and is used because it can show relatively high field-effect charge carrier mobility; PEDOT is a derivative of polythiophene, is relatively stable when oxidatively doped and is used as a charge-transfer complex with polystyrene sulphonic acid, PSS, as a (poor) metallic conductor; PPV is an example of a luminescent conjugated polymer that can be used as the emissive material in polymer LEDS; and AlQ3 is a yellow-green emitting electron transporting molecular semiconductor.

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Overlap of this pz orbital with pz orbitals on adjacent carbons allows formation of π-molecular orbitals which are substantially delocalised over the molecule and along segments of the polymer chain. The filled π-bonding orbitals form the valence states, and the empty π*-antibonding orbitals form the conduction states. For the case of molecular semiconductors, charge transport necessarily requires movement of charge between molecules, and this requires adequate overlap of the π-electron systems on adjacent molecules. This is generally achieved for conjugated molecules because the chemical bonding forces the structure to be planar, so that the packing of molecules in the solid state can allow good contact between the π-wavefunctions. A crude measure of this intermolecular π-π contact is the strength of the resonance or transfer integral (within a tight-binding description of the electronic structure), and this is generally of the order of 0.1 eV for well-ordered materials. This can give substantial charge mobility, in spite of a relatively high effective mass. For polymers where the πelectron system is delocalised along the backbone, intra-chain widths for the π valence and π* conduction bands are considerably higher, and values for the transfer integral can reach 1-3 eV. This allows in principle much easier intrachain transport, though in practice inter-chain transport is still required for the usual size range of devices made with these materials. The formation of well-delocalised conduction and valence band states is one of several necessary conditions to obtain useful semiconducting behaviour. It is important to note that the σ ‘single’ bonds formed by the sp2 hybrid orbitals also play an important role: because these are much stronger bonds than those formed with the π electrons they generally keep intact the molecular structure in the presence of excitations of the π electrons. As mentioned above, it is common to prepare organic semiconductors with disordered structures, either as rapidly-cooled vacuum-sublimed films or as solution-processed films, and this lack of structural regularity must clearly affect electronic properties. However, inter-molecular disorder and intra-chain disorder due to chain twists and torsions does not generally cause changes to the covalent intra-molecular bonding, and therefore does not create ‘defect’ electronic states that are associated with dangling bonds or dislocation lines in inorganic semiconductors. Thus, ‘nonbonding’ states within the semiconductor gap are not generally formed. This makes possible very clean interfaces, for example between dissimilar organic semiconductors. Disorder does however affect strongly the transport properties of organic semiconductors, and both charged and neutral excitations can be localised due to disorder. This is a particular problem for organic semiconductors used in FETs where carrier mobility is important. Luminescence and excitons Many molecular semiconductors are highly luminescent, particularly when in dilute solution. The electron and hole generated by photon absorption across the π to π* band gap are unlikely to separate because molecular semiconductors have low dielectric constants, typically around 3, so that screening of Coulomb potentials is relatively weak. In consequence, the Coulomb interaction between the photoexcited electron-hole pair, causes strong binding. The Wannier description of the coulombically-bound electron-hole pair, or exciton, is a useful starting point. Setting the electron and hole effective masses to the free electron mass, and with a dielectric constant of 3, the resultant exciton ‘hydrogenic’ binding energy is about 0.75 eV, and the Bohr radius is 0.3 nm. This is at the limit where the excited state is confined to an individual molecular unit, and is therefore better

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described as a Frenkel rather than Wannier exciton, and this is a reasonable starting point for the description of optically excited neutral states, or excitons. The relatively small size of the exciton has two consequences. Firstly, there is a substantial exchange energy between spin-singlet and spin-triplet exciton configurations. This is comparable in magnitude to the Coulomb binding energy, and is commonly found to be in the range 0.5 to 0.7 eV. In the absence of spin-orbit coupling, radiative emission from the triplet exciton is spinforbidden, and its formation therefore through electron-hole capture in an LED can be detrimental to LED efficiency. The role of triplet excitons in the context of LEDs is discussed later. A second general consequence of localised excited states on molecular semiconductors is the appearance of significant electron-lattice interactions, in the form of vibrational mode coupling to the electronic transitions, in both optical absorption and luminescence. In simple terms, confining the antibonding wavefunction which is produced by moving an electron from a π valence state to a π∗ conduction band state to a small number of carbon-carbon bonds causes substantial rearrangement of the valence electrons so that the bond lengths change in response. For polymer chains which contain phenylene (benzene) units in the chain, the vibrational mode which is coupled is the normally Raman-active ring-stretching mode near 1600 cm-1, and such high energy vibrational modes are often seen as distinct peaks in both absorption and emission measurements.

1.2 1.0

PPV (high structure)

0.8

Absorbance T = 77 K

0.6 0.4 Photoluminescence T = 15 K

0.2 0.0 1.5

2.0

2.5 3.0 Energy (eV)

3.5

Figure 2 Optical absorption and luminescence from a well-ordered film of PPV, showing vibronic structure associated with the phenylene ring stretch mode near 1600 cm-1 as illustrated schematically. Singlet excitons are mobile, moving through Forster dipole-dipole energy transfer. Energy transfer from higher to lower energy sites is responsible for the better-resolved vibronic structure in luminescence than in absorption as shown in figure 2. This disorder does reduce the diffusion range of excitons from values found in single crystals down to about 10 nm for PPV [8]. The exciton diffusion range is important for the operation of PV diodes, as discussed below.

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Excited States – electronic charges Electrons and holes on π* and π states can show moderately high mobilities, though this is very dependent on the nature of the disorder present in the sample. Time of flight carrier mobility measurements on single crystals of naphthalene carried out by Karl et al, [9] show mobilities of around 1 cm2/Vs at room temperature, which rise rapidly as temperature is reduced, to values as high as 300 cm2/Vs at around 10K. Below 100K the temperature dependence follows a T-1.5 law, characteristic of electron-phonon scattering through an acoustic deformation potential, indicating free-carrier like behaviour in this regime. On the other extreme of the spectrum are amorphous organic semiconductors such as molecular glasses and solid solutions of conjugated molecules in inert polymer hosts. The randomness in the molecular positions and orientations leads to strong localization of carriers on individual molecules and transport takes place by hopping from one molecule to the other. The fact that the hopping site in these materials is well-defined makes them model systems for studies of hopping transport [6]. Their mobility is low (typically 10-6-10-3 cm2/V·sec) and shows a Pool-Frenkel dependence on electric field. The absence of grain boundaries and the fact that the amorphous state is not associated with distorted or broken bonds can lead to trap-free charge transport – a key requirement in electrophotography. Another factor that is considered to contribute to charge carrier localisation is that of polaron formation, in which the lattice is locally deformed to receive the excited electronic configuration. In the context of the polymers, the contribution of this electron-lattice interaction to the selflocalisation of electronic excited states has been described in terms of relatively extended excitations of the ground-state π-electron bond order. Su et al showed that the particular bond-order symmetry of the trans-isomer of polyacetylene has the potential to support solitary-wave, or soliton-like excitations [10]. More generally, symmetry considerations allow only ‘polaron’ excitations, for example on the polythiophene and poly(phenylenevinylene) shown in figure 1. In this description, an electronic charge placed on a perfect polymer chain will self-localise to form a polaron. Different measurements do however indicate different levels of self-localisation through this mechanism; experiments which probe the electronic structure of chemically-doped materials (charge transfer complexes with counter-ions present alongside the polymer chain) indicate strong localisation, whereas experiments with field-induced charges indicate much weaker localisation. It is likely that the role of the counter ion present when samples are chemically doped is to increase localisation through the presence of the ionic Coulomb potential. Processing The general requirement for organic semiconductor processing is the production of a thin film of uniform thickness. A secondary requirement is for in-plane patterning, as required for example in the production of red, green and blue subpixels. Much of the interest in these materials has been in finding new ways to process them to form useful structures for semiconductor devices, and several very promising methods have been developed. Processing from the liquid phase, usually from a solution in a non-polar solvent, is particularly appealing, because this is scalable to large areas, and can also allow direct patterning by printing. For molecular semiconductors, solution processing is of limited use, because they often show limited solubility, and do not form continuous thin films, tending instead to crystallise. However,

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some degree of controlled crystallisation can give useful properties for thin-film FET devices, and has been demonstrated with derivatives of pentacene [11,12]. When solution-processed for use in electrophotography, they are dispersed within a polymer matrix [6]. However, vacuum sublimation at relatively modest temperatures, to form high quality thin films, has been very successful. This is particularly because successive deposition of different molecular layers is straightforward, and such heterostructures play a very important role in LED and photovoltaic diode operation. Another virtue is that differential sublimation can be used as an effective purification procedure. Polymers have been particularly developed because they are conveniently processed from solution to form uniform thickness thin films. Solution processing is attractive for several reasons. Firstly, it allows elements of ‘self-assembly’ of one material with respect to another, so that for example, a polymer layer can align onto a pre-ordered substrate (e.g. via a liquid crystalline mesophase), as is desirable for example in FETs. It can also allow complex morphologies with non-planar interfaces between different semiconductors, and one example of this is the use of controlled de-mixing of two polymers deposited from common solution to form an interpenetrating network of the two polymers. This is needed particularly for PV diodes, as discussed below, where light needs to be absorbed throughout the thickness of the absorbing semiconductor layer but also be absorbed close to the heterojunction between electron- and hole-accepting semiconductors so that charge separation can occur. Most of the potentially useful applications for organic semiconductor devices also require in-plane patterning. This is the case for full-colour LED displays where separate red, green and blue subpixels need to be defined, but is also the case for transistor circuits where each transistor needs to be formed from a single area of organic semiconductor in order to avoid cross-talk between adjacent devices. There has therefore been great interest in the use of direct printing of semiconducting or doped conducting polymers and this can realised by their formulation as ‘inks’ (selection of viscosity and surface tension), so as to be compatible with convenient printing methods. Ink-jet printing has been particularly popular. However, ink-jetted drops as produced by current generation ink-jet print heads have volumes of a few picolitres, and diameters of more than 10 μm. This is adequate for patterning of sub-pixels for LEDs, but not generally useful for defining structures such as FET channels [13]. However, by pre-patterning the surface free energy of the substrate (using techniques such as micro-contact printing) it is possible to steer the flow of the fluid droplet deposited by ink-jet printing, so that its eventual position is very accurately determined.

Figure 3 Optical micrograph of two ink-jet printed lines of the conducting polymer composition PEDOT-PSS. The first line to be printed is surface-treated to repel the second line as it is printed, and the resulting structure can be used as the source and drain of an FET. The effective channel length between the two conducting lines for this structure was found to be below 100 nm [14].

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A further approach that allows the patterning of very narrow channels between source and drain of an FET is to arrange that the first electrode (printed as a line of droplets from the polymeric metal PEDOT-PSS in aqueous solution) is printed, dried and then rendered hydrophobic (by for example treatment in a CF4 plasma) and the second electrode then printed nearby. As the printed drops spread and reach the first structure they are prevented from wetting and a well-defined channel is set up between the two conducting lines, as shown in figure 3. The channel length between these two electrodes can be arranged to be below 100 nm[14]. Lateral patterning of organic semiconductors deposited by vacuum sublimation is not so easy to achieve. Shadow masking has been used extensively but, as a manufacturable technique, suffers from accumulation of material on the mask. There are many proposals in the literature, including the use of ‘dye sublimation’ as used in some forms of colour photography printing. One recentlyreported approach that shows promise is the use of a gas transporting agent to direct a flow of semiconductor molecules sublimed into the gas flow, and directed through a small nozzle onto the substrate [15]. Light-Emitting Diodes Diode structures can be manufactured by successive deposition of organic and inorganic layers, both by vacuum sublimation of molecular semiconductors [1] and by solution processing (spincoating or printing) of polymers [16]. Many very simple diode structures are now known to function as LEDs, and efficiencies, durability and colour control have now brought these devices to consumer products as light-emitting pixelated displays. O

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Figure 4 Structure of simple polymer LED devices: (a) the LED is formed by spin-coating of a solution of the semiconducting polymer, here shown as PPV, onto the anode formed as a layer of transparent indium-tin oxide. The top electrode is then formed by thermal evaporation of a low work-function metal such as calcium onto the semiconductor layer. (b) energy level scheme for a diode formed with a layer of the conducting polymer composition PEDOT-PSS spin-coated onto the indium-tin oxide layer. This acts to improve injection of holes from the ITO into the π valence band of the semiconducting polymer. Electrons are injected from the low workfunction electrode, shown here as calcium, into the π* conduction band states.

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These LEDs operate through electron and hole injection from opposite electrodes, electron-hole capture within the bulk of the semiconductor film to form bound excitons, and subsequent radiative emission from the exciton. That these devices work at all, let alone very efficiently, has come as a surprise. The organic semiconductor layers are generally very thin (total thickness of around 100 nm), and interfaces between these and the two inorganic electrodes might be expected to be very troublesome. Indium-tin oxide on a transparent support substrate (usually glass, but also polymer substrates) is generally used as the bottom, hole-injecting electrode. Although it has a high work function, as required for hole injection into the valence band states of the organic semiconductor, it is often coated with a more predictable hole-injecting layer, such as the conducting polymer formulation PEDOT:PSS which is conveniently water soluble. Low work function metals are required for electron injection, and metals such as calcium or magnesium (often alloyed) are widely used. The scheme of energy levels for this model of operation is shown schematically in figure 4(b), in which we have not attempted to modify electrode – semiconductor interfaces to take account of the interfacial interactions. This crude model is moderately successful because the interfacial chemistry at both electrodes is relatively benign, in that it does not introduce ‘broken bonds’ with energy states deep in the semiconductor gap, but in detail, this has proved to be a very rich area of investigation of both chemical reactions and charge polarisation at interfaces. Photoelectron spectroscopy has proved to be a very powerful technique, and has revealed that in spite of significant interfacial chemistry, this picture is moderately successful [17]. However, interfacial dipoles can certainly be present, and for example, it is generally found that there is a reduction in effective work function for high workfunction metals such as Au due to dipole formation at the interface [18].

Energy

TPD

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Figure 5 Heterostructure LED formed with two semiconductor layers with different electronegativities. Holes injected from the anode into the hole transport layer (here shown as TPD) are trapped at the heterojunction formed with the more electronegative AlQ3 layer, and electrons injected into the AlQ3 layer are similarly trapped as they reach the heterojunction. Electron-hole capture is therefore arranged to take place at the heterojunction. For TPD-AlQ3 the exciton forms in the AlQ3 layer because this has the lower bandgap. Most of the more effective LED structures make use of at least one heterojunction between different organic semiconductors, because this can be used to control and balance electron and hole currents, and the electron-hole recombination zone. This was first shown to be effective in a seminal paper from Tang et al. in 1987 [1], who used vacuum sublimation of a hole-transporting material similar to TPD onto an indium-tin oxide anode, followed by a layer of electron-transporting Alq3 (see figure 1 for molecular structures), and with a cathode of magnesium-silver alloy. The heterojunction is of ‘type II’, with both conduction and valence bands of the Alq3 displaced to lower

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energies with respect to those of the TPD, with an arrangement of energies as shown in the scheme in figure 5. Both holes and electrons are blocked by the band-edge offsets at the heterojunction, so that electron-hole capture is confined close to this region. These architectures also operate with single layers of blended polymers, and these also can operate with reasonable efficiency, above 20 lumen/W in the green part of the visible spectrum [19]. The role of triplet excitons in LED operation is very important. As discussed above, triplet excitons are generally 0.5 to 0.7 eV lower in energy than the corresponding singlet, as is illustrated in figure 6, and once formed are unlikely to decay radiatively for the simple hydrocarbon organic semiconductors generally used. Assuming that electron-hole capture is spin-independent, only 1 in 4 of the capture events will produce a singlet, and if the other 3 triplet excitons are non-emissive, this is a severe limitation to efficiency. The achievable quantum efficiency for an organic LED that emits from spin singlet excitons is determined by this and a number of other factors, often expressed as ,

(1)

where η is the efficiency (photons out per electron injected), q is the photoluminescence efficiency, γ is the fraction of injected electrons and holes that recombine to form an exciton within the emissive semiconductor layer, rst is the fraction of excitons that are formed as spin-singlets, and fout is the fraction of the light generated within the device that is able to leave it in the forward direction. The value of q for π-conjugated molecules can be very high for isolated molecules as in solution, but is often considerably reduced in solid structures where intermolecular interactions can cause the exciton to become non-emissive. This is usually described as the delocalisation of the exciton across a pair of molecules (or polymer chains) where, in general, the lowest energy state has the transition dipole moment oppositely oriented on the two molecules, causing cancellation of the dipolar radiative transition (the so-called H aggregate). Another cause of loss of luminescence is the rapid motion of the exciton by Forster transfer to a local defect that acts as a quenching site. There has been very considerable progress made in the improvement of materials purity and in the design of molecular structures that are not susceptible to becoming non-emissive, so that values for the singlet luminescence efficiency above 80% are reported. One interesting aspect to the challenge of materials design is that large molecules, such as polymers, support larger exciton wavefunctions and these show weaker cancellation of the dipolar radiative transitions and can therefore be efficient emitters without dilution [20]. The value for γ is set by the diode architecture, and is considered to be close to 100% for devices that incorporate at least one heterojunction between semiconductors of the type shown in figure 5, and for which the barriers for injection of electrons and holes from their respective electrodes are sufficiently low. The optical out-coupling, fout presents a more serious limitation. Refraction of light from a higher index to lower index medium (from device to air) considerably restricts the solid angle of emission within the device from which light is emitted in the forward direction, in simple models to perhaps 25% of the whole. Though this is less serious problem than is the case for inorganic semiconductor LEDs where refractive indices are high (the organic semiconductors generally show values for refractive index of less than 2), it is difficult to couple light out efficiently and this does represent a significant loss mechanism.

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The management of spin triplet excitons has proved to be a very fruitful area for development. Very substantial improvements to device efficiency have resulted from the work of Forrest, Thompson et al., who showed that incorporating an organometallic complex which can act as the emissive site and which has substantial spin-orbit coupling can allow both singlet and triplet excitons to emit radiatively [21]. Complexes with iridium, as shown in figure 6 below, have been particularly successful for this purpose. These show relatively fast radiative transition rates from the T1 state to the S0 ground state, with lifetimes of a few μsecs. These are generally included as dilute components within vacuum-sublimed molecular semiconductor layers.

Tn S1

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intersystem crossing

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singlet emission

Ir triplet emission

N

3

S0 Figure 6 State energy diagram for singlet and triplet excitons. The inset shows the chemical structure for an iridium complex which shows efficient triplet luminescence (phosphorescence) when used as the emissive material in an LED structure [21]. Through this approach, very high efficiencies have been reported, particularly from industrial groups. For example, Novaled have claimed power efficiency for a green OLED greater than 120 lm/W at 1,000 cd/m2[22]. Inclusion of dilute quantities of triplet-emitting materials in solutionprocessed layers comprising polymers has been achieved by adding side-chains to improve solubility and to discourage aggregation and crystallisation, and excellent results have been achieved using iridium-containing dendrimers [23]. There is tantalising but confusing evidence that the simple model for spin-independent electron-hole recombination may not be sufficient, and that, in LEDs, spin-singlet formation may be preferred over triplet formation, leading to higher values for rst up to and above 60%. Evidence comes from a range of measurements including optically-detected magnetic resonance [24], through direct triplet emission in polymers containing platinum within the conjugated polymer chain [25], and through measurements and modelling of the efficiency of singlet emission, where the Philips group reported that modified anodes can allow very efficient singlet-emitting devices, with 35 cd/A for green emission, and an estimated singlet fraction of at least 60% [26]. (Other techniques for measuring the singlet exciton fraction, however, do not show values above 25% [27].) That there may be spindependent electron-hole capture is not unreasonable - singlet and triplet excitons on polymer chains have very different spatial wavefunctions, the former well delocalised and the latter more localised, and it is likely that these different sizes and their different energies play a determining role in the process of electron-hole capture, with the more delocalised singlet exciton being closer in energy to the electron-hole pair than the triplet, as can be described using the framework of Marcus theory [28] more accessible from the relatively delocalised electron and hole wavefunctions.

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There is one further factor beyond those indicated in equation (1) that determines the energy efficiency, ηenergy of the LED – the operational voltage, V. ,

(2)

where is the photon energy of the emitted photon. It is clearly desirable to drive LEDs at voltages V close to , and this requires that there are very low barriers for injection of electrons and holes from anode and cathode respectively. There has been a very large amount of work carried out to improve these processes, and operational voltages at useful levels of light output have now been reduced to be close to . At the anode, the doped conducting polymer PEDOT-PSS has proved very effective for polymer-based diodes, and it is possible that there is some movement of the counter-ions present on the PSS chains into the semiconducting layer, to produce some degree of local ‘doping’ of this layer, thus allowing screening of barriers for charge injection. Very substantial improvements have been achieved by controlled chemical doping of sublimed molecular layers using molecular dopants that remain immobile in the sublimed layer (this is generally not easy to achieve for organic semiconductors). Leo et al. have used electron acceptors such a fluorinated TCNQ to achieve p-type doping [29], and this reduction in operating voltage has been instrumental in the demonstration of the highest efficiencies. The cathode also requires careful design, and generally, low workfunction metals with very thin (monolayer) coverage with typically LiF have proved effective, for reasons that are not entirely clear. LED emission colour is of course determined by the optical energy gap of the emissive semiconductor. Colour tuning by chemical design has been extensively developed, and many of the better materials have been produced within industry, where their chemical structure is not generally disclosed. Though colour is easy enough to tune across the visible spectrum, both ends of the spectrum present difficulties. Red is often difficult to produce because red-emitting fluorescent materials often show low luminescence efficiencies. This is probably due to the relatively high rate of non-radiative decay via multiple emission of vibrational quanta associated with high frequency modes such as C-H stretch near 3300 cm-1. Many of the more efficient red emitters turn out to be triplet rather than singlet emitters, and it is convenient to select materials where the red-shift from triplet to singlet does pull the emission to the red part of the spectrum. Green is relatively easy to engineer (though spectral purity can be difficult to get right), but blue is hard because the higher energy gap between π-valence states and π* conduction states makes it difficult to get a good match of energy levels with those of the injecting electrodes. This causes drive voltages to be raised, because there are barriers for charge injection, and this generally results in reduced operational lifetimes. Triplet emission in the green is commonly achieved with high efficiency, but triplet emission in the blue part of the spectrum compounds the problem of charge injection further – the effective bandgap for the emissive species is that of the singlet exciton, and this will lie well into the UV for a true blue emitter. This presents huge problems for selection of host materials and charge-injection electrodes. LED Applications The account above of the development of LED architectures to deliver efficient light emission has been matched by a very substantial industrially-led activity to improve device durability. Both for polymer and for vacuum-sublimed devices lifetimes have been advanced very considerably, with

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projected lifetimes under drive conditions to half initial brightness (with a starting value usually taken at around 1000 cd/m2 – about 5 x display brightness) in excess of 100,000 hours. These results are only achieved if there is extremely good encapsulation that prevents ingress of water and oxygen, and at present, requires the use of glass as substrate since it has very much better barrier properties than polymer substrates. Much of the efforts with organic LEDs have been directed to the manufacture of pixellated full colour displays. These generally require an active matrix of thin-film transistors to drive the correct current through each LED, but the circuit demands are more challenging than those set by liquid crystal displays, because the LED is a current-driven device. The use of laser-annealed polycrystalline silicon transistor arrays has therefore been developed, with the local transistor circuit comprising at the minimum, two transistors per sub-pixel. There are at present many demonstrator displays seen at trade shows, made both with polymers (patterned by ink-jet printing) and, more commonly, vacuum-sublimed molecules. Patterning of the latter however remains very difficult to achieve, and one approach that is currently adopted is to deposit white-emitting diodes (see below), and to use a red/green/blue colour filter on top of these. The disadvantage of this approach is that much of the white light generated is discarded, and efficiency is reduced by a factor of 3 or so. As of early 2008, there is now one commercially-available display on the market, produced by Sony, as shown in figure 7.

Figure 7 Images of the Sony XEL-1 organic LED television. The screen diagonal is 11”, and the screen thickness 3 mm. From http://www.sony.co.uk/ The other potentially important area of application for organic LEDs is that of lighting. Improved lighting efficiency is widely regarded as necessary, but Hg-based fluorescent tubes, though efficient (80 lm/W) do not find universal market acceptance. Very considerable progress has been made with inorganic LEDs based on gallium nitride, which, with suitable phosphors to down-convert from the near UV at 405 nm to cover the visible spectrum, can provide excellent efficiencies (comparable to fluorescent tubes). Organic LEDs in contrast are better suited to large-area structures, and it is the case that this matches better the needs for space lighting in building interiors (diffusers and light shades are required for conventional ‘point source’ lighting). Generation of white light in organic LEDs raises some interesting challenges for device architectures. Down conversion from blue using external phosphors has been demonstrated, but is inherently inefficient. Direct generation of red, green and blue (or more realistically, blue and a broader red/green emitter) within the same diode structure is not easy to achieve simultaneously, because there are many channels by which higher energy excitons can be moved to lower energy sites within the same semiconductor layer. Approaches that separate blue (singlet) from lower energy (triplet) layer give good results [30], but perhaps the most elegant approach is to use the singlets generated in the LED to produce blue emission, and channel the triplet excitons formed alongside them to lower energy

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emissive sights, thus using all excitations efficiently [31,32]. Current white organic LEDs show very considerable promise, with efficiencies that should exceed 80 lm/W [22]. Lasing Both molecular and polymeric semiconductors can show very high photoluminescence efficiencies, and it is straightforward to demonstrate optical gain, and with appropriate optical feedback, lasing. This has been demonstrated by many groups [33,34], both for molecular semiconductors (which need to be present at low concentration, as guest, in a higher energy gap host material) or in polymers which can show lasing as pure solid materials. Figure 8 shows one of the early laser structure and associated lasing modes for a polymer device [34]. This is due to the very high luminescence efficiencies that can be achieved in solid state semiconducting polymer films, and makes these materials particularly attractive for optically-pumped lasing because they are strong optical absorbers. One important milestone is the demonstration of lasing achieved by optical pumping with an inorganic GaN laser diode, and this has recently been reported by several groups, as reviewed in [35].

Emission 60 nm

Ag

100 nm

PPV

Intensity (a.u.)

High Power

Low Po wer X50

DBR 355 nm excitation (T = 30%)

500

520

540 560 580 600 Wavelength (nm)

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Figure 8 An early optically-pumped polymer laser structures [34], showing the vertical cavity formed between a layer of PPV with a DBR mirror below and an evaporated silver mirror above. Three cavity modes seen in emission at low intensity reduce to a single mode at high optical excitation intensity.

Optical gain following electrical excitation in an LED structure has not been demonstrated and is difficult for several reasons. Firstly, the presence of injected charge carriers causes associated optical absorption, generally in a band just below the ground-state optical absorption edge, associated with the ‘polaron-like’ character of the injected charge. This has been measured in LED structures which can be driven at very high current densities in pulsed mode (above 1000 A/cm2), but under these conditions, the injected charge densities are several orders of magnitude higher than the exciton density, and no optical gain is possible [36]. The obvious strategy is therefore to increase carrier mobilities in order to reduce charge densities, but if this were achieved, the second problem comes into play: that exciton-exciton interactions generally result in annihilation (this is

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usually modelled as Forster transfer of energy from one exciton to another, which subsequently relaxes to its initial state). This phenomenon has been known for many decades [3], and the threshold at which it sets in depends on exciton mobility, so that high purity single crystals of molecular semiconductors such as tetracene show low thresholds, and this is known to prevent even optically-pumped lasing in such materials [37]. The final problem to be overcome is that the presence of electrodes near to the emissive semiconducting layers can cause significant optical losses, particularly for optical modes confined within the plane of the device. This is hard to avoid because it is necessary to keep the semiconductor layer thin (typically to 100 nm) if drive voltages are to be kept low. This is reviewed in [35]. Photovoltaic Diodes There is renewed interest in the scope for using thin-film organic semiconductors in PV diodes. These are potentially very attractive because there is scope for low cost manufacture onto plastic substrates. The basic challenge that has to be met is that optical absorption in such materials generates a bound exciton that will not readily dissociate in the bulk to electron and hole because the coulombic binding energy is substantial (of order 0.5 eV). The approach that is universally adopted is the use of a heterojunction between electron- and hole-accepting semiconductors, first demonstrated by Tang using a layered structure of phthalocyanine as hole acceptor and perylene derivative as electron acceptor [38]. The scheme of operation is shown in figure 9, with representative semiconducting polymers that also achieve this function [39].

electron C6H13

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Energy

OR

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OR

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CN

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CN-PPV ηIp

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Figure 9 Energy band scheme for operation of a PV diode showing the steps of optical absorption in the hole-accepting polymer, followed by electron transfer at the heterojunction to the electron acceptor. This is demonstrated for alkoxy-substituted PPV versus a cyano-derivative of PPV [39] and for poly(3-hexyl thiophene) versus a soluble C60 derivative, PCBM [40]. Exciton ionisation using the heterojunction schemes shown in figure 9 can be engineering by selecting a sufficiently large band-edge offset so that the intra-chain exciton binding energy is overcome, and there are many examples of systems which achieve this now in the literature, which as reviewed in [41,42]. These systems are relatively inefficient when constructed as two-layer abrupt heterojunctions because photogenerated excitons must be able to reach this heterojunction in

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order to ionise, and their characteristic diffusion range is generally only 10% or so of the thickness of material required for full optical absorption [8]. One promising approach is to form a ‘distributed heterojunction’ structure as illustrated in figure 10, so that all photogenerated excitons are sufficiently close to heterojunctions to be ionised. With organic semiconductors this approach has been explored by the use of de-mixing of a blend of the electon- and hole-accepting materials upon evaporation of solvent from a spin-coated film of a mixture of the two [39,40]. The required length scale for the network is set by the diffusion range of photogenerated excitons, and this is of the order of 10 nm [8]. There are many refinements that would be desirable to use in order to control the morphology of the resultant network, for example, the use of diblock copolymers, but the chemical synthesis of such materials remains challenging. ITO

Polymer blend

Al

h Exciton e

(a)

(b)

Figure 10. (a) AFM image of the free surface of a blend of two semiconducting polymers that have partly de-mixed on evaporation of the solvent used to deposit a film of a mixture of the two by spin coating, after [43]; (b) idealised scheme for the distributed heterojunction required to achieve efficient charge photogeneration. The best results to date have been achieved with blends of poly(3-hexyl thiophene) and the soluble derivative of fullerene, PCBM, as shown in figure 9. Energy conversion efficiencies at 5% are now reliably reported by several groups, as reviewed by [42]. This efficiency is limited by the relatively high onset of optical absorption, near 650 nm, for P3HT (PCBM is weakly absorbing in the visible and near-IR) and the relatively low open circuit voltage (typically 800 mV) due to the very substantial offset of conduction band energies between the two of almost 1 V. Both are in principle open to engineering and improvement, but have yet to be easily improved. For example, Durrant et al. [44] report that as the potential open circuit voltage is increased by modification of the holeaccepting polymer, the yield of separated charge falls rapidly. This is consistent with studies carried out in the author’s group on polymer-polymer blends that indicate that the process of photoinduced charge transfer can result in the formation of a still-bound electron-hole pair (alternatively described as a charge-transfer exciton or exciplex) at the heterojunction, which for some polymer combinations can be detected through direct radiative decay across the heterojunction, with slow and red-shifted emission [19].

Field-Effect Transistors Field-effect structures such as transistors were first studied in the late 1980s, with clean transistor characteristics shown using polyacetylene [45], and are now very routinely made using organic

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semiconductors, as reviewed for example in [46]. Surface charge density is induced at the interface between organic semiconductor and a suitable dielectric by applying an electric field across the dielectric layer (through control of the gate voltage), and this induced charge density provides the conduction path between source and drain. Doped silicon wafers with thermally-grown oxide are often used to provide the gate and dielectric layer, with source and drain provided by lithographically-patterned gold (this provides a good choice for p-type operation). This structure only requires deposition of organic semiconductor (by sublimation or by solution-processing) to complete the transistor, and is therefore particularly convenient to work with.

n

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( SO3

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HSO3 O O O O O O S S S S+ nS O O H O O

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Figure 11 A shows ink-jet printing of PEDOT-PSS onto a surface-patterned substrate, causing confinement of the source and drain to either side of a 5 μm channel of polyimide, B shows an AFM image of the structure, C shows the completion of the device by spin-coating of semiconductor and dielectric and ink-jet printing of the gate electrode [47], D shows an optical image taken with crossed polarisers showing the channel as the light blue line. These structures are useful for exploration of the underlying semiconductor physics, but are not directly useful in areas requiring large areas. A greater challenge is to construct the transistor with organic materials for semiconductor, metallic electrodes and dielectric; if this can be demonstrated to be practical then it becomes feasible to manufacture arrays of transistors over large areas. Figure 11 shows the structure of such a scheme [48] that uses an organic polymer, poly(vinylphenol) as dielectric, and is patterned through the use of inkjet printing of PEDOT-PSS for the source, drain and gate. These devices show modest performance as FETs, as shown in the characteristics presented in figure 12, with field-effect mobilities of order 10-2 cm2/Vs.

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Figure 12 Drain current x channel length versus source-drain voltage for transistors as shown in figure 11, for the values of gate voltage indicated on the figure. Note that there is evidence for some contact resistance, more noticeable for the shorter channel structure [48] Si/Pr3

R S S

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S R

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Figure 13 High mobility solution processible organic semiconductors for use in FETs, PBTTT [49] and TIPS-pentacene [11]. The mobilities of the field-effect charges control the usefulness of the device both for research and for applications. The challenge for materials process is to achieve a well-ordered interface between semiconductor and dielectric, because the surface-induced charges are confined within a couple of nm to this interface. Chemical treatment of the SiO2 top surface, for example with an alkyl silyl chloride to replace the polar SiO2 surface with a sheet of alkyl chains to the organic semiconductor layer, can greatly improve this order. By such methods, mobilities for the best ordered polymers (P3HT) of up to 0.1 to 0.2 cm2/Vs have been reported [50]. Modified polythiophene structures that are better able to crystallise, PBTTT as illustrated in figure 13 below, have recently been shown to exhibit considerably improved mobilities, up to 0.5 cm2/Vs [49]. Molecular semiconductors, such as pentacene as shown in figure 1, can show considerably higher field-effect mobilities, but this requires very careful growth of ordered, crystalline films onto the (bottom) dielectric layer. Mobilities in the range 1-10 cm2/Vs are routinely achieved, as reviewed in [46]. The physical limits to mobility are not clearly understood – though the relatively narrow

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bandwidths expected from the inter-molecular π-electron interactions will restrict mobilities to values lower than found in three-dimensionally bonded semiconductors. Some progress has been made in the solution processing of molecular materials, particularly derivatives of pentacene such as shown in figure 13, and these can show mobilities above 1 cm2/Vs [12]. Performance of FETs is determined by both semiconductor and also the dielectric, since the charges confined to the interface between these two materials will be sensitive to disorder in either layer. An important discovery [51] was the finding that low dielectric constant polymeric insulators give better properties than materials with higher dielectric constants since the latter are generally more polar and disorder in these impedes motion of the accumulation layer charges. Another important aspect of the engineering of the dielectric layer is to be able to produce very thin films that are free of pin-holes; these are required in order to reduce gate voltages and must be used for short channel FETs. Recent progress involving cross-linking of 20 nm thick layers to produce robust dielectric layers is very promising [52]. Light-Emitting Transistors Most of the literature on organic semiconductor FETs has reported p-type operation of these devices, partly because it is generally more convenient to work with air-stable electrodes such as gold, but primarily because n-type operation is difficult to observe, particularly for higher energy gap semiconductors [46]. However, many of the problems in observing n-type behaviour can be attributed to the interfacial chemistry that can occur when polar dielectrics are used, particularly so for the case of SiO2, for which electrochemical reactions to reduce surface hydroxyl groups to Oions can prevent injection of electrons into the semiconductor conduction band [53]. When nonpolar organic dielectrics are used, n-type operation and ambipolar operation become relatively easy to observe [53]. This has made it possible to construct FETs which allow simultaneous injection of electrons (from ‘source’) and holes (from ‘drain’) into the transistor channel, and which show light emission where the drifting electrons and holes meet within the channel [47,54]. This is seen directly in images of light emission from within the transistor channel, as shown in figure 14. FET Applications Organic transistor at present show moderate performance in comparison with amorphous silicon as used (widely) in large-area thin-film transistor arrays for active matrix addressing of liquid crystal displays. Their potential advantage lies in the scope for low temperature processing, enabling the manufacture onto plastic substrates that cannot be taken to the high process temperatures required for amorphous silicon. This is being exploited for the manufacture of active matrix transistor backplanes onto plastic substrates for electronic paper displays, with two current developments both in Europe [55,56].

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Figure 14 (a) Structure of a light-emitting transistor; (b) structure of the light-emitting polymer, F8BT; (c) position of emission zone with respect to source (grounded) electrode and source-drain current versus gate voltage during a transfer scan of an ambipolar F8BT transistor with L = 20 μm; (d) optical images of light emission from F8BT light-emitting transistor with interdigitated sourcedrain electrodes (dark areas) with L = 20 μm. [57]. Outlook The past two decades were characterized by tremendous progress in the performance of organic semiconductor devices. The progress has been so remarkable, that the field of organic electronics – a electronics technology based on organic materials as active layers in semiconductor devices – has moved from the realm of academic laboratories into large-scale manufacturing. With organic LEDs appearing into consumer electronic devices, organic FETs close to the market, and the potential for progress with PV diodes, the strong technological basis being established makes the future of organic electronics seem bright. References: [1] [2] [3] [4] [5]

C. W. Tang, S. A. VanSlyke: Appl. Phys. Lett. Vol. 51 (1987) p. 913-15. J. H. Burroughes, D. D. C. Bradley, A. R. Brown, R. N. Marks, K. Mackay, R. H. Friend, P. L. Burns, A. B. Holmes: Nature Vol. 347 (1990) p. 539-41. M. Pope, C. E. Swenberg: Electronic Processes in Organic Crystals and Polymers, Oxford University Press, New York, 1999. M. Pope, H. Kallmann, P. Magnante: J. Chem. Phys. Vol. 38 (1963) p. 2042-43. W. Helfrich, W. G. Schneider: Phys. Rev. Lett. Vol. 14 (1965) p. 229-31.

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[18] [19] [20] [21] [22] [23] [24] [25] [26]

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P. M. Borsenberger, D. S. Weiss: Organic Photoreceptors for Imaging Systems, M. Dekker, New York, 1998. C. K. Chiang, C. R. Fincher, Y. W. Park, A. J. Heeger, H. Shirakawa, E. J. Louis, S. C. Gau, A. G. MacDiarmid: Phys. Rev. Lett. Vol. 39 (1977) p. 1098-101. J. J. M. Halls, K. Pichler, R. H. Friend, S. C. Moratti, A. B. Holmes: Appl. Phys. Lett. Vol. 68 (1996) p. 3120-22. N. Karl, in R. Farchioni, G. Grosso (Eds.), Organic Electronic Materials. Springer, Berlin, 2001, p. 283-326. A. J. Heeger, S. Kivelson, J. R. Schrieffer, W.-P. Su: Rev. Mod. Phys. Vol. 60 (1988) p. 781850. J. E. Anthony, J. S. Brooks, D. L. Eaton, S. R. Parkin: Journal of the American Chemical Society Vol. 123 (2001) p. 9482-83. S. K. Park, T. N. Jackson, J. E. Anthony, D. A. Mourey: Applied Physics Letters Vol. 91 (2007). H. Sirringhaus, T. Shimoda: Materials Research Society Bulletin, Vol. 28, No. 11, November Vol. (2003). C. W. Sele, T. von Werne, R. H. Friend, H. Sirringhaus: Advanced Materials Vol. 17 (2005) p. 997-+. M. S. Arnold, G. J. McGraw, S. R. Forrest, R. R. Lunt: Applied Physics Letters Vol. 92 (2008). R. H. Friend, R. W. Gymer, A. B. Holmes, J. H. Burroughes, R. N. Marks, C. Taliani, D. D. C. Bradley, D. A. Dos Santos, J. L. Brédas, M. Lögdlund, W. R. Salaneck: Nature Vol. 397 (1999) p. 121-27. W. R. Salaneck, K. Seki, A. Kahn, J. J. Pireaux (Eds.), Conjugated polymer and molecular interfaces: Science and technology for photonic and optoelectronic applications. Marcell Dekker, New York, 2002. N. Koch, A. Kahn, J. Ghijsen, J. J. Pireaux, J. Schwartz, R. L. Johnson, A. Elschner: Applied Physics Letters Vol. 82 (2003) p. 70-72. A. C. Morteani, A. S. Dhoot, J. S. Kim, C. Silva, N. C. Greenham, C. Murphy, E. Moons, S. Cina, J. H. Burroughes, R. H. Friend: Advanced Materials Vol. 15 (2003) p. 1708-+. J. Clark, C. Silva, R. H. Friend, F. C. Spano: Physical Review Letters Vol. 98 (2007). M. A. Baldo, S. Lamansky, P. E. Burrows, M. E. Thompson, S. R. Forrest: Applied Physics Letters Vol. 75 (1999) p. 4-6. www.novaled.com. S. C. Lo, N. A. H. Male, J. P. J. Markham, S. W. Magennis, P. L. Burn, O. V. Salata, I. D. W. Samuel: Advanced Materials Vol. 14 (2002) p. 975-+. M. Wohlgenannt, Z. V. Vardeny: Journal of Physics-Condensed Matter Vol. 15 (2003) p. R83-R107. J. S. Wilson, A. S. Dhoot, A. J. A. B. Seeley, M. S. Khan, A. Köhler, R. H. Friend: Nature Vol. 413 (2001) p. 828-31. E. A. Meulenkamp, R. van Aar, J. J. A. M. Bastiaansen, A. J. M. van den Biggelaar, H. Börner, K. Brunner, M. Büchel, A. van Dijken, N. M. M. Kiggen, M. Kilitziraki, M. M. de Kok, B. M. W. Langeveld, M. P. H. Ligter, S. I. E. Vulto, P. van de Weijer, S. H. P. M. de Winter: Proceedings of the SPIE Photonics Europe meeting, Strasbourg, France, April 2004 Vol. (2004). M. Segal, M. A. Baldo, R. J. Holmes, S. R. Forrest, Z. G. Soos: Physical Review B Vol. 68 (2003) p. art. no.-075211. J. L. Bredas, D. Beljonne, V. Coropceanu, J. Cornil: Chemical Reviews Vol. 104 (2004) p. 4971-5003.

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[29] X. Zhou, M. Pfeiffer, J. Blochwitz, A. Werner, A. Nollau, T. Fritz, K. Leo: Applied Physics Letters Vol. 78 (2001) p. 410-12. [30] G. Schwartz, K. Fehse, M. Pfeiffer, K. Walzer, K. Leo: Applied Physics Letters Vol. 89 (2006). [31] G. Schwartz, M. Pfeiffer, S. Reineke, K. Walzer, K. Leo: Advanced Materials Vol. 19 (2007) p. 3672-+. [32] Y. R. Sun, N. C. Giebink, H. Kanno, B. W. Ma, M. E. Thompson, S. R. Forrest: Nature Vol. 440 (2006) p. 908-12. [33] F. Hide, M. A. DiazGarcia, B. J. Schwartz, M. R. Andersson, Q. B. Pei, A. J. Heeger: Science Vol. 273 (1996) p. 1833-36. [34] N. Tessler, G. J. Denton, R. H. Friend: Nature Vol. 382 (1996) p. 695-97. [35] I. D. W. Samuel, G. A. Turnbull: Chemical Reviews Vol. 107 (2007) p. 1272-95. [36] N. Tessler, N. T. Harrison, R. H. Friend: Adv. Mater. Vol. 10 (1998) p. 64-68. [37] M. A. Baldo, R. J. Holmes, S. R. Forrest: Physical Review B Vol. 66 (2002) p. art. no.035321. [38] C. W. Tang: Appl. Phys. Lett. Vol. 48 (1986) p. 183-85. [39] J. J. M. Halls, C. A. Walsh, N. C. Greenham, E. A. Marseglia, R. H. Friend, S. C. Moratti, A. B. Holmes: Nature Vol. 376 (1995) p. 498-500. [40] G. Yu, J. Gao, J. C. Hummelen, F. Wudl, A. J. Heeger: Science Vol. 270 (1995) p. 1789-91. [41] B. A. Gregg: Journal of Physical Chemistry B Vol. 107 (2003) p. 4688-98. [42] S. Gunes, H. Neugebauer, N. S. Sariciftci: Chemical Reviews Vol. 107 (2007) p. 1324-38. [43] A. C. Arias, J. D. MacKenzie, R. Stevenson, J. J. M. Halls, M. Inbasekaran, E. P. Woo, D. Richards, R. H. Friend: Macromolecules Vol. 34 (2001) p. 6005-13. [44] H. Ohkita, S. Cook, Y. Astuti, W. Duffy, S. Tierney, W. Zhang, M. Heeney, L. McCulloch, J. Nelson, D. D. C. Bradley, J. R. Durrant: Journal of the American Chemical Society Vol. 130 (2008) p. 3030-42. [45] J. H. Burroughes, C. A. Jones, R. H. Friend: Nature Vol. 335 (1988) p. 137-41. [46] C. D. Dimitrakopoulos, P. R. L. Malenfant: Advanced Materials Vol. 14 (2002) p. 99-117. [47] J. Zaumseil, R. H. Friend, H. Sirringhaus: Nature Materials Vol. 5 (2006) p. 69-74. [48] H. Sirringhaus, T. Kawase, R. H. Friend, T. Shimoda, M. Inbasekaran, W. Wu, E. P. Woo: Science Vol. 290 (2000) p. 2123-36. [49] I. McCulloch, M. Heeney, C. Bailey, K. Genevicius, I. Macdonald, M. Shkunov, D. Sparrowe, S. Tierney, R. Wagner, W. M. Zhang, M. L. Chabinyc, R. J. Kline, M. D. McGehee, M. F. Toney: Nature Materials Vol. 5 (2006) p. 328-33. [50] H. Sirringhaus, P. J. Brown, R. H. Friend, M. M. Nielsen, K. Bechgaard, B. M. W. LangeveldVoss, A. J. H. Spiering, R. A. J. Janssen, E. W. Meijer, P. Herwig, D. M. de Leeuw: Nature Vol. 401 (1999) p. 685-88. [51] J. Veres, S. D. Ogier, S. W. Leeming, D. C. Cupertino, S. M. Khaffaf: Advanced Functional Materials Vol. 13 (2003) p. 199-204. [52] M. H. Yoon, H. Yan, A. Facchetti, T. J. Marks: Journal of the American Chemical Society Vol. 127 (2005) p. 10388-95. [53] L. L. Chua, J. Zaumseil, J. F. Chang, E. C. W. Ou, P. K. H. Ho, H. Sirringhaus, R. H. Friend: Nature Vol. 434 (2005) p. 194-99. [54] J. S. Swensen, C. Soci, A. J. Heeger: Applied Physics Letters Vol. 87 (2005). [55] www.polymervision.com/ [56] www.plasticlogic.com: [57] J. Zaumseil, C. R. McNeill, M. Bird, D. L. Smith, P. P. Ruden, M. Roberts, M. J. McKiernan, R. H. Friend, H. Sirringhaus: Journal of Applied Physics Vol. 103 (2008).

Materials Science Forum Vol. 608 (2009) pp 181-200 © (2009) Trans Tech Publications, Switzerland doi:10.4028/www.scientific.net/MSF.608.181

Photovoltaic Power Generation the Impact of Nano-materials A.R. Peaker & V.P. Markevich Prof.Anthony. R. Peaker Electrical and Electronic Engineering Sackville Street Building Room D4 The University of Manchester MANCHESTER M60 1QD ,UK [email protected]

Keywords: solar, photovoltaic, silicon, nanomaterials, quantum dot CdSe, GaAs, GaInAs, GaInP, Ge

Abstract: Solar power is seen by many as a solution to the world’s energy problems. The earth receives 1.7x1017W from the sun compared to a total electricity generation capacity of 4.6x1012W (OECD prediction for 2010). However the average power density is low with a daytime average over the earth of 680Wm-2. This makes centralised generation problematic but distributed photoelectric generation by domestic and commercial users is a rapidly developing market. However typical commercially available modules have an energy conversion efficiency of less than 12%. Silicon cells with 24% efficiency have been produced in the lab while multi-junction tandem cells using different semiconductor materials (GaInAs, GaInP and Ge) to absorb different parts of the sun’s spectrum have reached 40%. This chapter describes some of the materials and device achievements so far and looks at possible ways in which higher efficiencies might be achieved with particular emphasis on nano-materials to use more of the solar spectrum efficiently. The possibility of using quantum slicing and multiple exciton generation to make more efficient use of high energy photons is considered and impurity band generation as a possible route to use low energy photons. One of the greatest challenges is to do this cheaply using semiconductors made from non-toxic abundant elements.

1.

Solar Energy

The last ten years has seen a dramatic increase in research into renewable energy sources. The reasons are well publicised: increasing world energy demands particularly from countries with emerging economies, exhaustion of easily accessible oil resources and fears that global warming is a result of CO2 emissions from fossil fuels. Solar power is the prime source of renewable energy and is very substantial. In one hour the sun delivers energy equivalent to an entire year of energy consumption by mankind. The problem is how to harness the sun’s massive energy output. One option is to produce electricity by photovoltaic cells.

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The irradiance at the extremity of the earth’s atmosphere is ~1360 W m-2 with a spectral distribution as shown in Figure 1 as (a). The spectrum is basically that of a 5762K black body radiator on which are superposed the fine detail of emission lines and Fraunhofer lines resulting from absorption in the peripheral solar gas. At the surface of the earth additional spectral detail is introduced by absorption in the earth’s atmosphere1 (line b) resulting primarily from water vapour, carbon dioxide and ozone. The available energy is also reduced by Rayleigh and Mie scattering processes with the result that the available power density at the earth’s surface after the light has passed through 1.5 atmospheres (typical of latitudes ~50º) is around 900W m-2 at midday. These data have been published as ASTM standards from which Figure 1 is derived 2. However local variations occur due to climatic conditions in addition to the systematic variation with latitude, season and of course time of day. For Europe these values have been compiled under the PVGIS project3 and are available as interactive maps. As an example of the total of the solar energy available in an average year on an optimally inclined surface the value in Berlin is 1142 kWh/m2.

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Figure 1 Spectral distribution of the sun’s irradiance on earth at a) air mass 0 (top curve) and b) air mass 1.5. For a simple pn junction silicon solar cell only photons with an energy greater than 1.12eV are absorbed Many approaches to using this energy have been proposed. In this chapter we focus on photovoltaics but this need to be considered in the context of other approaches. These have been reviewed with an emphasis on the materials requirements in a 2008 issue of the MRS Bulletin devoted solely to energy provision4.

2.

Photovoltaic Power Generation

2.1 Basic Concepts Converting the power in sunlight to electricity efficiently is not simple. It can be seen in Figure 1 that there is quite a broad spectral distribution of the available energy. If the light is used to generate electrons in a semiconductor, photons with an energy greater than the bandgap will be absorbed and have a probability of producing a carrier which can be supplied to an external circuit. In

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conventional solar cells, often referred to as first generation cells, photons with an energy less than the bandgap will not be absorbed by the semiconductor and their energy will be lost. This also applies to second generation cells which are usually thin films of semiconductor deposited on low cost substrates. In a conventional p-n junction solar cell the output voltage is dependent on the bandgap of the absorbing semiconductor so the greater the bandgap the greater the voltage. However photons with an energy greater than the bandgap will only produce one carrier pair so energetic photons will not be used effectively in a simple p-n junction system. These concepts are illustrated in Figure 2 which also shows some other energy loss mechanisms. Recombination at defects and impurities is normally small in high quality wafers of single crystal silicon grown by the Czochralski or float zone methods but is very significant in block cast polycrystalline material. Surface and interface recombination depends largely on cell design and fabrication technologies but is increasingly important in conventional second generation thin film cells. However the dominant loss mechanisms are the fundamental problem of not using below bandgap photons at all and not using photons with energies significantly above band gap effectively.

Figure 2 Representation of some important energy loss mechanisms in first and second generation pn junction solar cells A consequence of the above issues is that there is an optimum bandgap for simple solar cells (ie first and second generation). A maximum possible efficiency for conversion of the solar spectrum can be calculated allowing for the lost photons of long wavelength and the partial energy conversion of the short wavelength radiation. This calculation was first published by Loferski5 in 1956 and subsequently refined by Shockley and Queisser6. They assumed the sun was a black body radiator at 6000K and the solar cell temperature 300K. They derived a detailed balance limit of the conversion efficiency for a semiconductor of gap 1.1eV of 30% assuming a perfectly matched load, 100% absorption of photons with energy greater than the band gap and no non-radiatative recombination losses. Numerous variants on this calculation have been published and an “optimum” bandgap calculated at around 1.35eV determined but the general conclusion is that there is a fundamental limit to the achievable efficiency of a simple p-n junction solar cell of between 30 and 35%, the exact value in various publications being dependant on the assumptions made.

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In practice silicon with its bandgap of 1.12eV has received most technological attention and efficiencies over 24% have been achieved for small area optimised structures7. Much effort has been expended by many researchers in these high efficiency cells in order to reduce surface recombination, optimise absorption and reduce reflection. These issues are discussed in detail elsewhere8. The silicon used to achieve these efficiencies was single crystal magnetically-confined Czochralski or float zone. These materials have a long minority carrier lifetime and so largely fulfil one of the Shockley-Queisser conditions of no non-radiatative recombination. This is not the case for the low cost block cast polycrystalline silicon used for mass produced cells where typical efficiencies are 10%. In this material and in very lower cost metallurgical silicon purified by low energy methods the challenge is to reduce the non-radiative paths usually attributed, at least in part, to metallic contamination. This issue has received much attention and a substantial volume of literature exists quantifying the problem and proposing possible solutions9. In conventional silicon cells a long minority carrier lifetime is an essential prerequisite for high efficiency primarily because it provides the long diffusion length for minority carriers and hence enables effective collection of the carriers generated by absorption of photons. The fundamental requirements are to eliminate (or at least minimise) recombination in the bulk, at the surface and at interfaces. Cells based on wafers of single crystal silicon are considerably more efficient than cells made from polycrystalline material or thin films deposited on glass or metal substrates. However the material cost is higher. In May 2008 SunPower10 announced that they had produced a production prototype large area cell (5inch) based on mono-crystalline wafered silicon with an efficiency of 23.4% beating the previous year’s pre-production best from Sanyo by a small margin. This is probably very close to the achievable limit for commercial device designs. It is well known that photovoltaic cells degrade under normal operating conditions11. In the case of satellite cells the dominant mechanism is radiation damage which limits the useful life of the cell. In terrestrial cells there are a number of known mechanisms. A particular problem is the degradation of the efficiency of boron doped silicon cells containing oxygen which occurs during the first few days of operation. This is most significant in high efficiency cells made from Czochralski material but also occurs in multi-crystalline cast material. Typical degradation is 10% relative so the efficiency of a 20% cell reduces to 18% after two or three days’ operation. Although this effect has been known for some time it is only recently that the mechanism has been explained as being due to the formation of a metastable boron-oxygen complex12, 13. The effect can be reversed by thermal treatments14 and avoided by doping with gallium instead of boron or reducing the oxygen content of the silicon. Unfortunately these alternatives have economic or practical difficulties and so this rapid initial degradation is of considerable practical importance.

2.2 Economic and Ecological Considerations The economics of the generation of electricity from solar power are skewed by governments providing a “feed in tariff” This essentially guarantees domestic users and small enterprises a market for their solar electricity fed into the distribution grid at a price well above the 2008 cost of generation from fossil fuels. Some countries (for example Germany) guarantee the tariff for a fixed period making the purchase of solar panels a safe investment. In general the cost of this subsidy is met by increased tariffs to the electricity consumers. Estimates of the actual ratio of production costs vary but in the USA a figure which is often quoted is that electricity generated by a small photovoltaic installation (~ 2kW peak) if it were to be fed into the grid would cost five times as much as electricity generated from a coal station at the point of production. This assumes the

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photovoltaic system has a working life of 25 years. The calculation is only relevant for grid connected installations because it does not take into account the need for energy storage necessary for stand alone systems during the hours of darkness. This is more than the cost of the solar cells. Feed in tariffs are a justifiable short term policy for the situation where photovoltaic generation is a small proportion of the total generation capacity. Such distributed power generation, usually at a domestic level, is based on the solar panel as a consumer good. A century of experience tells us that such markets have a high elasticity of demand. Mass production drives down the price which further stimulates demand. The norm early market situation is a 10% decrease in production cost for each doubling of market size. At the present time system costs far outweigh material costs but in the future this will not be the case. Infrastructure costs also favour high efficiency devices because, although cheap lesser efficiency systems seem equivalent, the reality is that for urban applications the area available for solar cells is strictly limited and a larger area means larger land and installation costs. Inevitably the driving force is towards cost effective high efficiency systems. A useful concept in assessing the ecological and economic value of solar cells is “payback time”. This can either mean the time to recover the financial investment in terms of the cost of energy produced or simply the time taken to recover the energy expended in producing the solar cell or more realistically the solar cell system including the voltage conversion and management circuits and devices. If we ignore the feed in tariff the reality of the situation in 2007 was that commercially available systems will take more than 20 years to pay back economically. Although some manufacturers claim a 30 year life expectation for their modules it is quite evident that both cost and efficiency improvements are essential. Much needs to be done in terms of materials research to achieve this. Energy payback time has been studied recently for the case of silicon polycrystalline panels by Stoppato15. She analysed the production process in detail and identified the most energy hungry steps. Assuming a commercial poly-silicon 100cm2 panel manufactured by existing methods, installed on grid (all output used) in various locations, she calculated an energy payback time typically between 4 and 6 years.

3.

Beating the Shockley-Queisser Limit

Achieving truly high efficiencies (well above the Shockley-Queisser limit) at low cost is an essential pre-requisite to the widespread adoption of photo-voltaics for energy production. Many publications propose approaches to this problem. The most common short term solution is to split the spectrum into component parts and extract energy from the spectral segment with an appropriate band gap semiconductor. This can be done with dichroic mirrors feeding light to two separate independent cells or by using a number of solar cells stacked with the widest bandgap on top. Such a structure could consist of separate cells or a monolithic structure composed of semiconductors with multiple gaps again with the widest gap on top. The design of such stacked multiple junction cells is very complicated. As the junctions are connected in series the same current flows though the entire structure. In consequence the band gaps need to be chosen so that each material system contributes the same current utilising the appropriate spectral region. This is compromised in the monolithic structures by practical considerations of available materials with either lattice matching or controlled strain … issues which will be considered later.

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These structures are inevitably more expensive than a simple one bandgap cell so, although they are widely used as power supplies in communication satellites, for terrestrial applications they are looked at primarily for applications where the sunlight is concentrated via a lens or reflector system. However a key problem with concentrators is that in a focused system the optics must track the sun to retain the optimum advantage of concentration. This is typically done with mechanical systems although clever optics can eliminate moving parts at a cost of lower efficiency when the sun deviates by more than about 20º from the cell axis. Cells operating under concentrated light are in general more efficient. This is partially because of the reduced significance of non-radiative processes but after such processes have saturated, the gain in efficiency with increased intensity is due to increased cell voltage. The photovoltaic current increases approximately linearly with solar intensity and because the current appears across a p-n junction the voltage increases logarithmically with voltage. Hence an increase in efficiency is observed until the increase in Ohmic voltage drop (which rise linearly with current and is due to series resistance effects) exceeds the increase from the diode I-V dependence. The temperature rise of the cell has also to be considered because of its effect on the leakage current and the shift of band gap. The latter is a surprisingly large effect. At 20ºC the optimum gaps16 for a two band gap cell are 0.96 and 1.54eV while at 150ºC the gaps (measured at 20ºC) need to be 1.2 and 1.8eV respectively17. Because of these factors concentrator cells usually operate at or less than two hundred times the intensity of normal sunlight, referred to as 200 suns. Henry18 has calculated the limiting efficiency of multiple energy gap solar cells using a very similar approach to Shockley and Queisser but using the true air mass 1.5 spectrum for a somewhat unrealistically high level of concentrated light of 1000 suns. Henry’s calculation for a single material cell with the optimum gap of 1.35eV under one sun is 31% (very close to the Shockley and Queisser calculation) and under 1000 suns 37% assuming a cell temperature of 300K. For multiple junction devices with optimum bandgap materials the maximum efficiency of a two junction cell was calculated to be 50%, three junctions 56% and 72% for 36 energy gaps. Henry makes an important point that this efficiency although high is well below the thermodynamic limit for converting the energy of 1000 sun radiation into work ( 93%). This is because energy is lost and entropy increases when light is emitted from the forward biased p-n junctions.

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Multiple Cell Systems

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Conceptually dual cell systems are the simplest way to utilise more of the solar spectrum effectively. Early proposals consisted of two separate cells of different materials In Figure 3a this is effected by a dichroic mirror. Using AlGaAs and Si as the materials an efficiency of 28.5% was achieved as early as 1978 19. The wavelength separator system has also been proposed for use in conjunction with a thermoelectric generator20. The more difficult to utilise long wavelength region could be concentrated on the thermopile while the shorter wavelength component would be directed onto a photovoltaic element. Current thermoelectric materials provide efficiencies around 8% so much work must be done before such systems contribute much to the total system performance.

Figure 3 Two approaches to spectrum splitting a) dichroic mirror with two cells b) cascaded cells using a wide gap cell on top with a transparent rear connection allowing longer wavelength light to be transmitted An approach which combines the concepts illustrated in Figures 3a and 3b is being followed in a current research programme using two tandem cells one of which filters the radiation with the remaining flux being incident on a silicon cell21. By using a static concentrator and a dichroic prism designed to have an optical efficiency of 93% in combination with GaInP/GaAs + Si and GaInAsP/GaInAs diodes the sum of the outputs from the cells (not connected in series and optimised independently) amounted to 42.9% . The structure shown in Figure 3b utilises the top cell to absorb the high energy photons which are filtered out leaving the remaining radiation to be used by the lower cell. This is the basis of the most widely used strategy for beating the Shockley-Queisser limit namely the monolithic tandem cell.

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Monolithic Multiple Cell Structures

Monolithic tandem cells are based on well established technologies and have been used extensively in commercial space applications since the mid 1990s. These structures are typically made from InGaP/GaAs/Ge with bandgaps of 1.85/1.4/0.66eV. In 1997 such devices used in terrestrial applications achieved 30% efficiency at air mass 1.5 under 1 sun intensity22. For concentrator applications under AM 1.5 and 200 suns such a cell has been demonstrated to give 39.2% 23. The development of such devices presents immense challenges in terms of materials and design trade offs. The concept is simple and expounded above. The two materials have to filter out a segment of the spectrum so that the combination of bandgap, thickness and efficiency produces equal current in each region which is also equal to the current generated in the germanium substrate. Direct gap materials are desirable for the upper layers because the absorption edge is abrupt resulting in the requisite absorption being produced by thinner (and hence in principle less expensive) layers. In addition thinner layers give good performance with shorter diffusion lengths. However in thin layers the surface and interface become more significant so that surface recombination needs to be actively suppressed. To a large extent all these issue can be quantified and used in a design model. However what is much more difficult to predict is the effect of strain, relaxation and dislocations on the non-radiative recombination. An added complication is the inter-diffusion between the layers which can occur during growth and subsequent processing. This can result in bandgap shifts or in unwanted donors and/or acceptors. The latter problem is relevant because the substrate is a group IV compound and the upper layers III-Vs, A key issue in tandem cells is that it is necessary for current to flow through the entire structure. This necessitates passing current through a reversed biased junction without a significant barrier and minimal series resistance. The latter issue is particularly important for concentrator cells and is achieved by using a tunnelling junction relying on highly doped regions. This “contact” between cells must also be transparent

4.3

GaInP/GaInAs/Ge Concentrator Cells

The material system GaInP/GaInAs/Ge has proved to be one of the most successful for concentrator cells produced at the time of writing. It has been used by several research groups and some designs are in an early production stage in concentrator systems. Figure 4 illustrates two very efficient monolithic tandem structures. One is a lattice matched cell and the other a metamorphic tandem cell. Both are designed by Spectrolab and have achieved over 40% conversion efficiencies24, 25.

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Figure 4 A 40% efficient InGaP/GaAs tandem cells with InGaP tunnel junctions and an AlInP barrier layer acting as a window layer (from King et al25 Copyright © 2007 The Boeing Company. All rights reserved. Used by permission. ) The metamorphic device was operated at 240 suns (24W cm-2) at air mass 1.5. The device has an open circuit voltage of 2.9V and a short circuit current of 1A (current density 3.8A cm-2) The cell consists of a Ga0.44In0.56P/Ga0.92In0.08As/Ge structure (1.8/1.3/0.66eV). Carrier confinement (to reduce surface and interface recombination) is effected in the top cell by the AlInP window and the AlGaInP back surface field (BSF) layer. At the time of writing the Spectrolab device holds the world record for efficiency of any solar cell. However other groups have achieved efficiencies close to 40%. The view has been expressed in both commercial and scientific literature that 50% is achievable using this technology. Metamorphic material systems offer greater design flexibility but are not as mature as lattice matched systems. Life tests on lattice matched systems designed for space use are remarkably stable under 1 sun under air mass 1.5. Certainly they do not suffer the 10% relative degradation in the first few days of operation seen in high efficiency boron doped Czochralski silicon cells. However detailed studies are required to discover the long term stability of high efficiency concentrator tandem cells. There are however many doubts surrounding these well developed tandem cell materials. The high cost restricts their use to concentrator systems. To maintain a high system efficiency throughout all hours of daylight mechanical tracker systems have to be used. Although these are acceptable for central generator installations they are less attractive for domestic use because of maintenance and the impact on the appearance of homes. Passive concentrators compromise efficiency over a large part of the day and are only highly efficient for around two hours each side of noon. However a crucial point to bear in mind is that the ultimate or thermodynamic limit on efficiency is 68% at one sun but rises with concentrated sun light. As the subject progresses it seems inevitable that we will move towards the thermodynamic limit making concentrator cells a certainty for large scale commercial generation on fundamental as well as economic grounds. If solar cells are to contribute a major part of our electricity requirement very large amounts of the solar cell material will be required and the question has been raised as to whether accessible

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resources of indium and germanium are adequate for such widespread application. The question is even more acute in non concentrator systems.

5.

Thin Films and Hetero-junctions

Many other ways of making solar cells are being explored. The so called second generation solar cell projects are focussing on reducing costs by using thin films usually with a single p-n junction but sometimes with wider band gap confining layers. The technological target is to reduce material and manufacturing cost while attaining high efficiency in an evolutionary rather than revolutionary way. A very large number of systems and materials have been explored including amorphous Si, thin film Si, CuInxGa(1-x)Se2, CdTe, and a range of organic materials. The latter will be considered in detail in section 6.5. These second generation cells are based on inexpensive supports, soda glass, metal or in some cases plastics and encapsulated with low cost materials. In some cases good efficiencies have been achieved in the lab. However wafer based crystalline silicon still remains the dominant material system commercially constituting more than 85% of sales. Among the thin film devices CdTe has achieved greatest market penetration (although others have considerable potential) because of reasonable efficiencies and the possibility of depositing thin films very cheaply and with little energy expenditure. However the long term future of CdTe as a major technology is questionable. The primary reason for this is the toxicity of cadmium. CdTe cells contain more than 1% Cd and so are technically illegal in Europe. They can only be sold because of a special temporary dispensation. In addition Te has the problem referred to above of being a material with very limited abundance which could not sustain widespread use in non-concentrator applications. The market leader in the field, First Solar, has attempted to overcome these difficulties by providing recycling as part of their module supply contracts. An overview of the development of thin film technologies has been published by Green26 and a review of confirmed best efficiencies across all technologies compiled on a regular basis and published in Progress in Photovoltaics27. An interesting variant on solar cell design is to use a pn hetero-junction. Here the different bandgaps of the two materials can absorb a wider spectral region than a single material and so can beat the Shockley-Queisser limit. However there is a fundamental difference when compared to the tandem cell. Carriers generated in both materials contribute to the current so that the current contributions from the two materials are in parallel. The output voltage is the voltage from the single junction. In the tandem cell the junctions are in series (hence the need to balance the currents) but the junction voltages are additive. This is conceptually important in relation to the next section in which nano-materials are discussed.

6.

Nano Materials to the Rescue?

The primary importance of nano-materials in opto-electronics is that the small dimensions confer quite different properties on the material. Such structures bridge the transition between bulk semiconductors and individual atoms. If the physical size of the semiconductor sample is reduced the interaction between the atoms differs from the bulk solid and the properties become very interesting from the point of view of electronic materials and novel applications particularly in the area of opto-electronics. Such concepts are not at all new. The ideas expressed above have been known in terms of quantum wells for more than twenty years and are widely used today in semiconductor LASERs in consumer

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goods. Quantum wells are planes of semiconductor material usually within a wider band gap host. Carriers are confined to move in two (as distinct to three) dimensions. A structure which is of fundamental interest in relation to nanostructures is the quantum well solar cell. Mazzar28 describes a strain-balanced GaAsP/InGaAs multi-quantum well structure grown on GaAs with a AM 1.5 efficiency under 200 suns of 26%. The spectral response is extended considerably beyond that of GaAs. An important factor in these structures is the recombination in the quantum wells which is believed to be predominantly radiative resulting in photon recycling. However there are inevitably losses involved in such recycling and this may present an insuperable barrier to obtaining very high efficiencies in such cells. Much more interesting are structures which confine carriers to motion in one or zero dimensions referred to historically as quantum wires (1D) or quantum dots (0D). For the purposes of this chapter these later structures are our nano-materials. A key advantage in optoelectronics (and indeed in several other semiconductor device applications) is that the material properties can be adjusted or in some cases continuously tuned by simply changing the size of the structure. The most obvious property is the effective band gap which increases as the dimensions decrease. The use of such structures in solar cells have potential advantages over conventional materials in several important applications but represent immature explorations or in some cases little more than proposals. The primary hurdle to application is the fabrication of the nano-material with controlled structure. For example quantum dots can be fabricated by simple self organising techniques but the wide size distribution renders such materials difficult to use in applications where close control of specific properties is required. The requirements for a successful nano-structured solar cell which will be widely adopted follow quite logically from the discussion in earlier sections. Essentially: 1) It should have high conversion efficiency. This necessitates using as much of the solar spectrum as effectively as possible and being able to extract the carriers with minimal losses from recombination, series resistance etc. 2) It must be inexpensive to manufacture using abundant non-toxic materials. 3) It must not degrade substantially during a working life of 20 to 30 years. In the remainder of this chapter we will explore a range of approaches which either use nanostructures as the key enabling technology or material systems which might benefit from nanomaterials. This is a very fast moving area and many proposals regarding the potential of nanostuctures for solar energy have been made. The review below covers some of the key approaches and gives a brief overview of each with selected state of the art examples. Where possible references are given to comprehensive reviews.

6.1

Tandem and Heterojunction Cells using Nanomaterials

Being able to tune the bang gap of a nano-structured material suggests a solution to matching the solar spectrum. Silicon nano-crystals smaller than 6nm exhibit quantum confinement. It is quite easy to grow such dots in a matrix of SiO2. If they are sufficiently densely packed the overlap of the wavefunctions produces a miniband which results in a nano-structured material having an effective bandgap larger than that of silicon and in consequence could be used as the upper (short wavelength absorbing) layer in an “all silicon” tandem cell. One could envisage multiple layers with varying sizes of nano-particles resulting in a multiple tandem structure. Silicon is an indirect bandgap semiconductor so needs phonon participation in the absorption process. This results in weaker absorption and a less steep dependence of absorption coefficient as a

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function of wavelength in bulk materials. In quantum dots the k-conservation requirement is relaxed and so the material behaves more like a direct gap material with, effectively, greater absorbance. However a major problem is the extraction of carriers and, as in the cases of the III-V tandem cells described earlier, the difficulty of matching currents in the series combination of layers A less demanding task would be to produce a hetero-structure cell as shown in Figure 5. Here the shorter wavelength light generates carriers in the wider bandgap nano-material while longer wavelength light is absorbed in the substrate. The carrier current in the two regions is additive while the open circuit voltage will depend on the bandgaps, their alignment and the location of the Fermi levels in the two materials. Such a cell need not necessarily have a uniform size distribution of quantum dots which is difficult to achieve if reliance is placed on random nucleation. However the layer must carry current and the carriers must be extracted from the dots. This has proved to be extremely difficult to achieve with any reasonable efficiency in practical systems.

Figure 5 Conceptual representation of a silicon quantum dot heterostructure solar cell. The silicon quantum dots absorb shorter wavelengths to create carriers while the crystalline silicon substrate acts as a conventional photovoltaic material in the heterostructure. The optimum bandgap for the top absorber in a silicon based two cell device at AM1.5 is 1.7eV. Photoluminescence studies29 indicate that 2nm quantum dots in an SiO2 matrix would have an effective bandgap close to this. Cho et al30 have fabricated such a nano-material in silicon by producing by thermal treatment of a sputtered silicon rich SiOx layer between 2 and 5nm thick on an p-type silicon substrate. Phosphorous was co-sputtered in order to produce n-type conduction in the dot layer although the actual mechanism is unclear. The role of dopants in quantum dots is rather debatable but Cho does observe n-type conduction in the nano-layer provided the spacing of the dots is less than 2nm. The open-circuit voltage increased with reductions in QD size, which was attributed to bandgap widening effect in the Si QDs and an improved hetero-junction field allowing a greater split of the Fermi levels in the Si substrate. Photovoltaic conversion efficiencies of ~10% were observed but at this stage it is not possible to say if the nano-layer made any contribution to this.

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A silicon substrate is not the ideal material for such a structure as, apart from cost, photons longer than the Si bandgap are lost in this type of cell. Some work has also been done on other materials but work is at a very early stage. However other very different approaches are being investigated to utilise the longer wavelength photons.

6.2

Intermediate Band Cells

All the cells we have considered so far use photons to effect excitation from the conduction to the valence bands. If we were to introduce an impurity band in the gap then carriers generated by longer wavelength photons could be used and the energy of two photons summed to produce carrier energies comparable with an excitation across the full band gap. This process was observed for discrete energy levels by Grimmeis31 and calculations undertaken in relation to its predicted application in solar cells by Wolfe32. The concept is illustrated in Figure 6. Ideally the band should be offset so that effectively the material has three absorption edges. The position of the band should be chosen so that the carrier flux in process (b) matches the carrier flux in process (c) so maintaining sufficient occupancy of the intermediate level to maximise absorption. The combination of the processes a, a′, b and c could cover the absorption range of a triple junction tandem cell although some of the energy involved in a′ would be lost.

Figure 6 Intermediate band cell showing absorption processes which might be engineered to provide effective absorption of photons and carrier generation over a very wide range of energies Detailed balance calculations for an idealised case have been undertaken by Luque and Marti33 who show that assuming the cell has perfect contacts and is thick enough to assure complete absorption of the photons with enough energy to induce the transitions in Figure 6 the cell will outperform a tandem cell. They also make the assumption that there is no non-radiative recombination. This is somewhat unrealistic because of recombination via the intermediate band similar to a Shockley Hall Read process. Attempts to use impurities in silicon to produce the intermediate energy level in such solar cells have been notably unsuccessful. The negative effects of non-radiative recombination always outweigh the effects of increased absorption. This is largely predictable as such near mid gap

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impurity states tend to have low oscillator strength but are often powerful non radiative centres when present as point defects. Recently however two proposals have been put forward which may avoid this seemingly fundamental barrier and the most promising route ahead appears to be via nanomaterials. Macdonald et al34 have proposed locating the impurity band in a region of the cell which has a larger band gap than the base cell material. The effect of this is that the carriers generated by interaction of the photons with the mid gap impurity band are swept away from the impurity doped region and hence are spatially remote from the potential recombination path. Initial trials used Si implantation damage in a-Si deposited on Si as the optically active region. A very marked increase in absorption of below bandgap light (1100 to 1600nm) was observed but no additional carriers were delivered to the crystalline silicon. Luque et al35 have developed the model referred to above and applied it to an intermediate band prototype fabricated from InAs quantum dots in a GaAs matrix. The analysis shows evidence of splitting between the conduction and intermediate band quasi-Fermi levels, one of the basic hypotheses on which operation of such cells must depend. These ideas have been used by Wei and Forrest36 to consider Quantum dots embedded in an energy fence barrier to eliminate charge trapping and hence non-radiative recombination. A p+ i n+ cell with QDs buried in a high band gap barrier layer has been proposed and analyzed by them. The maximum solar power conversion efficiency under AM1.5 of a GaAs-based photovoltaic cell employing 10-20 layers of InAs QDs surrounded by a AlxGa1-xAs barriers in the depletion region is calculated to be as high as 45%. Higher efficiencies are anticipated for InP-based cells. Kechiantz et al37 have considered similar issues using an intermediate band effected with type II quantum dots in the Si/SiGe system. A barrier layer promoting the separation of the quasi-Fermi levels is modelled around the QDs. Conditions for the separation of the quasi-Fermi levels and the activation of the two-photon generation of mobile carriers were found. Under these conditions the photocurrent and the conversion efficiency of the Ge QD buried Si solar cell exposed to concentrated sunlight was postulated to be 25% larger than that of conventional Si solar cells. However such devices have not been realised in practice.

6.3

Quantum Cutting

In cases where the photon energy exceeds the band gap the difference in energy is lost in a conventional photovoltaic cell. The tandem cell moves towards solving this problem by the series combination of different gaps and of course in the limit the loss could be eliminated completely by an infinite number of band gaps. Even with a nanostructure to produce tuneable gaps it seems unlikely that this could be done economically. Figure 2 summarises the problem … essentially how do we capture the energies shown as ΔEe and ΔEh? Several proposals have been put forward. One of these is the process of quantum cutting. The term was introduced in relation to the luminescence of Eu3+ doped LiGdF4 where the excitation of Gd3+ with a vacuum UV photon resulted in two visible photons being emitted by Eu3+ through a two-step energy transfer from Gd3+ to Eu3+, with a quantum efficiency that approached 200 percent38. Early indications are that similar processes can occur in silicon nanocrystals at longer wavelenths. Timmerman et al39 have undertaken proof of principle experiments which result in the spatial separation of the two lower energy excitonic states so eliminating the very rapid Auger recombination and carrier cooling effects that normally occur. If this can be translated into a practical device it provides a potentially very effective way of using higher energy photons.

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6.4 Hot Electrons, Multiple Exciton Generation and Carrier Multiplication A process with a similar end result to the above but which is conceptually quite different is to utilize the hot carriers produced by absorption of above band gap photons directly. There are several possible ways to do this. If the higher energy electrons can be extracted an enhanced photo-voltage will be produced. This process necessitates the fabrication of selective energy contacts from which the higher voltage can be obtained. This might be accomplished using resonant tunnelling and although such schemes have been proposed and proof of concept of selective energy contacts has been demonstrated for double barrier resonant structures using Si quantum dots40 the problems of efficient extraction and electrical linkage to energy generated by the equilibrium carrier population have not been resolved. If the photon energy is sufficient a second electron–hole might be produced and if the bandgap energy is small enough then it is possible that many electron hole pairs could be generated. This approach was considered in silicon by Kolodinski et al41. They presented experimental evidence that the excess photon energy shown in Figure 2 can be utilized for the generation of a second electron/hole pair. The hot carriers of the primary electron/hole pair generate secondary pairs and so can result in a quantum efficiency exceeding unity. In their case they observed a quantum efficiency of 1.3 and propose a band structure which would optimise the effect. This process has attracted much interest recently and there is now overwhelming evidence that multiple electron hole pairs are produced in many materials and that the process is very effective in quantum dots42. What has emerged in recent publications is that the process can be very highly efficient even at low excitation densities43 and is extremely fast. This is very important if it is to compete effectively with other processes which might result in energy loss. Much work has focussed on PbS, PbTe and PbSe nanocrystals which have sufficiently low band gap for the effect to be of practical value in relation to the solar spectrum. The generation of eight excitons from a single photon has been observed and the threshold energy of the photon to produce two excitons need only be twice the band gap energy44. The process seems to be remarkably efficient in many nano materials including silicon45. It is evident that such processes have great potential and estimates of ultimate efficiencies have been suggested in the scientific press of such third generation cells achieving efficiencies of 80%. However the problem of extracting the carriers from the quantum dots and using them efficiently remains unsolved and presents considerable fundamental difficulties.

6.5

Organic Composites

Very remarkable success has been achieved in recent years in the development of organic light emitting diodes. This is a major factor in stimulating investment in small molecule organics and polymers for solar cells. The big attraction of these materials is that some of them can be made and deposited very cheaply, often from solution on flexible substrates and with a very low expenditure of energy. This is a major area of research and has been the subject of several comprehensive reviews and of journal special issues in recent years46-49. It is possible to produce organic and polymeric materials with appropriate band gaps for use as solar cell materials. These are often referred to as low band gap organics (sometimes called small molecule materials in this context) or polymers. The band gap in these materials is considered to be the difference between the highest occupied molecular orbital and the lowest unoccupied molecular orbital energy levels. The absorption spectra are distinctly different to conventional inorganic semiconductors and are typified by broad peaks rather than an abrupt absorption edge. As a result the utilisation of the solar spectrum is not as effective as inorganics of appropriate band gap. The

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absorbancy of the solar spectrum in organics is typically rather low and so thick layers are required to achieve appropriate absorption. This is a major problem as the low carrier mobility of organic materials results in unacceptable series resistance in thick layers. Early attempts at using organic materials were typified by very low efficiencies and rapid degradation. The present position50, 51 is that reasonable efficiencies have been demonstrated (~5%) and lifetimes of tens of thousands of hours although it seems that often the most efficient materials degrade quite rapidly and so it is not usual to obtain both long life and high efficiency in the same material at the present time. The degradation process has been the subject of a recent comprehensive review52 A promising approach which may go some way to resolving the conductivity and absorption problem is to combine nano particles with organic materials. Various material systems have been explored by several research groups. A very early report of reversible photoinduced electron transfer from poly[2-methoxy,5-(2'-ethyl-hexyloxy)-p-phenylene vinylene] (MEH-PPV) onto C60 was published by Sariciftci53 and has stimulated many investigations of C60, which can act as an acceptor of up to six electrons, in polymers and small molecule organics. This system has been reviewed by Davenas et al54 who has compared it with TiO2 nanoparticles in poly[vinylcarbazole] (PVK) and silver particles in MEH-PPV to provide enhanced charge separation by plasmon resonance at the metal/polymer interface. Alternative approaches include C60 with zinc-phthalocyanine55, polymers using graphene as the acceptor56. and poly phenyl azo methane thiophene (PPAT) using ZnO nano-particles57. These and related systems offer considerable promise but as yet have not shown the expected increase in efficiency over the engineered polymer devices referred to previously

6.6

Dye Sensitisation

The term sensitisation is used to convey the idea of separating the absorption process from the carrier transport process so that appropriate materials can be selected separately for the two functions. The approach has similarities to film based photography where the spectral response of silver halides is modified by the co-location of dyes which have absorption spectra in the visible part of the spectrum. Solar cells base on dye sensitisation have been pioneered by O’Regan and Grätzel58 but conceptually the subject is a very broad. It includes two disparate aspects: the general area of sensitisation, which can be achieved by organic dyes or by quantum dots, and the topic of photochemical cells59 which also embraces the idea of direct photo-generation of hydrogen. A sensitised cell uses a material to effect the absorption of a photon to form an exiton, a mechanism to separate the hole and electron constituting the exiton, and material(s) to transport the holes and electrons to contacts to the external circuit. There is in this system an important fundamental difference from the conventional photovoltaic cell in that not only can the materials be optimised for their specific function but if total separation of the hole and electron can be achieved at the absorber/conductor interface recombination can be eliminated and so the only competing process is the recombination of the exiton inside the absorber. If the extraction rate is very fast compared to this (and evidence in quantum dots and dye molecules suggests that this can be the case) then in principle the efficiency is only limited by the spectral absorbance. Grätzel’s early cells58 were based on a thin (~10μm) film of TiO2 particles (~15nm in size) coated with a monolayer of a trimeric ruthenium dye complex. TiO2 has a band gap of 3.2eV but the cell absorption onset was at 750nm (due to the dye) and wavelengths shorter than 550nm were almost completely absorbed resulting in 46% of the incident solar energy being used. The carrier transport mechanism was a result of an electron being transferred from the dye to the n-type TiO2 and the

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electron being replaced in the dye by an iodide/tri-iodide redox electrolyte. The cell voltage is the difference between the quasi-Fermi level in the TiO2 under illumination and the electrochemical potential of the electrolyte. For the cell described this is ~0.65V and an overall efficiency at AM1.5 at slightly less than one sun was ~7%. Numerous variants on dye sensitised cells exist and efficiencies greater than 10% have been achieved60. TiO2 appears to work well because of its large surface area for holding the dye however the close packed structure does not conduct well so this has led some groups to consider quantum wires. Law et al used a dense array of close packed ZnO nanowires which provides better conductivity but the overall efficiency reported61 was less (1.5%) than the TiO2 nano particle structure due to reduced absorbancy as a direct result of the involvement of less dye. Dye cells suffer from various degradation processes but probably the most vulnerable aspect is the electrolyte. Attempts are in progress to replace the liquid with a solid or stable gel. In general this reduces the rate that carriers can be replenished in the dye reducing the efficiency at higher intensities. However Wang et al62 have obtained efficiencies of ~7% with a “quasi-solid-state” electrolyte and it seems that further progress is likely. Dye sensitised cells are a very attractive system both from a commercial and scientific viewpoint and considerable investment is now being committed to this approach.

7.

Conclusions

It is evident that there is considerable political and commercial pressure to develop effective sources of solar energy. Photovoltaics have many advantages over other approaches and seem to have the potential to achieve high efficiencies for both distributed and central electricity generation. At the present time the market is dominated by wafer based silicon technologies but second generation cells using thin films at lower cost per watt are likely to take a significant market share as demand increases. Longer term, high efficiency cells must inevitably replace these first and second generation systems. Already concentrator cells with efficiencies > 40% have been fabricated and higher efficiencies seem possible although at the present time these use very expensive technologies. It is evident that the community is now searching for revolutionary approaches as the evolutionary approach can already be seen to yield diminishing returns in terms of performance and ultimately in cost per delivered kWh. Many new ideas have flooded the literature in the last few years most revolving around nanostructures and it would seem that some of these have the potential to provide very high efficiencies at low cost … an essential prerequisite to large scale adoption of photovoltaic energy generation. Should this happen it is then inevitable that a massive market for solar cells will develop with conservative estimates of the value of the solar materials market exceeding the present day requirements of the semiconductor industry by more than a factor of ten.

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Keywords Index B Beyond CMOS Bipolar Transistor

17 1

159

G GaAs GaInAs GaInP Ge

181 181 181 181

H Heterojunction History

1 1

I Integrated Circuits

1, 17

L Lattice Mismatch LED Lithography

27 159 17

M Market Volume Microelectronics Moore’s Law

17 1, 27 1

N Nanomaterial

181

O Optoelectronic Organic Semiconductor

27 159

P Photovoltaic (PV) Photovoltaic Diode

Quantum Dot CdSe

181

S

F FET

Q

181 159

Self-Organization Semiconductor Silicon Solar Strained Layer System on Chip (SoC)

17 1, 17 181 181 27 17

Authors Index B Bez, R.

Pirovano, A. 111

C Camerlenghi, E.

D Dąbrowski, J.

55

F Friend, R.

159

G Grimmeiss, H.

1, 17

I Inumiya, S.

55

K Kasper, E. Kozłowski, G.

1, 17, 27 55

L Lippert, G. Łupina, G.

55 55

M Markevich, V.P. Miyazaki, S. Müssig, H.J.

181 55 17, 55

N Nara, Y.

55

O Ohta, A. Ovchinnikov, I.V.

55 133

P Peaker, A.R. Pei, Y.

W Wang, K.L.

111

181 55

111

133