Advances in Communication, Signal Processing, VLSI, and Embedded Systems: Select Proceedings of VSPICE 2019 [1st ed. 2020] 978-981-15-0625-3, 978-981-15-0626-0

Table of contents :
Front Matter ....Pages i-xl
MEMS-Based IMU for Pose Estimation (Sheethal S. Bangera, T. D. Shiyana, G. K. Srinidhi, Yash R. Vasani, M. Sukesh Rao)....Pages 1-14
Data Flow Verification in SoC Using Formal Techniques (K. S. Asha, Oswald Sunil Mendonca, Rekha Bhandarkar, R. Srinivas)....Pages 15-24
Performance Analysis of Converter Circuit Transfer Function Model Using PID Control Algorithms (Rumana Ali, Vinayambika S. Bhat)....Pages 25-38
Design of Low-Power Active High-Pass Filter Using Operational Transconductance Amplifier (Sharil Nivitha Rodrigues, P. S. Sushma)....Pages 39-54
Green Communication in Wireless Body Sensor Network—A Review (P. Rachana, Durga Prasad)....Pages 55-67
Outage Performance Analysis of Hybrid FSO/RF System Using Rayleigh and K-Distribution (U. Anushree, V. K. Jagadeesh)....Pages 69-78
Development of Reliable On-Board Computer of STUDSAT-2 (Rakshith Devadiga, Sachin Kainthila, Abhishek Bangera, Amshak Shanbhogue, Durga Prasad, K. S. Shivaprakasha)....Pages 79-87
Design Techniques of Flash ADC: Review (Akshatha Kumary, Satheesh Rao)....Pages 89-95
Pedal Effects Modeling for Stringed Instruments by Employing Schemes of DSP in Real Time for Vocals and Music (D’Souza Dony Armstrong, Shastrimath V. Veena Devi, V. N. Ganesh)....Pages 97-113
Design and Development of Piezo-Stepping Voltage Drive for Piezoelectric Stack Actuator (Nutana Shetty, K. Sushith, Muralidhara)....Pages 115-126
Hybrid Feature Extraction Technique on Brain MRI Images for Content-Based Image Retrieval of Alzheimer’s Disease (K. Chethan, Rekha Bhandarkar)....Pages 127-141
Feature Selection from Gene Expression Data Using SVMRFE and Feed-Forward Neural Network Classifier (Nimrita Koul, Sunilkumar S. Manvi)....Pages 143-149
Implementation of SAR ADC for Biomedical Applications—A Review (Lavita Mendonca, Rekha Bhandarkar)....Pages 151-159
Energy-Efficient Communication Using Data Aggregation and Data Compression Techniques in Wireless Sensor Networks: A Survey (S. Pushpalatha, K. S. Shivaprakasha)....Pages 161-179
Spectrum Allocation Policies in Flexi-Grid Optical Networks (M. B. Sumalatha, L. M. Aishwarya, C. L. Triveni)....Pages 181-193
Novel Approach in IoT-Based Smart Road with Traffic Decongestion Strategy for Smart Cities (Padma Prasada, Sathisha, K. Shreya Prabhu)....Pages 195-202
Design and Development of Low-Cost Electronic Stethoscope Trainer Kit (Sukshith Shetty, Sukeerth Kumar)....Pages 203-212
Modified Hungarian User Pairing Method for NOMA-Based 5G Networks (Tadepalli Sri Bala Ragni, Pigilam Swetha, V. P. Harigovindan)....Pages 213-226
Adaptive Bi-threshold Algorithm for ECG Compression Based on Signal Slope (Y. Mahesha, B. L. Lavanya)....Pages 227-237
Design of Set D Flip-Flop and Scannable Set D Flip-Flop with Optimized Area (M. Pooja, Guruprasad S. Shetty, Vedantham Shabara Datta, M. Suchitra)....Pages 239-245
User Satisfaction-Based Resource Allocation in LTE-A (Jagadeesha R. Bhat, S. Anantha Kamath)....Pages 247-261
Secure Routing Protocol for MANET: A Survey (K. J. Abhilash, K. S. Shivaprakasha)....Pages 263-277
Improved HMM-Based Mixed-Language (Telugu–Hindi) Polyglot Speech Synthesis (M. Kiran Reddy, K. Sreenivasa Rao)....Pages 279-287
Energy Harvesting Using Raindrops Through Solar Panels: A Review (Shreya Shetty, Vibha Kishore, Sinaida Reeya Pinto, K. B. Bommegowda)....Pages 289-298
Transfer Learning for Classification of Uterine Cervix Images for Cervical Cancer Screening (Vidya Kudva, Keerthana Prasad, Shyamala Guruvare)....Pages 299-312
Skew Analysis on Multisource Clock Tree Synthesis Using H-Tree Structure (Vinayak Krishna Bhat, H. H. Surendra, H. R. Archana)....Pages 313-323
Review on Implementation of Fingerprint Verification System Using Image Inpainting (Milind B. Bhilavade, Meenakshi R. Patil, Lalita S. Admuthe, K. S. Shivaprakasha)....Pages 325-333
PWM Controlled Solenoid Valves for Automatic Gear Change in Four-Wheelers (M. R. Anusha, M. G. Veena)....Pages 335-344
Literature Survey on Emotion Recognition for Social Signal Processing (A. Vijayalakshmi, P. Mohanaiah)....Pages 345-360
Low-Power Analysis of Full Adder and Subtractor Design Using Adiabatic Logic Styles ( Akshitha, Niju Rajan)....Pages 361-383
Design and Implementation of Multiple-Output CMOS Voltage Level Shifter (S. Swaroop, K. S. Ravindra)....Pages 385-401
Design and Development of Multi-output Isolated Supply for SiC MOSFET Gate Driver Using Flyback Topology (C. Shreya, G. Praveen Kumar, Vikhyath D. Amin, K. Suryanarayana)....Pages 403-418
Design of Error Correction Engine Based on Flexible Unequal Error Control Code (FUEC) for Flash Memory Faults in Space Applications (G. Amrutha Shree, Veena S. Chakravarthi)....Pages 419-431
Analysis of Cryptographic Algorithms for Secured Data Transmission in VANETs (Kalkundri Ravi, Rajashri Khanai, Kalkundri Praveen)....Pages 433-443
Classification of Landsat 8 Imagery Using Kohonen’s Self Organizing Maps and Learning Vector Quantization (B. R. Shivakumar, S. V. Rajashekararadhya)....Pages 445-462
Solar Based Inverter Design: A Brief Review (A. Vishwitha, Anil Kumar Bhat)....Pages 463-469
Two-Way Image Based CAPTCHA (M. Poornananda Bhat, Rashmi Naveen Raj)....Pages 471-483
Performance Comparison of Semi-Z-Source Inverter and Full-Bridge Inverter (M. Megha, V. Ansal)....Pages 485-501
Control Loop Design of DC–AC Power Supply with High Crest Factor Nonlinear Loads (Prajwal Puranik, M. Ashwini Kumari, K. Suryanarayana, K. Krishna Prasad)....Pages 503-518
Fuzzy Logic Controller for Indirect Vector Control of Induction Motor (Girisha Joshi, Pinto Pius A J)....Pages 519-534
Stability Improvement Using SSSC in Synchronous Generation System with PMSG-Based Offshore Wind Farm ( Chethan HR, R. Mageshvaran)....Pages 535-546

Citation preview

Lecture Notes in Electrical Engineering 614

Shubhakar Kalya Muralidhar Kulkarni K. S. Shivaprakasha   Editors

Advances in Communication, Signal Processing, VLSI, and Embedded Systems Select Proceedings of VSPICE 2019

Lecture Notes in Electrical Engineering Volume 614

Series Editors Leopoldo Angrisani, Department of Electrical and Information Technologies Engineering, University of Napoli Federico II, Naples, Italy Marco Arteaga, Departament de Control y Robótica, Universidad Nacional Autónoma de México, Coyoacán, Mexico Bijaya Ketan Panigrahi, Electrical Engineering, Indian Institute of Technology Delhi, New Delhi, Delhi, India Samarjit Chakraborty, Fakultät für Elektrotechnik und Informationstechnik, TU München, Munich, Germany Jiming Chen, Zhejiang University, Hangzhou, Zhejiang, China Shanben Chen, Materials Science and Engineering, Shanghai Jiao Tong University, Shanghai, China Tan Kay Chen, Department of Electrical and Computer Engineering, National University of Singapore, Singapore, Singapore Rüdiger Dillmann, Humanoids and Intelligent Systems Lab, Karlsruhe Institute for Technology, Karlsruhe, Baden-Württemberg, Germany Haibin Duan, Beijing University of Aeronautics and Astronautics, Beijing, China Gianluigi Ferrari, Università di Parma, Parma, Italy Manuel Ferre, Centre for Automation and Robotics CAR (UPM-CSIC), Universidad Politécnica de Madrid, Madrid, Spain Sandra Hirche, Department of Electrical Engineering and Information Science, Technische Universität München, Munich, Germany Faryar Jabbari, Department of Mechanical and Aerospace Engineering, University of California, Irvine, CA, USA Limin Jia, State Key Laboratory of Rail Traffic Control and Safety, Beijing Jiaotong University, Beijing, China Janusz Kacprzyk, Systems Research Institute, Polish Academy of Sciences, Warsaw, Poland Alaa Khamis, German University in Egypt El Tagamoa El Khames, New Cairo City, Egypt Torsten Kroeger, Stanford University, Stanford, CA, USA Qilian Liang, Department of Electrical Engineering, University of Texas at Arlington, Arlington, TX, USA Ferran Martin, Departament d’Enginyeria Electrònica, Universitat Autònoma de Barcelona, Bellaterra, Barcelona, Spain Tan Cher Ming, College of Engineering, Nanyang Technological University, Singapore, Singapore Wolfgang Minker, Institute of Information Technology, University of Ulm, Ulm, Germany Pradeep Misra, Department of Electrical Engineering, Wright State University, Dayton, OH, USA Sebastian Möller, Quality and Usability Lab, TU Berlin, Berlin, Germany Subhas Mukhopadhyay, School of Engineering & Advanced Technology, Massey University, Palmerston North, Manawatu-Wanganui, New Zealand Cun-Zheng Ning, Electrical Engineering, Arizona State University, Tempe, AZ, USA Toyoaki Nishida, Graduate School of Informatics, Kyoto University, Kyoto, Japan Federica Pascucci, Dipartimento di Ingegneria, Università degli Studi “Roma Tre”, Rome, Italy Yong Qin, State Key Laboratory of Rail Traffic Control and Safety, Beijing Jiaotong University, Beijing, China Gan Woon Seng, School of Electrical & Electronic Engineering, Nanyang Technological University, Singapore, Singapore Joachim Speidel, Institute of Telecommunications, Universität Stuttgart, Stuttgart, Baden-Württemberg, Germany Germano Veiga, Campus da FEUP, INESC Porto, Porto, Portugal Haitao Wu, Academy of Opto-electronics, Chinese Academy of Sciences, Beijing, China Junjie James Zhang, Charlotte, NC, USA

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Shubhakar Kalya Muralidhar Kulkarni K. S. Shivaprakasha •

•

Editors

Advances in Communication, Signal Processing, VLSI, and Embedded Systems Select Proceedings of VSPICE 2019

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Editors Shubhakar Kalya Singapore University of Technology and Design Singapore, Singapore

Muralidhar Kulkarni National Institute of Technology Karnataka Mangalore, Karnataka, India

K. S. Shivaprakasha Department of Electronics and Communication Engineering N.M.A.M. Institute of Technology, Nitte Karkala, Karnataka, India

ISSN 1876-1100 ISSN 1876-1119 (electronic) Lecture Notes in Electrical Engineering ISBN 978-981-15-0625-3 ISBN 978-981-15-0626-0 (eBook) https://doi.org/10.1007/978-981-15-0626-0 © Springer Nature Singapore Pte Ltd. 2020 This work is subject to copyright. All rights are reserved by the Publisher, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed. The use of general descriptive names, registered names, trademarks, service marks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use. The publisher, the authors and the editors are safe to assume that the advice and information in this book are believed to be true and accurate at the date of publication. Neither the publisher nor the authors or the editors give a warranty, expressed or implied, with respect to the material contained herein or for any errors or omissions that may have been made. The publisher remains neutral with regard to jurisdictional claims in published maps and institutional affiliations. This Springer imprint is published by the registered company Springer Nature Singapore Pte Ltd. The registered company address is: 152 Beach Road, #21-01/04 Gateway East, Singapore 189721, Singapore

Preface

We are glad that Department of Electronics and Communication Engineering and Department of Electrical and Electronics Engineering are jointly organizing International Conference on “VLSI, Signal Processing, Power Systems, Illumination and Lighting Control, Communication and Embedded Systems” (VSPICE-2019) during 23–24 May 2019 at N.M.A.M. Institute of Technology, Nitte. VSPICE-2019 is part of a multi-conference under the aegis of ICETE-2019. The VSPICE-2019 is patronized by Indian Space Research Organization (ISRO), with Springer as the publication partner. The main goal of the conference is to share and enhance the knowledge of the academicians, researchers and industry professionals. The conference aims to bridge the researchers working in academia and other professionals through research presentations and keynote addresses in current technological advances. The conference is also associated with a one-day preconference tutorial on machine learning on 22 May 2019. The organizing committee has worked extremely hard to make VSPICE-2019 an outstanding conference. We have received a total of 137 papers, and 41 papers are selected for presentation following a rigorous review process. Our sincere acknowledgements to ISRO for funding the conference under RESPOND scheme and Springer for the publication of the selected conference papers. We wish all the participants a very pleasant stay and excellent learning atmosphere at Nitte campus.

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Preface

Programme Chairs, VSPICE-2019

Dr. Rekha Bhandarkar Professor and Head Department of Electronics and Communication Engineering N.M.A.M. Institute of Technology Nitte, India

Dr. Nagesh Prabhu Professor and Head Department of Electrical and Electronics Engineering N.M.A.M. Institute of Technology Nitte, India

Message from Dr. Niranjan N. Chiplunkar

I am very happy to note that the Departments of Electronics and Communication and Electrical and Electronics at N.M.A.M. Institute of Technology, Nitte, are jointly organizing an International Conference on “VLSI, Signal Processing, Power Systems, Illumination and Control, Communication and Embedded Systems (VSPICE-2019)”, under the broad banner of the multi-conference titled “International Conference on Emerging Trends in Engineering (ICETE-2019)”. I understand that a good number of technical papers were received for VSPICE-2019, and after careful scrutiny by eminent experts, only quality papers have been selected for the oral presentation. During the conference, the delegates will get an opportunity to listen and interact with the eminent invited speakers. Networking with peers from different parts of the globe is another benefit of such conference. Participation of Padma Bhushan Dr. B. N. Suresh as the inaugurator and keynote speaker has really added value to this conference. I congratulate the whole team of VSPICE-2019 for their splendid work, wishing the conference every success. Dr. Niranjan N. Chiplunkar Principal N.M.A.M.I.T. Nitte

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Message from Dr. I. R. Mithanthaya

N.M.A.M. Institute of Technology started its first International Conference on Emerging Trends in Engineering (ICETE) from 2011 with an intention to provide platform for post-graduation and research scholars of engineering and technology and industry professionals to deliberate, explore and contribute their research findings. Since eight years, this conference attracted many researchers with scholarly contributions. Under this platform, I am very happy to know that Department of Electronics and Communication Engineering and Department of Electrical and Electronics Engineering, N.M.A.M.I.T., Nitte, are organizing International Conference on “VLSI, Signal Processing, Power Systems, Illumination and Control, Communication, and Embedded Systems” (VSPICE-2019) which is scheduled on 23 and 24 May 2019. The main objective of this international conference is to provide a platform for people who are working in electrical, electronics, communications and allied disciplines to share their expertise and contribute to technical innovations. I came to know that department received a very good response from India and abroad with 130+ papers and 41 papers were selected for presentation after critical review. I am also happy to hear that during the conference eminent keynote speakers from reputed organizations and Industries as well as from foreign

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Message from Dr. I. R. Mithanthaya

universities will share their experiences. I am also happy to note that a one-day pre-conference tutorial by Dr. Ashok Rao, Former Network Head, CEDT, IISc, Bangalore, covering the insight into the conference themes is organized on 22 May 2019. I appreciate the efforts taken by Programme Chairs of VSPICE-2019, Dr. Rekha Bhandarkar and Dr. Nagesh Prabhu and their team in making this conference a truly international conference with high-quality standard technical papers. In summary, the members of the Programme Committee have put all efforts to make this conference, truly an international one with quality papers on board. I congratulate all members of Programme Committee for their effort and hard work. I wish the programme every success.

Dr. I. R. Mithanthaya Vice Principal and Dean (Academics) N.M.A.M.I.T. Nitte

Message from Dr. B. R. Shrinivasa Rao

I am pleased to know that the Department of Electronics and Communication Engineering and Department of Electrical and Electronics Engineering, N.M.A.M. Institute of Technology, Nitte, are organizing a two-day international conference on “VLSI, Signal Processing, Power Systems, Illumination and Lighting Control, Communication and Embedded Systems (VSPICE-2019)” under the aegis of ICETE-2019: International Conference on Emerging Trends in Engineering on 23 and 24 May 2019. I congratulate the organizers of VSPICE-2019 for providing a platform to bring together researchers and practitioners from academia and industry to focus on recent systems and techniques in the broad field of electronics, communication and

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Message from Dr. B. R. Shrinivasa Rao

electrical engineering. I am sure the conference will be an incentive for the participants from various levels and will be useful and informative for all. I convey my best wishes for the success of the conference.

Dr. B. R. Shrinivasa Rao Vice Principal and Controller of Examinations email: [email protected]

Message from Dr. Sudesh Bekal

The ICETE conference series has changed its shape to become a multi-conference with five conferences being run parallel. VSPICE-2019, the International Conference of Electronics and Communication Engineering and Electrical and Electronics Engineering Departments, is planning to bring out the compendium of abstracts containing information about large number of papers received for presentation. It is a great effort on the part of conveners, and I am appreciative of the fact. It is worthwhile to note that with too much of specialization in every branch of engineering, it is meaningless to have single conference catering to all. This ICETE-2019 multi-conference is the big step in the right direction, what with so many experts and speakers available at hand with participants and researchers. I congratulate the editors and the editorial team for coming out with this compendium and wish conveners and office bearers of VSPICE-2019 all the best. Dr. Sudesh Bekal Dean (R&D)/Convener ICETE-2019 Multi-Conference

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About N.M.A.M. Institute of Technology, Nitte

N.M.A.M. Institute of Technology, Nitte, was established in 1986. The college is affiliated to the Visvesvaraya Technological University, Belagavi, and is recognized by the All India Council for Technical Education, New Delhi. Institute is accredited by National Assessment and Accreditation Council (NAAC) with ‘A’ grade with a CGPA of 3.11 out of 4 till 20 October 2022. Seven UG programmes, i.e. B.E. (Civil), B.E. (E&E), B.E. (BT), B.E. (Mech), B.E. (CS), B.E. (IS) and B.E. (EC), are accredited by NBA, New Delhi, under Tier-I category till 30 June 2021. Institute is certified to the ISO 9001:2015 standards for quality education by NVT Quality Certifications (ANAB accredited). The institution has been granted Academic Autonomy under the Visvesvaraya Technological University from 2007 to 08. The annual intake of students is 1080 for UG and 518 for PG, with over 5000 students studying in the campus. N.M.A.M. Institute of Technology, Nitte, offers undergraduate programme in seven disciplines of engineering, viz. civil engineering, electrical and electronics engineering, electronics and communication engineering, computer science and engineering, information science and engineering, mechanical engineering and biotechnology. The specializations in postgraduate (M.Tech.) programme include construction technology, structural engineering, machine design, energy system engineering, power electronics, digital electronics and communication, VLSI design and embedded systems, computer science and engineering, computer network engineering, software engineering and industrial biotechnology. All the departments have been recognized as research centres for offering M.Sc. (Engineering) and Ph.D. programmes under VTU. The institute also offers postgraduation and research programmes in computer applications and business management along with Ph.D. programmes in basic science and mathematics. Principal of NMMAIT, Prof. (Dr.) Niranjan N. Chiplunkar, holds a doctorate in computer science and engineering from the University of Mysore and has over 30 years of teaching experience. He was bestowed with the “Excellent Achievement” award by the Centre for International Cooperation on Computerization (CICC), Government of Japan (2002) and Bharateeya Vidya Bhavan’s “Best Engineering College Principal” award by ISTE, New Delhi (2014). NMAMIT has established a xv

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About N.M.A.M. Institute of Technology, Nitte

Research and Innovation Centre (RIC) with 8000 ft2 of laboratory space to promote research and innovation. It houses the research facilities like Centre for Tool Based Micromachining Research, Centre for Condition Monitoring Research, Centre for Advanced Machining Research, Centre for Research on Vibration Isolation System, Centre for System Design, Fabrication and Testing, Centre for I.C. Engine Research, Centre for High Performance Computing, Biofuel Information and Demonstration Centre, Centre for Innovation in Biofuel Production. A new start-up eco-space with 7000 ft2 area is coming up and will be ready by end of December 2018, which will have co-working space and all the infrastructural facilities that will allow young incubators to start their ventures. The mentorship and the help to get the financial support will be extended through this facility. The Department of Science and Technology (DST), Government of India, established the Entrepreneurship Development Cell (EDC) at NMAMIT in 2004 to conduct training programmes to promote development of business ventures/ small-scale industries/micro-enterprises and promote employment opportunities in the region as well as to create entrepreneurial culture in institutions and colleges in and around Nitte. Students are encouraged to start their own ventures, and all necessary help and guidance are given. A Vocational Training Centre has been established at NMAMIT in association with the Directorate of Industries and Commerce, Bangalore, with the objective of enhancing the employability of uneducated youth by providing the required training. Karnataka Biotechnology and Information Technology Services (KBITS), an autonomous organization established under the Department of Information Technology and Biotechnology, Government of Karnataka, has selected NMAMIT as one of the first nine engineering colleges for “Karnataka New Age Incubation Network”. The college has a MoU with Penn State University, Harrisburg, USA, and Ritsumeikan University, Japan, for faculty and student exchange programmes, with respect to research and projects. Department of Biotechnology has a collaboration with the National University of Singapore for training their students in the advanced areas.

About ICETE-2019

The Ninth International Conference on Emerging Trends in Engineering (ICETE-2019, A multi conference platform) will be held on 23 and 24 May 2019 at N.M.A.M. Institute of Technology, Nitte, Karnataka. The idea of multi-conference platform has been mooted in order to focus on the specific issues associated with various engineering fields. N.M.A.M. Institute of Technology, Nitte, has been organizing International Conference on Emerging Trends in Engineering (ICETE) annually since 2011. ICETE aimed to provide a proper platform for research scholars, postgraduate students of engineering and technology and industry professionals to deliberate, explore and contribute their research findings and to discuss the latest developments in the field of engineering and technology. Invited technical talks by eminent personalities from IIT and Foreign Universities on current topics of relevance in different streams of engineering were also organized to help the participants in upgradation of their knowledge about the recent advances in engineering and technology. This year, ICETE-2019—A Multi Conference Platform, will be held as a collection of several international conferences with themes specific to different engineering streams organized under a single umbrella.

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About VSPICE-2019

Department of Electronics and Communication and Department of Electrical and Electronics Engineering, N.M.A.M. Institute of Technology, Nitte, India, are organizing a two-day international conference on “VLSI, Signal Processing, Power Systems, Illumination and Lighting Control, Communication and Embedded Systems” (VSPICE-2019) as a part of multi-conference on International Conference on Emerging Trends in Engineering (ICETE-2019) on 23 and 24 May 2019. Advances in VLSI, Signal Processing, Power Systems, Illumination and Lighting Control, Communication and Embedded Systems pave a pathway for the development of efficient and economic systems. For making the best use of resources, expertise in multiple specializations and interdisciplinary research is gaining prominence. Hence, the objective of the conference is to provide a platform for people who are working in electrical, electronics, communications and allied disciplines to share their expertise and contribute to technical innovations. The conference is dedicated to driving innovation in nearly every aspect of electronics and communication and electrical engineering. The conference provides platform for researchers, professionals, executives and practicing engineers from various industries, research institutes and educational bodies to share and exchange their ideas on the theme of the conference. A series of keynote presentations and technical paper presentations are planned to discuss new issues, tackle complex problems and find advanced enabling solutions which are able to shape new trends and enable the development of mankind as a whole.

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VPSICE-2019: Committees

Programme Chairs Dr. Rekha Bhandarkar, Professor and Head, Department of Electronics and Communication Engineering Dr. Nagesh Prabhu, Professor and Head, Department of Electrical and Electronics Engineering

Coordinators Dr. K. S. Shivaprakasha, Associate Professor, Department of Electronics and Communication Engineering Mr. Raghavendra Prabhu, Assistant Professor, Department of Electrical and Electronics Engineering

Track Chairs Communication Illumination and Lighting Control Power Systems Signal Processing VLSI and Embedded Systems

Dr. V. Veena Devi Shastrimath, Professor, Department of ECE Dr. M. Satyendra Kumar, Professor, Department of EEE Dr. K. Suryanarayana, Associate Professor, Department of EEE Dr. Subramanya Bhat, Associate Professor, Department of ECE Dr. Krishnanada Shet, Associate Professor, Department of ECE

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VPSICE-2019: Committees

Publication Committee Chair Dr. K. S. Shivaprakasha, Associate Professor, Department of ECE

Members Mr. K. Mahaveera, Assistant Professor, Department of ECE Mr. Pradeep Kumar, Assistant Professor, Department of EEE Dr. Anitha M. Colaco, Assistant Professor, Department of EEE

Web Committee Chair Mr. B. R. Shivakumar, Assistant Professor, Department of ECE

Members Mr. M. J. Dileep Kumar, Assistant Professor, Department of ECE Mr. Raghavendra Prabhu, Assistant Professor, Department of EEE

Publicity Committee Chair Dr. K. V. S. S. S. S. Sairam, Professor, Department of ECE

Members Mr. K. B. Bommegowda, Assistant Professor, Department of ECE Mrs. Nayana P. Shetty, Associate Professor, Department of EEE Mr. Ravikiran Rao, Assistant Professor, Department of EEE

VPSICE-2019: Committees

Sponsorship Committee Chair Dr. A. G. Ananth, Professor, Department of ECE

Members Dr. Prabha Niranjan, Assistant Professor, Department of ECE Mr. K. V. Shettigar, Associate Professor, Department of EEE Mrs. Swathi Hatwar, Assistant Professor, Department of EEE

Transportation and Accommodation Committee Chair Mr. Durgaprasad, Associate Professor, Department of ECE

Members Mr. Karthik, Assistant Professor, Department of ECE Mr. Prajwal Hegde, Assistant Professor, Department of ECE Mrs. Amrutha Pai, Assistant Professor, Department of ECE Ms. Harshitha Bhat, Assistant Professor, Department of ECE Mr. J. Naveen, Assistant Professor, Department of EEE Mr. Abdul Raheman, Assistant Professor, Department of EEE

Event Management Committee Chair Mrs. Sunitha Lasrado, Assistant Professor, Department of ECE

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VPSICE-2019: Committees

Members Ms. R. Anusha, Assistant Professor, Department of ECE Mrs. N. Shankari, Assistant Professor, Department of ECE Mrs. Vaishali Y. Suvarna, Assistant Professor, Department of ECE Mr. Dinesh Shetty, Assistant Professor, Department of EEE Mrs. Raksha Adappa, Assistant Professor, Department of EEE

Keynote Speaker

Dr. B. N. Suresh Dr. B. N. Suresh is presently Chancellor, Indian Institute of Space Science and Technology, Thiruvananthapuram, and Honorary Distinguished Professor at ISRO HQ, Bangalore. He is Chairman, Governing Council, MVJ College of Engineering, Bangalore, and Vice Chairman, Design Division of Aeronautical Society of India, Mumbai. He was President for Indian National Academy of Engineering (INAE), Delhi, a premier Engineering Academy of the Country for 4 years and also he was Member of Board of Governors of IIT Madras for 7 years. After his degree in Science and Engineering from Mysore University, he obtained his postgraduate degree from IIT Madras. He received his doctorate under Commonwealth Scholarship in Control Systems from Salford University, UK. He joined Vikram Sarabhai Space Centre, Trivandrum, in 1969 and discharged several responsibilities before taking over as Director, Vikram Sarabhai Space Centre in 2003 and served four and half years till the end of November 2007. He took over as Founder Director for the newly established Indian Institute of Space Science and Technology (IIST) at Thiruvananthapuram in 2007 and served for three and half years. He was instrumental in establishing this world-class Institution. He was Member, Space Commission, for four years. He served as Vikram Sarabhai

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Keynote Speaker

Distinguished Professor for 5 years from 2011. He was also Distinguished Professor at IIT Bombay and MIT Manipal. He is Fellow of several professional bodies like Indian National Academy of Engineering (INAE), Indian National Science Academy (INSA), New Delhi, Astronautical Society of India (ASI), Aeronautical Society of India (AeSI), Indian Society of systems for Science and Engineering (ISSE) and International Academy of Astronautics (IAA) at Paris. He is also Fellow and past President for System Society of India (SSI). He is well recognized internationally too. He was Head of Indian delegation for the United Nations Committee for space on Peaceful Uses of Outer Space at Vienna, Austria, during 2004–07. He was elected as Chairman of the prestigious United Nations Scientific and Technical Committee for the year 2006 from the Asia-Pacific Countries. This was a unique distinction, since from the inception of UN Committee a technical expert from a developing country was selected for this coveted post. He was Vice-President for S and T Committee for International Academy of Astronautics (IAA), Paris, and Chairman for the selection of members in S and T area for IAA for five years. He was selected by the International Astronautical Federation to Chair for Programme Committee for the International Astronautical Congress in 2007. He has delivered several prestigious guest lectures like Ramanujam memorial, Vikram Sarabhai memorial, Dr. Srinivasan memorial, Satish Dhawan memorial, Raman memorial lecture and many more in prominent institutions and national conferences. He has given invited lectures at several international institutions like European Space Policy Institute, Paris, Space Institute at Strasbourg, United Nations conferences at Vienna, NASA conference on Project Management at Houston, USA, Jet Propulsion Laboratory, Los Angeles and many more. He has received several awards and honours and prominent among them are “Dr. Biren Roy Space Science Design Award” from Aeronautical Society of India, Agni Award from DRDO for achieving the self-reliance, “ASI Award” for contribution to space technologies, by Astronautical Society of India. Distinguished Alumni Award from IIT Madras, Ramanujam Award by PSG Institute of Technology for System Engineering, Technical Excellence Award by Lions International, Outstanding Achievement Award by Department of Space, Government of India, Lifetime Contribution Award in engineering by Indian National Academy of Engineering (INAE) for his significant contributions for space technologies, National Systems Gold Medal for lifetime contributions to large systems from System Society of India, Aryabhata Award the highest award by Astronautical Society for his invaluable contributions for aerospace developments, Karnataka State Rajyotsava Award for 2014 for Science and Technology, the top award from Government of Karnataka, MR Kurup Endowment Award by Centre for Indian Consumers Research, Thiruvananthapuram, Lifetime Achievement Award from Karnataka State Science and Technology Academy in 2015, “Sir M. Visvesvaraya Science Award, by the Karnataka Branch of “Vijnana Bharathi” in 2016, Lifetime Achievement Award by ISRO, Government of India, in 2016, in recognition of lifetime contributions to the Indian Space Programme.

Keynote Speaker

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Recently, he was awarded Global Pioneer Award by International Council of System Engineering at Washington, DC, USA, in July 2018 for his pioneering contributions to space system engineering. In recognition of his meritorious contributions for science and technology, Government of India, conferred on him Padma Shree during the year 2002 and third highest civilian Award Padma Bhushan during the year 2013. Abstract of the Talk on “Advanced Electronics in Aerospace and Future Trends” The electronics used in space systems have to function with zero defect, as most of the electronics systems are autonomous and any failure leads often to mission failure. In both launch vehicles and spacecraft, the important functions of the navigation, guidance and control, telemetry, telecommand, power are implemented by using highly reliable electronics. While commercial electronics is by and large technology oriented, the space avionics is reliability oriented and has to perform its duty without any failure. In spacecraft, the on-board electronics has to function more than 12–15 years without any break. The aerospace systems use VLSI, signal processing, power, communication and embedded systems to carry out all defined functions as detailed above. Many times, they have to function under a hostile environment of space with different temperature, vibration, shock, acoustics and EMI. The design of aerospace electronics is quite complex, with constraints of mass, space and device and specific requirement of functional integration. The RF systems in the aerospace systems are used for vehicle tracking, telemetry and telecommand. On-board video imaging system is used in to obtain the data on the separation of stages, spacecraft, etc., and consists of video compression unit, ruggedized camera and illumination source. The power source, in these systems, uses Ag–Zn batteries and Li–ion batteries, for improved energy density and overall reduction in weight and volume. The talk presents the overall electronics architecture, complexities, the design features and also the elaborated test methodologies used to ensure high reliability. The future perspectives of electronics in terms of SOS, where a large amount of functionality is integrated onto a single monolithic chip and MCM where multiple chips mounted on a common substrate and their overall functional integration aspects are also included.

Invited Speakers

Dr. C. P. Ravikumar C. P. Ravikumar is presently Technical Director, Technical Talent Development at Texas Instruments, India. He leads the TI India Technical University which provides learning opportunities to employees of TI India. His earlier roles in TI include Director of University Relations and Senior Technologist (VLSI Test). He is also Adjunct Faculty at IIT Madras. Before joining TI India in 2001, he was Professor of Electrical Engineering at the Indian Institute of Technology (1991–2001). He also held a visiting position (1995–1996) and the position of Vice-President (Training) at ControlNet India Pvt. Ltd (2000–2001). He obtained his Ph.D. (Computer Engineering) from the University of Southern California (1991), M.E. in Computer Science with highest scores from Indian Institute of Science (1987) and B.E. in Electronics with a Gold Medal from Bangalore University (1983). He has published over 200 papers in leading international conferences and journals. He founded the VLSI Design and Test Symposium (VDAT) and was General Chair of this event for 15 years, from its inception in 1998 to 2011. He is

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Author/Editor/Coauthor of over 12 books in areas of VLSI and has contributed several chapters. He is Editor of the Journal of VLSI and Electronic System Design and on the editorial board of the Journal of Electronic Testing: Theory and Applications and the Journal of Low Power Electronics. He has won the best paper award at IEEE International Conference on VLSI Design (2002) and VLSI Test Symposium (2005). He is Senior Member of IEEE, Honorary Secretary of IEEE-CAS Bangalore chapter (2004–current) which he founded and Honorary Secretary of VLSI Society of (2003–2011). He received an award from Zinnov for his work on ecosystem development in India (universities). He is now the Vice Chair of the IEEE Bangalore Section. Abstract of the Talk on “Building Smart Systems for the Future: Challenges and Opportunities” We are beginning to see the emergence of a brave new world where machine learning and artificial intelligence are becoming embedded in electronic devices. Smart devices can help in providing better value-added services to the end-user; at the same time, these devices are easier to monitor over the Internet. Such devices have become possible due to relentless improvements in VLSI technology, better EDA software and innovative design techniques. From a hardware perspective, availability of low-power processor nodes, sensors, low-power wireless communication has driven the revolution. From a software viewpoint, cloud computing, edge computing, data analytics, machine learning and artificial intelligence have contributed to the success of smart devices. For example, smart street lights can optimize the usage of power by providing illumination on demand. There is an estimate that 10 billion smart devices were sold in 2018 and that this market continues to grow. In this talk, we will go over this story from the viewpoint of both the possibilities these technologies open up as well the technical and social challenges they have created. Plenty of innovation, hard work and teamwork will be needed to harness the benefits offered by a smart and networked world. The teaching of electronics, communication and computer engineering in colleges across the world is changing to get students better prepared for a smart world. A system perspective will be essential for gaining better opportunities in the coming years.

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Dr. Shubhakar Kalya Dr. Shubhakar Kalya obtained his master’s degree in microelectronics from Indian Institute of Science (IISc), Bangalore, India, in 2007 and Ph.D. degree in the field of nanoelectronics from School of Electrical and Electronics Engineering, Nanyang Technological University (NTU), Singapore, in 2012–13. He obtained his Bachelor’s Degree in Electronics and Communication Engineering from NMAMIT, Nitte. He is working as Faculty in Engineering Product Development (EPD) Pillar at Singapore University of Technology and Design (SUTD), Singapore, since January 2012. His research work focuses on the nanoscale characterization of high-j gate dielectrics and 2D materials for advanced logic and memory devices and its reliability analysis. During July 2009 to December 2012, he has worked as Visiting Researcher at Institute of Materials and Research Engineering (IMRE), Singapore, and involved in research related to the characterization of high-j gate dielectrics using scanning tunnelling microscopy and atomic force microscopy. During January–June 2017, he was at Massachusetts Institute of Technology (MIT), Cambridge, USA, as Visiting Scientist. He has authored/co-authored more than 30 research publications (journals/international conferences) and two chapters. He is also involved in the review of various technical papers including IEEE Transactions on Device and Materials reliability, Microelectronic Engineering journals and international conferences related to nanoelectronics field. Abstract of the Talk on “Convergence of Fundamental and Applied Research in Advanced Electronics Engineering Field: Necessity and Challenges” In general, research work comprises new, creative and systematic work undertaken to increase knowledge and to uncover interesting and new facts. Moreover, the research findings can be directly applied to real-world applications, such as improving the functionality of systems and development of novel devices/elements and structures in different engineering fields. Important categories of research work/method can be considered as fundamental (basic) research and applied research. Fundamental research focuses on seeking answers to fundamental knowledge and its advancement, creating supporting theories that explain observed phenomena and better understanding of the fundamental concepts. Applied research

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refers to scientific study that seeks to solve practical problems. This type of research plays an important role in the development of innovative techniques and technologies. The applied research also tends to have a much narrower focus with a specific field with commercial interest. The fundamental research can provide the foundation for the applied research. Both the fundamental and applied researches are equally important and can be closely related. In the last few decades, electronics engineering field is one of the highly developed and rapidly evolving engineering disciplines. Recently, we have seen massive innovative changes in electronic devices, circuits and products with respect to size, operational speed and power consumption. Nanoelectronics is an exciting field which offers electronic technological innovation primarily due to the development of new tools that have made the characterization and manipulation of nanostructures practical and also as a result of new methods of preparation of these devices at the nanoscale. In addition, the development in the field of nanoelectronics offers opportunities in different domains of nanotechnological research such as nanosensors, nanomedicine, clean water and energy sources. In this presentation, we discuss the importance of convergence of the fundamental research and applied research in the advanced electronics engineering field and addressing the key challenges.

Preconference Tutorial

Dr. Ashok Rao Dr. Ashok Rao holds a B.E., M.E. and Ph.D. all in Electrical Engineering from Mysore University (1982), Indian Institute of Science, Bangalore (1985), and Indian Institute of Technology, Bombay (1991), respectively. He specializes in digital signal processing area and is known to be one of the leading figures in this area in India. In addition, he teaches and researches in areas of image processing, multimedia, linear algebra, renewable energy, bio-metrics, appropriate technology and sustainable development, management, archaeology, education and academic reforms and ICT. He has over 30 years of Teaching and Research Experience which Includes: 6 years in IIT Bombay, 7 years in IISc Bangalore, 4 years in NITK Surathkal, the rest in various places in India, Guided Ph.D.’s both in E&C and Computer Science areas and has over 100 publications. He is also Solar Photovoltaic (SPV) Specialist having been trained by Siemens Solar California during 1996–1997. Earlier he was Head, Network Project at CEDT, IISc Bangalore, from 1999 to 2005. It was a project funded by Swiss Agency for Development and Cooperation (SDC) and

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covered E&C Engineering education in whole of South India (Karnataka, Tamil Nadu, Andhra Pradesh and Kerala). He is also Entrepreneur having successfully started and managed several IT and renewable energy companies during 1998– 2011. About Preconference Tutorial on “Machine Learning” This tutorial aims to cover a broad outline of the popular topic of machine learning. To begin with it will explain what this “machine learning” is all about. Ranging from Elementary idea of Features all the way to Special Architectures and Paradigms that come from both Engineering and Neural Sciences. The focus is however on mathematical and statistical approaches along with neural architectures that now constitute 80% of machine learning. The special focus is on linear algebra-based subspace techniques that will be used and to begin with face recognition task is covered in detail and followed by multi-biometric task that uses a variety of machine learning techniques from mathematics, signal and image processing, pattern recognition and random optimization. A task is taken in stages with improved sophistication, and progressively, it is shown that close to 99.99% accuracy if desired can be obtained using machine learning approaches.

Contents

MEMS-Based IMU for Pose Estimation . . . . . . . . . . . . . . . . . . . . . . . . . Sheethal S. Bangera, T. D. Shiyana, G. K. Srinidhi, Yash R. Vasani and M. Sukesh Rao

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Data Flow Verification in SoC Using Formal Techniques . . . . . . . . . . . K. S. Asha, Oswald Sunil Mendonca, Rekha Bhandarkar and R. Srinivas

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Performance Analysis of Converter Circuit Transfer Function Model Using PID Control Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . Rumana Ali and Vinayambika S. Bhat

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Design of Low-Power Active High-Pass Filter Using Operational Transconductance Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sharil Nivitha Rodrigues and P. S. Sushma

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Green Communication in Wireless Body Sensor Network—A Review . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P. Rachana and Durga Prasad

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Outage Performance Analysis of Hybrid FSO/RF System Using Rayleigh and K-Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . U. Anushree and V. K. Jagadeesh

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Development of Reliable On-Board Computer of STUDSAT-2 . . . . . . . Rakshith Devadiga, Sachin Kainthila, Abhishek Bangera, Amshak Shanbhogue, Durga Prasad and K. S. Shivaprakasha

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Design Techniques of Flash ADC: Review . . . . . . . . . . . . . . . . . . . . . . . Akshatha Kumary and Satheesh Rao

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Pedal Effects Modeling for Stringed Instruments by Employing Schemes of DSP in Real Time for Vocals and Music . . . . . . . . . . . . . . . D’Souza Dony Armstrong, Shastrimath V. Veena Devi and V. N. Ganesh

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Design and Development of Piezo-Stepping Voltage Drive for Piezoelectric Stack Actuator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Nutana Shetty, K. Sushith and Muralidhara Hybrid Feature Extraction Technique on Brain MRI Images for Content-Based Image Retrieval of Alzheimer’s Disease . . . . . . . . . . 127 K. Chethan and Rekha Bhandarkar Feature Selection from Gene Expression Data Using SVMRFE and Feed-Forward Neural Network Classifier . . . . . . . . . . . . . . . . . . . . 143 Nimrita Koul and Sunilkumar S. Manvi Implementation of SAR ADC for Biomedical Applications—A Review . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Lavita Mendonca and Rekha Bhandarkar Energy-Efficient Communication Using Data Aggregation and Data Compression Techniques in Wireless Sensor Networks: A Survey . . . . . 161 S. Pushpalatha and K. S. Shivaprakasha Spectrum Allocation Policies in Flexi-Grid Optical Networks . . . . . . . . . 181 M. B. Sumalatha, L. M. Aishwarya and C. L. Triveni Novel Approach in IoT-Based Smart Road with Traffic Decongestion Strategy for Smart Cities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 Padma Prasada, Sathisha and K. Shreya Prabhu Design and Development of Low-Cost Electronic Stethoscope Trainer Kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 Sukshith Shetty and Sukeerth Kumar Modified Hungarian User Pairing Method for NOMA-Based 5G Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 Tadepalli Sri Bala Ragni, Pigilam Swetha and V. P. Harigovindan Adaptive Bi-threshold Algorithm for ECG Compression Based on Signal Slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 Y. Mahesha and B. L. Lavanya Design of Set D Flip-Flop and Scannable Set D Flip-Flop with Optimized Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 M. Pooja, Guruprasad S. Shetty, Vedantham Shabara Datta and M. Suchitra User Satisfaction-Based Resource Allocation in LTE-A . . . . . . . . . . . . . 247 Jagadeesha R. Bhat and S. Anantha Kamath Secure Routing Protocol for MANET: A Survey . . . . . . . . . . . . . . . . . . 263 K. J. Abhilash and K. S. Shivaprakasha

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Improved HMM-Based Mixed-Language (Telugu–Hindi) Polyglot Speech Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 M. Kiran Reddy and K. Sreenivasa Rao Energy Harvesting Using Raindrops Through Solar Panels: A Review . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 Shreya Shetty, Vibha Kishore, Sinaida Reeya Pinto and K. B. Bommegowda Transfer Learning for Classification of Uterine Cervix Images for Cervical Cancer Screening . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 Vidya Kudva, Keerthana Prasad and Shyamala Guruvare Skew Analysis on Multisource Clock Tree Synthesis Using H-Tree Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 Vinayak Krishna Bhat, H. H. Surendra and H. R. Archana Review on Implementation of Fingerprint Verification System Using Image Inpainting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 Milind B. Bhilavade, Meenakshi R. Patil, Lalita S. Admuthe and K. S. Shivaprakasha PWM Controlled Solenoid Valves for Automatic Gear Change in Four-Wheelers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 M. R. Anusha and M. G. Veena Literature Survey on Emotion Recognition for Social Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 A. Vijayalakshmi and P. Mohanaiah Low-Power Analysis of Full Adder and Subtractor Design Using Adiabatic Logic Styles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 Akshitha and Niju Rajan Design and Implementation of Multiple-Output CMOS Voltage Level Shifter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385 S. Swaroop and K. S. Ravindra Design and Development of Multi-output Isolated Supply for SiC MOSFET Gate Driver Using Flyback Topology . . . . . . . . . . . . . . . . . . . 403 C. Shreya, G. Praveen Kumar, Vikhyath D. Amin and K. Suryanarayana Design of Error Correction Engine Based on Flexible Unequal Error Control Code (FUEC) for Flash Memory Faults in Space Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419 G. Amrutha Shree and Veena S. Chakravarthi

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Analysis of Cryptographic Algorithms for Secured Data Transmission in VANETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433 Kalkundri Ravi, Rajashri Khanai and Kalkundri Praveen Classification of Landsat 8 Imagery Using Kohonen’s Self Organizing Maps and Learning Vector Quantization . . . . . . . . . . . . . . . 445 B. R. Shivakumar and S. V. Rajashekararadhya Solar Based Inverter Design: A Brief Review . . . . . . . . . . . . . . . . . . . . . 463 A. Vishwitha and Anil Kumar Bhat Two-Way Image Based CAPTCHA . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471 M. Poornananda Bhat and Rashmi Naveen Raj Performance Comparison of Semi-Z-Source Inverter and Full-Bridge Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485 M. Megha and V. Ansal Control Loop Design of DC–AC Power Supply with High Crest Factor Nonlinear Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503 Prajwal Puranik, M. Ashwini Kumari, K. Suryanarayana and K. Krishna Prasad Fuzzy Logic Controller for Indirect Vector Control of Induction Motor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519 Girisha Joshi and Pinto Pius A J Stability Improvement Using SSSC in Synchronous Generation System with PMSG-Based Offshore Wind Farm . . . . . . . . . . . . . . . . . . 535 Chethan HR and R. Mageshvaran

About the Editors

Dr. Shubhakar Kalya obtained his master’s degree in microelectronics from Indian Institute of Science (IISc), Bangalore, India, in 2007 and Ph.D. degree in the field of nanoelectronics from School of Electrical and Electronics Engineering, Nanyang Technological University (NTU), Singapore, in 2012–13. He obtained his bachelor’s degree in Electronics and Communication Engineering from N.M.A.M. Institute of Technology, Nitte. He is working as Faculty in Engineering Product Development (EPD) Pillar at Singapore University of Technology and Design (SUTD), Singapore, since January 2012. His research work focuses on nanoscale characterization of high-j gate dielectrics and 2D materials for advanced logic and memory devices and its reliability analysis. During July 2009 to December 2012, he has worked as Visiting Researcher at Institute of Materials and Research Engineering (IMRE), Singapore, and involved in research related to the characterization of high-j gate dielectrics using scanning tunnelling microscopy and atomic force microscopy. During January–June 2017, he was at Massachusetts Institute of Technology (MIT), Cambridge, USA, as Visiting Scientist. He has authored/co-authored more than 30 research publications (journals/international conferences) and two chapters. He is also involved in the review of various technical papers including IEEE Transactions on Device and Materials reliability, Microelectronic Engineering journals and international conferences related to nanoelectronics field. Dr. Muralidhar Kulkarni received his B.E. (Electronics Engineering) degree from University Visvesvaraya College of Engineering, Bangalore University, Bangalore; M.Tech. (Satellite Communication and Remote Sensing) degree from Indian Institute of Technology, Kharagpur (IIT KGP); and Ph.D. from JMI Central University, New Delhi, in the area of optical communication networks. He has served in various capacities in industry and academics for the last 35 years. He has held the positions of Scientist in Instrumentation Division at the Central Power Research Institute, Bangalore; Aeronautical Engineer in Avionics group of Design and Development team of Advanced Light Helicopter (ALH) project at Helicopter Design Bureau, Hindustan Aeronautics Limited (HAL), Bangalore; Lecturer xxxix

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(Electronics Engineering) at the Electrical Engineering Department, University Visvesvaraya College of Engineering, Bangalore; and as Assistant Professor in Electronics and Communication Engineering (ECE) Department, Delhi College of Engineering (DCE), Delhi. He has served as Head, Department of Information Technology, and Head, Computer Centre at DCE, Delhi. Currently, he is Professor in the Department of Electronics and Communication Engineering (ECE), National Institute of Technology Karnataka (NITK), Surathkal, Karnataka. His teaching and research interests are in the areas of digital communications, information theory and coding, fuzzy digital image processing, optical communication and networks and OFDM/COFDM techniques. He has published more than 50 papers in reputed international/national journals and conferences. He has also authored fivebooks in the areas of communication. Dr. K. S. Shivaprakasha received his B.E. (Electronics and Communication) degree from Bahubali College of Engineering, Visvesvaraya Technological University, Karnataka, with IX rank in the university and M.Tech. (Digital Electronics and Communication Systems) degree from Malnad College of Engineering, Visvesvaraya Technological University, Karnataka, with I rank with gold medal in the university in 2004 and 2007, respectively. He completed his Ph.D. from National Institute of Technology Karnataka (NITK), Surathkal, Karnataka, in the field of wireless sensor networks in 2015. Currently, he is Associate Professor in the Department of Electronics and Communication Engineering, N.M.A.M. Institute of Technology, Nitte, Karnataka. His areas of research interest include wireless sensor networks, mobile ad hoc networks, information coding theory and cryptography. He has published more than 20 papers in reputed international/national journals and conferences and has co-authored a book on “Information Theory and Coding”.

MEMS-Based IMU for Pose Estimation Sheethal S. Bangera, T. D. Shiyana, G. K. Srinidhi, Yash R. Vasani and M. Sukesh Rao

Abstract This research investigates pose estimation using micro-electromechanical-system (MEMS)-based inertial measurement unit (IMU) in real time. Accelerometers suffer from errors caused due to accelerations that add to gravity. This makes the position obtained from accelerometers unreliable and inaccurate. Gyroscopes are encountered by data drifting problems. This paper illustrates pose estimation by integrating the IMU data. A moving average filter is used to get the position information by reducing abrupt variations in the accelerometer data, whereas the complementary filter passes accelerometer and gyroscope data through low- and high-pass filters to obtain orientation. The results are recorded for both static and dynamic conditions which show that both complementary and moving average filters are less sensitive to variations compared to that by only integrating the IMU data. Keywords Complementary filter · IMU · Pose estimation · Moving average filter · Data fusion

S. S. Bangera (B) · T. D. Shiyana · G. K. Srinidhi · Y. R. Vasani · M. Sukesh Rao Department of Electronics and Communication, NMAM Institute of Technology, Nitte, Udupi, India e-mail: [email protected] T. D. Shiyana e-mail: [email protected] G. K. Srinidhi e-mail: [email protected] Y. R. Vasani e-mail: [email protected] M. Sukesh Rao e-mail: [email protected] © Springer Nature Singapore Pte Ltd. 2020 S. Kalya et al. (eds.), Advances in Communication, Signal Processing, VLSI, and Embedded Systems, Lecture Notes in Electrical Engineering 614, https://doi.org/10.1007/978-981-15-0626-0_1

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1 Introduction The inertial measurement unit (IMU) is an electronic device that measures accelerations and angular velocities with the use of three-axis accelerometer and three-axis gyroscope to estimate an object’s position and orientation. IMUs have long been used in the applications of aerospace [1] and navigation [2] fields. The IMUs were initially bulky in size. Over time, with the development of MEMS technology-based IMU, the size and the power consumed are reduced [3]. The MEMS-based IMU sensor can be used for the application of pose estimation, which has a wide use in the fields of robotics, navigation, and consumer electronics. In the robotics field, climbing robot, terrain robot, navigation robot, etc., orientation and position play a key role [4], but the results obtained by using MEMS-based IMU are simple but noisy and nonlinear. As the data from the accelerometer of IMU is noisy and subjected to external acceleration interference, when it is used to measure the gravitational acceleration, it is hard to obtain an accurate result in a vibrating environment. Hence, the orientation measurement cannot be relied only on the accelerometer in order to get accurate data even though it provides stable data without any drifts in long term. Gyroscope measures angular velocities around the three axes, and the signals are not prone to external noises as compared to accelerometers. Therefore, a tri-axis accelerometer-based MEMS IMU sensor and a tri-axis gyroscope-based MEMS IMU sensor are optimal for orientation estimation. However, the disadvantage of using a gyroscope is that the data measured tends to drift because of the angular velocity data bias that accumulates over time. The gyroscope data can be trusted for a short duration. Taking the advantages and disadvantages of gyroscopes and accelerometers, the IMU data fusion is essential for a reliable orientation estimation. The noisy data from the accelerometer is fed into the moving average filter where the abrupt variations in the measured data are smoothened and the position is obtained by the integration of acceleration twice. One of the most frequent methods used for data fusion in IMU is the complementary filter which makes use of accelerometer and gyroscope data to determine the orientation of an object [5]. Also in this paper, moving average filter is used to stabilize the accelerometer reading from the IMU to estimate the position. The complementary filter makes use of a relatively simple algorithm and few computations. Hence, it can be used in embedded system application. Hence, a comparative study of complementary filter by fusing IMU data to determine orientation and moving average filter used for accelerometer data for determining position, double integrating the IMU accelerometer data for position, and single integrating the gyroscope data for orientation under static and dynamic conditions for each case is taken into consideration. A comparison was made on the experimental results obtained using the above different methods.

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2 Methodology for Position Estimation 2.1 Double Integration An accelerometer is an electromechanical device. It used to measure the acceleration experienced by an object. It can be defined as the rate of change of velocity with respect to time. It is a vector quantity having both magnitude and direction. MEMS-based IMU sensor gives acceleration in terms of ‘g’ unit (‘g’ is acceleration measurement for gravity which is equal to 9.81 m/s2 ). The accelerometer data from the IMU sensor is integrated twice to obtain position [6]. The accelerometer’s data from the IMU is integrated once to obtain velocity as given in Eq. (1),  v(t) =

a(t)dt

(1)

The acceleration (t) is a function of time. Position is obtained by integrating velocity (t). The position x(t) as a function of time is given in Eq. (2),  x(t) =

v(t)dt

(2)

The data processing procedure of accelerometer data using double integration method is shown in Fig. 1.

Fig. 1 Double integration method used in IMU

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Double integration of acceleration data to estimate position is very inaccurate due to integration drift. As the iterations increases, double integration accumulates the error in the measurements.

2.2 Moving Average Filter In order to reduce the abrupt variations in the observed accelerometer data, moving average filter is used. This is a low-pass finite impulse response (FIR) filter usually used to smoothen an array of information. It takes M samples of input at a time, takes the average of these M samples, and produces an output. As the filter length increases, the smoothness of the output increases, whereas the sharp transitions of the information are reduced. It implies that the filter has very good time-domain response but a poor frequency response. The difference equation for a M-point discrete-time moving average filter with input represented by the vector x and the averaged output vector y is given in Eq. (3), y[i] =

M−1 1  x[i + j] M j=0

(3)

where M = number of points used for moving average filter. In this paper, the filter order M is considered to be 32. (n) is the input given to the filter, and (n) is the output as shown in Fig. 2. The data from the IMU is fed to the moving average filter where the abrupt variations of the accelerometer values are reduced which can be observed from the

Fig. 2 Signal flow graph of moving average filter with order M = 32

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Fig. 3 IMU sensor data with moving average filter

graph. This smoothened data is further double integrated, and the position is obtained as shown in Fig. 3. Moving average cannot detect sudden changes in acceleration. It involves definite amount of delay. If the filter length is low, smoothness of the output decreases. It is very challenging to decide on the correct filter length to be used. Moving average is place significance on past values that may or may not be relevant in the present or into the future. Due to the simplicity and flexibility of moving average filters, these are informative and not declarative.

3 Methodology for Orientation Estimation 3.1 Single Integration Gyroscope, also called as gyros, is devices that measures the rotational motion of an object. Micro-electro-mechanical-system (MEMS) gyroscopes are small, cheap sensors that measures angular velocity in °/s. Gyroscopes are used to obtain orientation. These are found useful in most navigation systems. These gyroscopes are making immense progress towards low power consumption and high performance in embedded systems [4]. MEMS gyroscopes use the Coriolis effect which measures the angular rate. The Coriolis force is an inertial or fictitious force or pseudo forces that act on objects that are in motion within a frame of reference which rotates with respect to an inertial frame. Orientation estimation is achieved by single integration of the gyroscope data from the IMU as given in Eq. (4),

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Fig. 4 Single integration method used in IMU

 Θ=

ω dt

(4)

The data processing procedure of gyroscope data using single integration method is shown in Fig. 4. However, gyroscopes are subjected to instabilities. The gyroscope data drifts over a period of time as a result of integration process. It can be noticed that accelerometer data is useful in a long duration of time, whereas the gyroscope data is useful for short time. Hence, the most appropriate approach can be considered by using a complementary filter that combines the accelerometer and gyroscope data as shown in the next section.

3.2 Complementary Filter The complementary filter was introduced by Shane Colton in the year 2007. The filter performs low-pass filtering on low-frequency orientation estimation on the data from the accelerometer, whereas high-pass filtering on high-frequency estimation which is obtained directly by integrating with the gyroscope output. All-pass estimation of the orientation is obtained by fusing both the data [5]. The complementary filter makes use of the low-pass filter data from the accelerometer which is used to correct the drift of the angle over long period of time and the integrated angle from the gyroscope for short period of time. The offset of the gyroscope is updated and corrected continuously. This gives the estimated angle as drift free and fast responding. The principle of the complementary filter is illustrated in Fig. 5. The mathematical equation for implementation of complementary filter is given by Eq. (5)

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Fig. 5 Complementary filter block diagram

Angle = K ∗ (angle + Rate ∗ dt) + K  ∗ accelraw ∗ K _GAIN

(5)

K

factor that determines the cut-off time for trusting the gyro and filtering in the accelerometer. The value is always between 0 and 1, usually close to 1. In this case, K is defined to be 0.98. K complement; i.e., (1 − K) is 98% of the current angle comes K from the previous angle measurement which is added to the integrated gyroscope value. The remaining 2% is derived from the accelerometer. dt sampling time, Rate gyroscope data in degrees per second, accelraw ∗ K _GAIN accelerometer reading which is converted to degrees.

4 Experiment Results 4.1 Position Estimation The raw data from the accelerometer in x-direction and y-direction is subjected to certain amount of noise even at zero position. Totally 15 trials are conducted and 100 samples are taken in each trial and averaged individually in x-direction and y-direction. It is noticed that the offset is varying in each trial as shown in Fig. 6. To reduce the noise when the object is at rest, the offset is then subtracted from the raw accelerometer data to reduce the noise when the object is at rest. The graph is plotted for 100 samples in x-direction and y-direction, respectively, as shown in Fig. 7.

4.1.1

Double Integration

Position is estimated by double integrating the acceleration. Table 1 illustrates two different values with 5 trials each in both x-direction and y-direction when the object

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Fig. 6 a Offset values of accelerometer in x-direction, b offset values of accelerometer in y-direction

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Fig. 7 a Accelerometer data when the object is at rest in x-direction, b accelerometer data when the object is at rest in y-direction

Table 1 Data observed after double integration method Actual position (m)

Practical position (m)

x-axis

x-axis

y-axis

y-axis

Average

Standard deviation

Average

Standard deviation

0.5

0.5

1.5295

0.00125

2.1456

0.00732

1

1

2.4821

0.00253

3.5437

0.00746

is in motion. In the first trial when the object is moved to 0.5 and 1 m in both x-direction and y-direction, the practical values are observed. Double integration method accumulates the error in the measurements as the iterations increases; hence, it is not possible to estimate the position from this method.

4.1.2

Moving Average Filter

To reduce the abrupt variations of the measured position from the true position, moving average filter can be used. The unwanted noisy component from the measured data is filtered when the object at rest. Figure 8 represents 500 samples in x-direction and y-direction of the IMU sensor. The following observations are made when the object is in motion:

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Fig. 8 a Accelerometer data with moving average filter when object is at rest in x-direction, b accelerometer data with moving average filter when object is at rest in y-direction

i. The object is made to move 0.9 m, but practically the position is observed to be 1.2 m in x-direction as shown in Fig. 9a. ii. The object is made to move 0.35 m, but practically the position is observed to be 0.8 m in y-direction as shown in Fig. 9b. The sudden changes in acceleration cannot be detected by using moving average filter. It is also observed that if the filter length is low, the smoothness of the output waveform decreases, and if the length is high, computation time increases. Hence, it is difficult to select the precise length of the filter.

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Fig. 9 a Object in motion in x-direction with moving average filter, b object in motion in y-direction with moving average filter

4.2 Orientation Estimation The raw data from the gyroscope in x-direction and y-direction is subjected to certain amount of noise even at zero position. In total, 1000 samples are taken individually in x-direction and y-direction. It is noticed that there is a large amount of drift in the gyroscope data even though the object is at rest as shown in Fig. 10.

4.2.1

Single Integration

The orientation of an object is estimated by single integrating the gyroscope data. The data after single integration is observed to be drifted by a large amount even at rest as shown in Fig. 11. It can be concluded that gyroscope alone cannot be used for orientation estimation.

4.2.2

Complementary Filter

The data from gyroscope and accelerometer cannot be used separately to estimate the orientation as shown in Sect. 4.2.1. Therefore, the best method is to fuse the

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Fig. 10 a Gyroscope data when the object is at rest in x-direction, b gyroscope data when the object is at rest in y-direction

Fig. 11 a Gyroscope data after single integration in x-direction, b gyroscope data after single integration in y-direction

gyroscope and accelerometers’ data, which can be done by using a complementary filter. Experimentally when the object is placed at 30°, it is observed that by using only accelerometer, the orientation is varied compared to that when a complementary filter is used which gives 28.1° as shown in Fig. 12. Table 2 illustrates the different values of orientation obtained from the complementary filter. It is observed that values obtained using this filter are the average ± standard deviation.

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Fig. 12 Comparison between the angles obtained from complementary filter and accelerometer

Table 2 Data observed after using complementary filter Actual angle (°)

x-axis Average

y-axis Standard deviation

Average 0.43322

Standard deviation

0

1.0254

0.0275

15

15.5542

0.0841

16.1034

0.1813

0.0961

30

29.3151

0.0748

33.9035

0.0417

45

45.3090

0.1252

48.8193

0.3309

60

61.4460

0.0434

62.4619

0.0672

75

74.5571

0.0599

76.9035

0.0346

90

87.0252

0.3497

89.1316

0.5839

5 Conclusion MEMS-based IMU is used for pose estimation. Accelerometers’ raw data has a lot of variations. Position is obtained by double integrating this data. This procedure continuously accumulates the error. To overcome this erroneous data, moving average filter is used which smoothens the abrupt variations giving the more appropriate position of an object. However, this is not the best method as it is difficult to estimate the precise length of the filter. It is observed that the gyroscope data is reliable only for short duration of time, whereas the accelerometer data is trusted for long term. Clearly, by only using accelerometer to determine the orientation accurately is difficult as the data is sensitive to variations, whereas the gyroscope data is used to offset the disadvantages of accelerometer data. As gyroscope data drifts over a period of time, hence to solve these problems, different filter algorithms are required. Taking different aspects of gyroscope and accelerometer into consideration, the fusing of IMU data is required for the orientation estimation, which is obtained by using complementary filter. This

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technique can be effectively used in orientation estimation as long as the proper filter parameters are found.

References 1. Bergamini E, Ligorio G, Summa A, Vannozzi G, Cappozzo A, Sabatini AM (2014) Estimating orientation using magnetic and inertial sensors and different sensor fusion approaches: accuracy assessment in manual and locomotion tasks. Sensors 14(10):18625–18649 2. Fang W, Zheng L, Deng H (2016) A motion tracking method by combining the IMU and camera in mobile devices. In: 2016 10th international conference on sensing technology (ICST), pp 1–6. IEEE 3. Callari FG, Soucy G, Ferrie FP (1998) Uncertainty in pose estimation: a bayesian approach. In: Proceedings of fourteenth international conference on pattern recognition, 1998, vol 2. IEEE, pp 972–976 4. Rehbinder H, Ghosh BK (2003) Pose estimation using line-based dynamic vision and inertial sensors. IEEE Trans Autom Control 48(2):186199 5. Zhang Y, Song K, Yi J, Duan Z, Pan Q, Huang P (2016) Pose estimation of a rigid body and its supporting moving platform using two gyroscopes and relative complementary measurements. In: 2016 IEEE/RSJ international conference on intelligent robots and systems (IROS). IEEE, pp 90–95 6. Seifert K, Camacho O (2007) Implementing positioning algorithms using accelerometers. Freescale Semicond

Data Flow Verification in SoC Using Formal Techniques K. S. Asha, Oswald Sunil Mendonca, Rekha Bhandarkar and R. Srinivas

Abstract Hardware security is becoming increasingly critical in SoC designs. A SoC integrates several modules to form a larger system. To reduce the time-tomarket and design efforts, reusable, pretested modules called intellectual properties (IPs) are incorporated in the design. Hence, designing mainly relies on interconnection of modules that may lead to unintentional functional paths. As SoC may contain several secure and non-secure modules, data propagation in the design must be carefully analyzed. There exist various forms of security attacks like tampering, repudiation and privilege elevation. These attacks may affect system manufacturers, system designers or the end users. A designer invests a lot on design in terms of both money and time, and SoC protection becomes highly important. Security Path Verification (SPV) App of JasperGold Tool by Cadence is used to check the sanctity of the data in the design. SPV uses formal techniques to verify the data propagation in the design. Keywords SoC verification · IP protection · JasperGold tool · Security path verification

K. S. Asha (B) · R. Bhandarkar Department of ECE, NMAM Institute of Technology, Nitte, Karkala, India e-mail: [email protected] R. Bhandarkar e-mail: [email protected] O. S. Mendonca NXP Semiconductors India Pvt. Ltd., Bangalore, India e-mail: [email protected] R. Srinivas R&D Design, Digital Design, NXP Semiconductors India Pvt. Ltd., Bangalore, India e-mail: [email protected] © Springer Nature Singapore Pte Ltd. 2020 S. Kalya et al. (eds.), Advances in Communication, Signal Processing, VLSI, and Embedded Systems, Lecture Notes in Electrical Engineering 614, https://doi.org/10.1007/978-981-15-0626-0_2

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1 Introduction Security plays a very important role, and it is a critical parameter in the modern system on chip (SoC) designs. Intellectual properties (IPs) that are used to build larger systems reduce engineer’s design effort and improve the time-to-market requirement. General block diagram of a SoC is shown in Fig. 1. In general, a SoC may contain several IPs, and hence, security of IP components that hold the key designs and parameters is considered as a critical design requirement. The risk of losing critical designs and parameters to the frauds must be reduced or merely eliminated. Data propagation in the design must be verified under all the constraints and conditions as per the design specifications. As unintentional functional paths may lead to leakage of critical information, security holes in the design must be carefully analyzed and verified for secure data flow. The use of IPs in VLSI industries and its protection plays an important role in SoC design. VLSI IP reuse-based design technology trends were initially used by semiconductor industry in the early 1990’s. Protecting the IPs and preventing stealing of critical data and information have always been a challenging issue. The circuit capacity afforded by the Moore’s Law pace of technology advancement was growing faster than the capabilities of EDA tools and VLSI engineers flows to support the associated design complexity. This gave rise to the productivity gap, and engineers were unable to design all the transistors on a single die. To reduce this gap, industries adopted IP reuse-based design. These IPs became the most valuable assets for the companies. Three different types of IPs are hard IPs (such as GDSII files and custom physical layout), firm IPs (placed RTL blocks) and soft IPs (synthesizable HDL source codes).

Fig. 1 General block diagram of SoC

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Tremendous growth of VLSI IP reuse technology demanded the emergent of IP protection to overcome various kinds of security threats like tampering and reverse engineering. In general, commonly used IP protection deterrents include patents, copyrights, contracts, trademarks and trade secrets. Though, these do not directly avoid IP privacy, if being caught a severe penalty could be enforced to compromise the financial loss to the IP owner. IP protection has been identified as one of the key enabling technologies for the reuse-based design methodology [1]. The globalization of SoC design flow has created opportunities for fraud IP vendors to insert malicious codes into the IPs. A formal verification technique can be used to verify the thirdparty IPs for unauthorized information leakage. To reduce time-to-market constraints and fabrication and test costs, fabless SoC engineers integrate third-party IPs with in-house IP cores. But, this can lead a fraud IP vendor to introduce malicious circuits or codes during fabrication, and it may cause failure of the design or it may unknowingly introduce a backdoor for the attacker to access the system without authorization [2, 3]. Formal verification techniques provide 100% coverage, and counterexamples provide a complementary solution. A formal property verification (FPV) can be used for rapid prototyping and verification [4, 5]. Development of an IP protection based on information hiding explains that though IP reuse and exchange is favorable, it may result in considerable security risks. Hence, during the system design, incorporation of an embedded ownership proof using information hiding can be useful. At the starting of IP design life cycle, additional information can be added to the design, and this helps to identify the copyright [6]. Enhanced techniques may reduce the system security if care is taken during the design. Data confidentiality and intellectual property protection can be breached through testing security breaches. The countermeasures like protocol level protection, scan chain level protection and pattern watermarking could provide security while testing [7]. Logic obfuscation technique can be used to protect the design from reverse engineering of IP or IC and protect it from overbuilding. Obfuscation technique modifies the original netlist which is logically equivalent to original design when proper key is used. It also has been concluded that although the attackers can extract the gatelevel netlist by circuit extraction-based reverse engineering, they cannot infer the obfuscated logic functions [8]. To reduce the design time and TTM, IPs are used as building blocks for designing larger systems. This avoids individual module’s verification as IPs are pre-verified, and working modules and designers need to concentrate only on the connection between the modules. Further, modern SoCs may also contain critical data like passwords and account PINs. Hence, verification plays an important role in securing IPs and its data from frauds.

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2 IP S and IP Protection To reduce the course of design time, verified, tested and working reusable modules are used. These modules are referred to as intellectual properties (IPs). Intellectual property is a general term for various legal entitlements. It is a category of property that includes intangible creations of the human intellect and protected from IP laws. IP includes patents, copyrights, design rights, literary/artistic works, inventions, trade secrets and other non-tangible property. Semiconductor IP is in that category as well. Usage of IPs reduces engineers’ efforts in designing each module from the scratch. As designing of ICs requires a lot of efforts and investment, it is important to protect these IPs from various kinds of threats. Threats can be (i) Spoofing: sending unauthorized information. (ii) Tampering: changing the contents without authorization. (iii) Repudiation: denial of authorizing actions that took place. (iv) Information disclosure: injecting malicious code, sniffing interfaces. (v) Denial of service: blocking of the controller, lock of debug port. (vi) Elevation of privilege: get access as a developer, non-authorized features. Major attacks to the SoC include malicious modifications of a design referred to as hardware Trojan attacks, stealing of hardware IPs in the form of unauthorized sale or use of soft intellectual property cores/ICs and physical attacks like side-channel attack, fault-based attack and scan-based attack on cryptographic systems during deployment [9]. The SoC must be analyzed for different security issues. As the first step of threat analysis, the overall functional diagram must be drawn, and all the weak point in the design must be identified. The SoC is then extended with assets that are required to protect the secure IPs. The extended assets can include (i) Encryption/decryption keys. (ii) Passwords: to protect debug ports. (iii) Keycodes: encrypted codes to get access to additional features. (iv) Configuration details: to enable specific set of features for a product variant. A secure SoC must provide (i) Secure boot: to ensure that no malicious software is loaded into the system. (ii) Secure and non-secure memory. (iii) Encryption and decryption support and (iv) Debug port protection. In a security IP architecture, private buses are implemented to carry decrypted parameters and keys. Plain key is never made available in public bus. All the critical parameters in the design are stored in secure memory that can never be read through the debug ports when unlocked. Debug ports are always password protected, and user or the designer is allowed to debug the SoC using unique password only. All the registers connected to the private buses are cleared before entering into the scan mode to ensure that no secret data is read through the debug ports.

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3 SoC Verification In an IC design life cycle, generally after design phase, implementation and fabrication and testing are then followed. If any error in the design occurs at the later point, more effort and time will be required to rectify the design. Also, if any security holes like backdoors, unintentional functional paths exist, critical parameters or data may be lost to the frauds. Hence, the design verification is done to capture the design faults at the early phase of design life cycle to remove the design faults before it is implemented. Functional verification is carried out to check the correct functionality of the design soon after the design phase. Formal verification methods are more useful where the designs are verified formally. Verification gives us predictive analysis to ensure that the synthesized design, when manufactured, will perform the given I/O function. It is responsible for the quality of the design. Simulation is a very primitive verification approach. A SoC is tested exhaustively for all the possible input conditions and outputs are verified against the functional specifications. This approach can detect any kind of fault in the design but is limited to smaller designs. As today’s circuits are highly complex, it is merely impossible to generate all possible input vectors to check the behavior of the system. In nonexhaustive approach, the system is checked only for selected input vectors. Hence, the accuracy of this approach purely depends on the heuristic of the verification engineer. Formal verification methods are static, less time consuming and provide 100% coverage. The properties are developed from the system design specification, and system is checked if the defined properties are proven under given conditions and constraints. Though functional verification by simulation is robust, it is more restricted to smaller designs. Formal techniques not only improve verification quality, but also can reduce the verification effort and time and also a quick and thorough module verification. Hence, formal verification is a better choice for highly complex designs [10]. The role of formal technology in the overall SoC design and verification flow has grown significantly. JasperGold platform provides several formal verification applications. Security Path Verification App of JasperGold verifies the data propagation in the design. Data in a secure area should not be accessible from non-secure area. SPV ensures that there is no leakage of data through any unintended paths. Hence, unintentional functional paths are avoided in this application. Initially, properties are created with certain constraints. The app introduces a unique tag at the source and checks if it can ever appear at the destination. If a property is proven, then it is impossible for a data to propagate from the given source to destination under given constraints. If the property fails, then a counterexample shows how data can propagate from source to destination. Security Path Verification involves the following steps. (i) Analyzing and elaborating the design. (ii) Adding basic tie-off constraints. (iii) Defining clock and reset

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Fig. 2 Formal property verification flow

Fig. 3 Message log output after elaboration of test design

conditions. (iv) Create properties and prove. (v) Debug the design. The formal property verification flow is shown in Fig. 2. HDL designs are hierarchic by nature. The top entity instantiates signals, components and processes. Each component instantiates additional signals, components and processes. The compiler explores the top-down design hierarchy and builds an interconnection table until it reaches the building blocks of the design. At this step, the building blocks are still generic RTL constructs: logic gates, registers, memories, etc. Analysis is the process in which the design is checked for syntactic and semantic errors. Elaboration is responsible to translate the design into a database of interlinked generic elements which are independent of design language. The test SoC included Verilog, VHDL and SystemVerilog files; all these modules are analyzed using respective switches. In JasperGold Tool design has been elaborated at the IC level. The design has been analyzed successfully. Figure 3 shows the message log output after analysis and elaboration.

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Fig. 4 Clock generation unit in SoC

A clock signal is generated by the clock generator. Even with the more complex system arrangements, most basic clock signal used is square wave signal with a 50% duty cycle, generally using a fixed and constant frequency. A clock generation unit derives multiple clock frequencies from the same clock, as different modules are operated at different frequencies. Clock derivation in a SoC can be generally represented as shown in Fig. 4. A part of the clock generation unit is analog design, and it is black boxed from security analysis. Hence, all the derived clocks are defined, and these signals are made independent by defining environmental stopats. Environmental stopat makes a signal independent of its driver. Unlike clock signal, only one reset condition can be defined. All the clock signals and reset condition are defined for the design. Properties are generated to check data flow between two disjunctive modules. Few of the generated properties are as shown in Fig. 5. It has been proven that there is no data flow from defined source to the destination under any constraints. Figure 6 shows the SPV viewer after running proof command.

4 Future Work Properties are to be developed to check the secure data flow between secure IP and other modules. All the properties are to be developed from the design specifications.

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Fig. 5 Generated properties

5 Conclusion Verification plays an important role as it detects design errors at the early phase of design life cycle. Formal verification methods are static, less time consuming and provide 100% coverage. SPV of JasperGold Tool uses formal techniques to verify the data flow from given source to the destination. The clock generation unit is black boxed, as a part of clock generation unit is analog design. Hence, clocks are defined for each module. Design reset condition is defined. Nine hundred properties are developed to check if there exists any unintentional data flow between two disjunctive modules for the test design. All the properties have been proven indicating that there is no flow of data from the given source to destination under any circumstances. This ensures no data flow between the disjunctive modules. TCL scripting is used to develop the source code.

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Fig. 6 Output showing no data flow from defined source to destination

References 1. Potkonjak M, Qu G, Koushanfar F, Chang CH (2017) 20 Years of research on intellectual property protection. In: 2017 IEEE international symposium on circuits and systems (ISCAS). IEEE, pp 1–4 2. Rajendran J, Dhandayuthapany AM, Vedula V, Karri R (2016) Formal security verification of third party intellectual property cores for information leakage. In: 2016 29th international conference on VLSI design and 2016 15th international conference on embedded systems (VLSID). IEEE, pp 547–552 3. Sen L, Roy A, Bhattacharjee S, Mittra B, Roy SK (2010) DFT logic verification through property based formal methods: SOC to IP. In: Proceedings of the 2010 conference on formal methods in computer-aided design. FMCAD Inc., pp 33–34 4. Liao WS, Hsiung PA (2003) FVP: a formal verification platform for SoC. In: Proceedings of IEEE international SOC conference (systems-on-chip), 2003. IEEE, pp 21–24 5. Stoffel D (2009) Formal verification of systems-on-chip-industrial experiences and scientific perspectives. In: 2009 20th international workshop on database and expert systems application. IEEE, pp 3-3 6. Basu A, Mallick R, Sur S, Sarkar SK (2012) On the implementation of a intellectual property protection based on information hiding. In: 2012 5th international conference on computers and devices for communication (CODEC). IEEE, pp 1–4 7. Hély D, Rosenfeld K, Karri R (2011) Security challenges during VLSI test. In: 2011 IEEE 9th international new circuits and systems conference (NEWCAS). IEEE, pp 486–489

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8. Zhang J (2016) A practical logic obfuscation technique for hardware security. IEEE Trans VLSI Syst 24(3):1193–1197 9. Wang X, Zheng Y, Basak A, Bhunia S (2015) IIPS: infrastructure IP for secure SoC design. IEEE Trans Comput 64(8):2226–2238 10. Hanna Z (2014) Challenging problems in industrial formal verification. In: 2014 formal methods in computer-aided design (FMCAD). IEEE, pp 1-1

Performance Analysis of Converter Circuit Transfer Function Model Using PID Control Algorithms Rumana Ali and Vinayambika S. Bhat

Abstract Switching power converter circuits are commonly employed in most electronic gadgets for various applications. The effective control of the converter circuit is significantly important in achieving steady-state response. The PID control algorithms, (i) Ziegler–Nichols, (ii) modified Ziegler–Nichols, and (iii) Good Gain are designed for the transfer function model of the boost and bidirectional converter circuits. The closed loop servo and regulatory responses are recorded in the MATLAB/Simulink environment. The time-domain specifications and performance indices are analyzed. The controller effectiveness is also evaluated in the presence of +10% uncertainties in the process parameters. Keywords Converter circuit · Transfer function · PID controller · Performance indices · Uncertainties

1 Introduction Power converters mark a new trend in Industrial Revolution because of its proficiency in various fields of application like laptops, LED drives, electric and hybrid vehicle, fuel cell vehicle, renewable energy, and aerospace [1]. The DC–DC converter circuits are used to increase and/or decrease the voltage amplitude of the input voltage to the required amplitude of the voltage suitable for various applications [2]. “The different types of converters are Buck converters, Boost converters, Buck–Boost converters, Cuk converters, Zeta converters, and SEPIC converters [3].” The most important research interest is the application of power converters and its control. R. Ali (B) Department of Mechatronics Engineering, Mangalore Institute of Technology and Engineering, Moodbidri, India e-mail: [email protected] V. S. Bhat Department of Electronics and Communication Engineering, Mangalore Institute of Technology and Engineering, Moodbidri, India e-mail: [email protected] © Springer Nature Singapore Pte Ltd. 2020 S. Kalya et al. (eds.), Advances in Communication, Signal Processing, VLSI, and Embedded Systems, Lecture Notes in Electrical Engineering 614, https://doi.org/10.1007/978-981-15-0626-0_3

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Boost converters are expected to achieve high efficiency, improved power quality and are compact in size and economic with low-energy losses. Ideally, converters have to maintain constant output voltage with change in input voltage, load current, and variations in element values of the converter circuit [2]. In practical, the converters are unstable, time-variant and have nonlinear dynamic characteristics. The reason for nonlinear responses in converters is mainly the presence of passive devices, operation of switches (ON/OFF), power quality issues, and change in load current and supply voltage [4]. Controllers can be employed to ensure the stability of the converters [5]. Recent research states that “the design of a controller is most challenging due to the nonlinear responses of the power converter [4–6].” It is necessary to model the converter dynamic behavior and to understand how the output voltage behaves with change in supply voltage, duty cycle, and input current. To attain this, proportional integral derivative (PID) controllers are the best contenders among the various controllers. About 90% of the industries employ PID controllers as it is classic in design with gradable performances [6]. The demanding need is the difficulty in finding PID gains to achieve the desired features (gain and overshoot response time) for an application. The gains of a PID controller can be determined manually with trial and error methods, which are sluggish and haphazard [5]. Thus, standard tuning procedures like the Ziegler–Nichols method, the modified Ziegler–Nichols, and the Good Gain method are commonly used [7, 8].

2 Organization of the Article The article is organized as follows. Section 3 briefly states about the boost converter and its transfer function using the state-space averaging method. Section 4 describes the bidirectional converter and its transfer function in step-up mode. Section 5 introduces the controller design, including its tuning methods. Section 6 depicts the results, which includes the servo response, regulatory response, and system response with uncertainties in all plant parameters. Finally, Sect. 7 presents the conclusions and Sect. 8 scope for future work.

3 Boost Converter “The boost converter is a DC to DC converter used to enhance the voltage from a lower level to a higher level, normally an unregulated to a regulated DC output voltage [1].” It delivers smooth acceleration, excellent efficiency, and excellent dynamic response [6]. A boost regulator uses a power transistor as a switching device. The designing of the circuit is a challenge task as it includes designing of the power and control circuits.

Performance Analysis of Converter Circuit Transfer Function …

27

Fig. 1 Circuit diagram of boost converter [1]

Fig. 2 Boost converter at ON condition [1]

Current and voltage harmonics are triggered in the power converters which can be minimized with the proper choice of design and control strategy [5]. Stabilizing of the regulators becomes tedious as the output is very subtle to change in the duty cycle. The ripple content of the output voltage is eliminated by using inductive and capacitive filters [4]. Figure 1 shows the circuit diagram of a boost converter. The circuit topology operates in two modes. In mode 1, the transistor S is turned ON, and the current flows through the inductor as shown in Fig. 2. By varying the conduction time t of the transistor S, the output voltage can be controlled. If T is the chopping period, then t1 = K t, where, K is the duty cycle of the boost converter [9, 10]. During the ON state, at time interval KT, the state-space equations are VO =  [V0 (t)] = 0

VI N 1−K

rL r L + rc

(1) 

i L (t) vc (t)

 (2)

The transistor S is turned OFF in mode 2 as shown in Fig. 3. During the time interval (1 − K) T, the state-space equation is Fig. 3 Boost converter at OFF condition [1]

28

R. Ali and V. S. Bhat

 [V0 (t)] = r L ||rc

rL r L + rc



i L (t) vc (t)

 (3)

The transfer function model of the boost converter is obtained using the state-space averaging method [9] as given below.   (1 − k)2 (R) 1 P(s) = RrC 1 − k (1 − k)2 + r L + k(1 − k) R+r

(4)

C

4 Bidirectional Converter Bidirectional converters are employed to transfer the power between two different DC sources in both forward and reverse direction. Bidirectional DC–DC converters have been a wide area of research for regenerative applications [4]. Bidirectional flyback converters are feasible due to its basic structure and effortless control [11]. The converters are used to transfer energy from source to load and from load to source. The energy storage components involved in converters suffer voltage stress [10]. Figure 4 shows a bidirectional converter, which is a DC–DC converter operating both in step-down and step-up mode. The evaluation of the converter in step-up mode can be done using the transfer function approach [12]. The transfer function for a bidirectional converter operating in boost mode is [13] P(s) =

Fig. 4 Bidirectional boost converter [10, 11]

M 1 + sτ + s 2 τ τd

(5)

Performance Analysis of Converter Circuit Transfer Function …

29

In (1), “M is the voltage gain, and τ is the converter time constant, which is not dependent on the switching frequency. Damping time constant is τd [13].” The output of the system is dependent on the damping time constant. Bidirectional converters can be modeled using the transfer function and state-space averaging [12, 13]. To keep the output voltage constant in DC–DC converters, closed loop controllers are utilized [14]. These controllers are designed to function at specific operating points, and it modulates the output voltage for swift change in input and output conditions [1]. In this research article, the boost converter and bidirectional converter in step-up mode have been considered for controller design and analysis.

5 Design of Controller “The three major control impacts of a PID controller include proportional action (P), integral action (I), and derivative action (D) [12, 15].” A shift in the input, which is directly proportional to the error of the controller, is because of the proportional action. The main focus of the integral action is to minimize the offset and provide a change in the input which is proportional to the integrated error. Further, derivative action is deployed to stabilize the system and to speed up the output in few instances and provide a change in input proportional to the derivative of the controlled variable. A combination of the above three actions leads to a PID controller [16]. The transfer function of a PID controller is C(s) = k p +

ki + kd s s

(6)

where k p is the gain of proportional action, ksi is the gain of the integral action, and kd is the gain of the derivative action. Figure 5 depicts the block diagram of a single-input single-output (SISO) feedback system with plant P(s), controller C(s), set-point r, error e, controller output u, plant output y, and disturbance d. Fig. 5 Block diagram of a SISO feedback system [17]

30

R. Ali and V. S. Bhat

5.1 Ziegler–Nichols Method The Ziegler–Nichols tuning method, based on sustained oscillations, is most widely applicable for Ziegler and Nichols (1942) first proposed PID controllers [16, 18]. “Ziegler–Nichols tuning method is known by different names like online, continuous cycling, and ultimate gain tuning method [18].” The ultimate gain ku and frequency Pu are obtained from the closed loop unit step responses by driving the proportional controller to critically stable state, ki the integral time constant is set to infinity, and the derivative time constant kd is set to zero. The tuning parameters are calculated using [18, 19] k P = 0.6ku , Ti =

Pu Pu , Td 2 8

(7)

5.2 Modified Ziegler–Nichols Method The modified Ziegler–Nichols method is an improvement in the closed loop Ziegler– Nichols tuning method [18]. The system is not driven to marginally stable condition as this method does not allow sustained oscillations. In this method, the integral time constant is set to infinity, and kd the derivative time constant is set to zero. The decay ratio is assumed to be 0.25, and based on this, the gain is decreased or increased [16]. Tud is the time period between two oscillating overshoots [18]. Using the modified Ziegler–Nichols method, the tuning parameters are calculated as k P = adjusted, Ti =

Tud 1.5k P , Td = k P Tud 6

(8)

5.3 Good Gain Method (GGM) An advanced PID tuning method known as the Good Gain method was first introduced by Finn Haugen in 2010 [8]. In this method of tuning, the system must have welldamped oscillations which lead to stability limit while tuning. First, the controller is set to proportional mode with k P = zero or one, kd = 0, and ki = 0. The value of k P is adjusted such that the system has some overshoot and slight undershoot. This value of k P , assumed to give better stability, is considered as K PGG . The time period between undershoot and overshoot is Tou [8]. Further, the tuning parameters are calculated using k P = 0.88kPGG , Ti = 1.5Tou Td = 0.25Ti

(9)

Performance Analysis of Converter Circuit Transfer Function …

31

5.4 Performance Indices The other best possible method to design a controller is based on the performance indices, which examine the entire response of the closed loop system [20]. “Integral of the absolute value of the error” (IAE) ∞ IAE = |e(t)|dt

(10)

0

“Integral of the square value of the error” (ISE) ∞ ISE =

e2 (t)dt

(11)

0

“Integral of the time weighted absolute value of the error” (ITAE) ∞ ITAE =

t|e(t)|dt

(12)

0

“Integral of the time weighted square of the error” (ISTE) ∞ te2 (t)dt

ISTE =

(13)

0

5.5 Uncertainties No mathematical model is found to be satisfactory to represent the performance of the actual plant. “The scarcity of a model to truly represent the dynamics of the actual system is because of the presence of various uncertainties [21].” Other sources of uncertainties may be imperfections in the measurement devices and implication of a higher-order nominal model. Uncertainties can be placed into two categories, i.e., signals with disturbance and the dynamic state of the system subjected to perturbations [22]. Disturbance signals are the ones, which affect the system and enhance the error, which include sensor noise and input and output disturbances. Perturbations are the deviation between the mathematical model and the actual dynamics of the plant, which may include modeled high-frequency dynamics, omitting the nonlinearities

32

R. Ali and V. S. Bhat

or considering linearities, reduced order models, variation in system parameters, etc. Due to these errors and uncertainties, the stability and performance of the system get affected. Thus, the analysis of system behavior with uncertainties must be essentially studied [21].

6 Results and Discussions The transfer function of the boost converter is obtained with state-space averaging method using (4). The boost converter topology with Vin = 12 V and Vout = 48 V with duty cycle = 0.75 [9] is   4.996s + 3.997 × 106   P1 (s) = 2 s + 780s + 1.056 × 106

(14)

The transfer function of a bidirectional converter in step-up mode is obtained with the transfer function approach using (5). In the step-up mode, the bidirectional converter topology has Vin = 14 V and Vout = 42 V with duty cycle = 0.6 [10]. P2 (s) =

4 0.001714s 2 + 0.08279s + 1

(15)

The open loop step response with unit step input and unity feedback of both the transfer functions P1 (s) and P2 (s) is analyzed using the Simulink model as shown in Fig. 6. The circuit modeling of both the converters is performed, and the responses are shown in Fig. 7. It is observed that the unit step responses have both overshoot and undershoot with steady-state error. To prevail over such problems, a PID controller

(a)

1.2

(b)

1 0.9

1

0.8 0.7

0.8

0.6

0.6

0.5 0.4

0.4

0.3 0.2

0.2

0.1

0

0

0.005

0.01

0.015

0.02

0.025

0.03

0

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

Fig. 6 Unit step response of (a) boost converter P1 (s) and (b) bidirectional converter P2 (s)

0.9

1

Performance Analysis of Converter Circuit Transfer Function …

60

(a)

45

(b)

40

Output voltage

50 40

Response

33

30 20

35 30 25 20 15

10

10 0 5 -10 0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

0

1

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Time (seconds)

1

Time (seconds)

Fig. 7 Response obtained from the circuit modeling of (a) boost converter, and (b) bidirectional converter

with three different tuning techniques is designed and simulated using the Simulink for both the converters. The robustness of a feedback control system to uncertainties and disturbances is of significant concern. The tuning values ki , ki , and kd are evaluated for the Ziegler–Nichols, modified Ziegler–Nichols, and the Good Gain methods using (7)–(9), respectively, and are tabulated in Table 1. A system can be analyzed with two conditions, namely servo response and regulatory response. The servo response of the system is analyzed for transfer functions of the boost and bidirectional converters. Figure 8 shows the servo response of the tuning techniques. The performance indices of the servo system are calculated using (10)–(13) and are tabulated in Table 2. It can be noted that the Ziegler–Nichols method gives better performance indices compared with the other two methods. The maximum overshoot and settling time of the servo response are tabulated in Table 3. The system response with disturbance of 0.1 is considered for the analysis of the regulatory response. The regulatory response for converters with PID controllers is simulated using the MATLAB/Simulink. The regulatory responses with Ziegler– Nichols, modified Ziegler–Nichols, and the Good Gain methods are shown in Fig. 9 for boost and bidirectional converters. The performance indices of the regulatory Table 1 Tuning values evaluated for P1 (s) and P2 (s) Controller tuning technique

P1 (s) =

P2 (s) =

4 0.001714s 2 +0.08279s+1

4.996s+3.997×106 s 2 +780s+1.056×106

PID tuning parameters

kP

ki

kd

kP

ki

kd

Ziegler–Nichols method

0.6

400

0.02

0.6

1

0.07

Modified Ziegler–Nichols method

0.09

45

0.004

0.9

0.81

0.002

Good gain method

0.04

8.89

0.004

0.77

8.05

0.18

34

R. Ali and V. S. Bhat

1.4

(a)

1.2 Unit Step Ziegler Nichol's Modified Ziegler Nichol's Good Gain Method

1.2

Unit Step Ziegler Nichol's Modified Ziegler Nichol's Good Gain

1

Response

1

Response

(b)

0.8 0.6

0.8 0.6 0.4

0.4 0.2 0.2 0 0

0 1

2

3

4

5

6

7

8

9

10

0

1

2

3

4

5

6

7

9

8

10

Time (seconds)

Time (seconds)

Fig. 8 Servo response of PID controller for (a) boost converter P1 (s) and (b) bidirectional converter P2 (s)

Table 2 Performance indices of the servo response 4.996s+3.997×106 s 2 +780s+1.056×106

Transfer function

P1 (s) =

P2 (s) =

4 0.001714s 2 +0.08279s+1

PI

ZN

ZN-modified

GGM

ZN

ZN-modified

GGM

IAE

0.002

ISE

0.001

0.022

0.026

0.250

0.307

0.031

0.016

0.022

0.043

0.142

ITAE

0.015

0.000

0.000

0.000

0.193

0.103

0.001

ISTE

0.000

0.000

0.000

0.017

0.023

0.000

Table 3 Percentage overshoot and settling time of servo response 4.996s+3.997×106 s 2 +780s+1.056×106

Transfer function

P1 (s) =

P2 (s) =

4 0.001714s 2 +0.08279s+1

Tuning techniques

ZN

ZN-modified

GGM

ZN

ZN-modified

GGM

Percentage overshoot

27.56

30.92

29.22

0

0

0

Settling time

0.013

0.010

0.008

3.662

2.040

0.327

response are tabulated in Table 4. The percentage overshoot and settling time of the servo response are tabulated in Table 5. The PID controller designed with the Good Gain method provides a noteworthy reduction in the error specifications for the disturbances given with fast settling time. Converters with +10% uncertainty were analyzed and simulated using the MATLAB/Simulink. Figure 10 depicts converter responses with +10% uncertainty. The performance indices of the converters with +10% uncertainty are tabulated in Table 6,

Performance Analysis of Converter Circuit Transfer Function …

(a)

1.8

1.2

35

(b)

1.6 1 1.2

Response

Response

1.4

1 0.8 0.6

0.8 0.6 0.4

0.4 0.2 0.2 0

0

10

20

30

40

50

60

70

80

0 0

90 100

10

20

30

40

50

60

70

80

90 100

Time (seconds)

Time (seconds)

Fig. 9 Regulatory response of PID controller for (a) boost converter P1 (s), and (b) bidirectional converter P2 (s)

Table 4 Performance indices of regulatory response Transfer function

P1 (s) =

PI

ZN

4.996s+3.997×106 s 2 +780s+1.056×106

ZN-modified

GGM

P2 (s) =

4 0.001714s 2 +0.08279s+1

ZN

ZN-modified

GGM

IAE

0.61

0.006

0.82

0.27

0.33

0.03

ISE

0.03

0.002

0.32

0.04

0.14

0.01

ITAE

18.48

0.03

4.63

1.50

1.64

0.23

ISTE

0.33

0.001

0.27

0.03

0.09

0.005

Table 5 Percentage overshoot and settling time of regulatory response 4.996s+3.997×106 s 2 +780s+1.056×106

Transfer function

P1 (s) =

P2 (s) =

4 0.001714s 2 +0.08279s+1

Tuning techniques

ZN

ZN-modified

GGM

ZN

ZN-modified

GGM

Percentage overshoot

0

0

0

0

0

0

Settling time

3.97

3.34

0.14

3.58

2.14

0.43

and the corresponding percentage overshoot and settling time are tabulated in Table 7. It is observed with +10% uncertainties that the Ziegler–Nichols method gives comparatively better results. Figure 11 shows the responses of the Ziegler–Nichols, modified Ziegler–Nichols, and Good Gain PID controllers.

36

R. Ali and V. S. Bhat 1.4

(a)

1.2 Unit Step Ziegler Nichol's Modified Ziegler Nichol's Good Gain Method

1.2

(b) Unit Step Ziegler Modified Modified Ziegler Nichol's Good Gain

1

Response

Response

1 0.8 0.6

0.6 0.4

0.4

0.2

0.2 0 0

0.8

1

2

3

4

5

6

7

8

9

0

10

0

2

1

3

4

5

6

7

9

8

10

Time (seconds)

Time (seconds)

Fig. 10 Servo response of PID controllers with +10% uncertainties, (a) boost converter P1 (s) and (b) bidirectional converter P2 (s) Table 6 Performance indices with +10% uncertainty Transfer function

P1 (s) =

P2 (s) =

4.4 0.001714s 2 +0.0836179s+1.01

PI

ZN

ZN-modified

IAE

0.002

0.65

GGM

ZN

ZN-modified

GGM

0.74

0.25

0.30

0.03

ISE

0.0007

ITAE

1.37

0.24

0.32

0.04

0.14

0.01

0.57

0.63

0.19

0.10

ISTE

7.72

0.001

0.10

0.13

0.17

0.02

0.0002

5.045s+4036970 1.01s 2 +787.8s+1067570

Table 7 Percentage overshoot and settling time with +10% uncertainty Transfer function

P1 (s) =

P2 (s) =

Tuning techniques

ZN

ZN-modified

GGM

ZN

ZN-modified

GGM

Percentage overshoot

29.22

29.22

21.341

0

0

0

Settling time

0.013

0.010

0.008

3.354

1.9

0.415

5.045s+4036970 1.01s 2 +787.8s+1067570

4.4 0.001714s 2 +0.0836179s+1.01

7 Conclusions In this research article, the converter topologies are modeled using the transfer function and circuit configuration. With unit step input, it is observed that the response had problems like overshoot and steady-state error. In order to overcome such problems, a PID controller for boost and bidirectional converters is designed. The MATLAB/Simulink is used to analyze both the servo and regulatory performance of the

Performance Analysis of Converter Circuit Transfer Function …

0.7

(a)

10

Time Series Plot:

37

(b) Ziegler Nichol's Modified Ziegler Nichol's Good Gain

Ziegler Nichol's Modified Ziegler Nichol's Good Gain

0.6

8

Response

0.5

data

0.4 0.3 0.2

6

4

2

0.1 0

0 -0.1 0

1

2

3

4

5

6

7

8

Time (seconds)

9

10

-2

0

1

2

3

4

5

6

7

8

9

10

Time (seconds)

Fig. 11 Controller responses for (a) boost converter P1 (s) and (b) bidirectional converter P2 (s)

converters. The comparison of settling time, overshoot, ISE, IAE and ITAE, and uncertainties for Ziegler–Nichols, modified Ziegler–Nichols, and Good Gain methods ensure that the designed PID controller provides efficient control action. The Good Gain method gives better performance indices compared with the other two methods. Converters with PID controllers give stable response with reduced overshoot and steady-state error.

8 Scope for Future Work The hardware implementation of the converter topologies can be the future work. Acknowledgements The authors would like to thank the Mangalore Institute of Technology and Engineering (MITE), Moodbidri, for creating an ecosystem for research and development.

References 1. Rashid MH (2003) Power electronics-circuits, devices and applications, 3rd edn. Pearson Education, Upper Saddle River 2. Saharia, Barnam (2014) A comparative study on converter topologies for maximum power point tracking application in photovoltaic generation. J Renew Sustain Energy 1–23 3. Li J, Liu J (2019) A novel buck–boost converter with low electric stress on components. IEEE Trans Ind Electron 66(4):2703–2713 4. Ibrahim O, Yahaya NZ, Saad N, Ahmed K (2015) Design & analysis of a digital controller for boost converter with renewable energy sources for domestic DC load. Appl Mech Mater 785:141–145

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5. Hari VM, Lakshmi P, Kalaivani R (2014) Time domain analysis of servo and regulatory responses of various controllers. In: Sixth international conference on advanced computing (ICoAC), pp 130–134 6. Lee C (2004) A survey of PID controller design based on gain and phase margins. Int J Comput Cognit 63–100 7. Bhowate A, Deogade S (2015) Comparison of PID tuning techniques for closed loop controller of DC-DC boost converter. Int J Adv Eng Technol 8(1):2064–2073 8. Haugen F (2010) The good gain method for PI (D) controller tuning. Tech Teach 1–7 9. Modabbernia MR, Sahab AR, Mirzaee TM, Ghorbany K (2012) The state space average model of boost switching regulator including all of the system uncertainties. In: Advanced materials research, vols 403–408. Tech Publications, Switzerland, pp 3476–3483 10. Hasaneen BM, Elbaset Mohammed AA (2008) Design and simulation of DC/DC boost converter. In: 12th international middle-east power system conference, Aswan, pp 335–340 11. Liu J (1995) Evaluate the performance of the systems with uncertainties. In: Proceedings of 1995 American control conference—ACC’95, Seattle, WA, USA, vol 6, pp 4427–4428 12. Sarif MSM, Pei TX, Annuar AZ (2018) Modeling, design and control of bidirectional DC-DC converter using state-space average model. In: 2018 IEEE symposium on computer applications & industrial electronics (ISCAIE), pp 416–421 13. Yang L-S, Liang TJ (2012) Analysis and implementation of novel bidirectional DC-DC converter. IEEE Trans Ind Electron 59(1):422–434 14. Hegazy O, Van Mierlo J, Lataire P (2011) Analysis, control and implementation of a highpower interleaved boost converter for fuel cell hybrid electric vehicle. Int Rev Electr Eng 6(4):1739–1747 15. Rosas-Caro JC, Ramirez JM, Peng FZ, Valderrabano A (2010) A DC-DC multilevel boost converter. IET Power Electron 3(1):129–137 16. Ang KH, Chong GCY, Li Y (2005) PID control system analysis, design, and technology. IEEE Trans Control Syst Technol 559–576 17. Gómez D, Bécares J, Janeiro JR, Gorostiaga L, Baeyens E, Moya J (2011) Assessment of Ziegler-Nichols tuned loops using control performance monitoring indices. ETFA2011, Toulouse, pp 1–4 18. Ibrahim O, Yahiya NZ, Saad N (2016) Comparative studies of PID controller tuning methods on a DC-DC boost converter. In: 6th international conference on intelligent and advanced systems (ICIAS), Kuala Lumpur, pp 1–5 19. Yadaiah N, Malladi S (2013) An optimized relation between Ti and Td in modified Ziegler Nichols PID controller tuning. In: 2013 IEEE international conference on control applications (CCA), Hyderabad, pp 1275–1280 20. Sathyanarayana V, Bavisetti N (2012) Analysis of novel DC-DC boost converter topology using transfer function approach. Int J Eng Res Technol (IJERT) 1(6) 21. Das A, Sharma V (2017) Modelling of uncertainty in control systems and design of a robust controller using H∞ method. In: International conference on intelligent computing and control systems, pp 1008–1013 22. Gu D-W, Petkov PH, Konstantinos MM (2005) Robust control design with MATLAB. Springer, London

Design of Low-Power Active High-Pass Filter Using Operational Transconductance Amplifier Sharil Nivitha Rodrigues and P. S. Sushma

Abstract The circuits which consume very low power are on high demand in recent years. It is a key challenge to the circuit developer to design a circuit which results in very low-power consumption. In this paper, active high-pass filters are designed which operates at low voltage and also has very low-power consumption. The filters are designed in Cadence Virtuoso tool using 180 nm CMOS technology at the supply of 1.6 V. Gain and cut-off frequency of the designed filters are determined. Keywords Active high-pass filter · Gate OTA · Series–parallel technique · Low power · Cut-off frequency

1 Introduction Fundamental requirement of any integrated circuit is the minimum power consumption. The desire for portability of electrical equipment has resulted in the need of low-power systems. Low-power dissipation is essential to have reasonable weight and battery life. The most common practice adopted to reduce power consumption is to operate the circuit at reduced supply voltages. If the circuit operates at low voltages, then it results in low-voltage swing with degraded circuit performance [1]. The supply voltage can be minimized only if all the transistors operate in the subthreshold region. Power consumption in analog CMOS circuits depends on the task, technology, circuit topology, and speed which are represented by bandwidth and the precision which is represented by signal-to-noise ratio (SNR) [2]. Op-amps are highly power-hungry devices due to low-output impedance [3–5]. Hence, there is a great demand for operational transconductance amplifier (OTA), S. Nivitha Rodrigues (B) · P. S. Sushma Department of ECE, NMAM Institute of Technology, Nitte, India e-mail: [email protected] P. S. Sushma e-mail: [email protected] P. S. Sushma REVA University, Yelahanka, India © Springer Nature Singapore Pte Ltd. 2020 S. Kalya et al. (eds.), Advances in Communication, Signal Processing, VLSI, and Embedded Systems, Lecture Notes in Electrical Engineering 614, https://doi.org/10.1007/978-981-15-0626-0_4

39

40

S. Nivitha Rodrigues and P. S. Sushma

Fig. 1 a Symbol of OTA, b low-frequency linear model of OTA

which converts voltage to current. OTA is voltage to current converter which takes differential voltage as input and gives current as the output. Thus, it acts as a voltagedependent current source. Therefore, it has large output impedance [6]. OTA acts as basic building blocks for many analog circuits. OTA is widely used for the conversion of differential voltage to current over Op-amps. OTA can have fully differential, pseudo differential or single-ended output [5]. The schematic symbol of single-ended OTA is shown in Fig. 1a. An ideal OTA has two input voltages Vin− and Vin+ as the inverting and non-inverting voltages applied to the circuit. The bias current Ibias controls the gain of the amplifier. The current Ibias is proportional to the transconductance of OTA [3]. Under ideal condition, the output current linearly follows the differential input voltages [7]. Figure 1b shows the low-frequency linear model of OTA. Clearly, the output voltage can be derived from the current by simply driving a resistive load [7]. The transconductance is the ratio of output current and input differential voltage. The output current and the transconductance can be adjusted since OTA can be used without feedback. The output current of OTA is given by Eq. (1). The power dissipation, unity gain bandwidth, gain margin, phase margin, slew rate, CMRR, etc., are the various performance parameters to be considered while designing the circuits using OTA. OTAs are used in the design of analog preprocessing circuits used in the applications such as sensors, portable devices, active analog filters and hearing aids [8–10]. OTA is widely used in the devices which operate at low frequency [8]. A number of active filters can be realized with the help of OTA. Power is the important factor in filter design. Iout = G m (Vin+ − Vin− )

(1)

Following this introduction, the paper briefs about the low-transconductance and low-power gate OTA using the series–parallel PMOS differential pair technique in Sect. 2. Section 3 describes the design of various active high-pass filters. In Sect. 4, simulation results for the design of active high-pass filter are explained. Finally, in Sect. 5, some concluding remarks are given.

Design of Low-Power Active High-Pass Filter Using Operational …

41

2 Low-Power and Low-Transconductance OTA Using Series–Parallel Differential Pair Technique The transconductance of OTA makes it a voltage-controlled current device. Low power and low transconductance are the basic need of circuits especially in biomedical applications. Use of complex OTA architectures increases the noise, mismatch offset, transistor area, and finally it results in circuit trade-offs [11]. There are many techniques to achieve low power with reduced transconductance. Some of the techniques are active source degeneration technique [3], current division and cancelation technique [5], differential pair [8], bias offset technique [12], feedforward technique [13], series–parallel technique [11], etc. The combination of series–parallel technique with differential input pair provides promising results in order to achieve minimum power and the transconductance.

2.1 Series–Parallel PMOS Differential Pair OTA Series–parallel technique is effective regarding power consumption and noise. This design of an OTA results in good linearity and reduced transconductance [11]. The series–parallel PMOS differential pair technique is the modification of basic current division technique. In current division technique, the transconductance is reduced by factor of N without improving the linearity [11] where N is the number of transistors in series and parallel. In series–parallel technique, the transconductance of an OTA can be calculated by using Eq. (2). Gm =

gm1 N2

(2)

where gm1 is the transconductance of the input transistor M 1 , and N is the number of transistors in series and parallel. The schematic of gate-driven series–parallel PMOS differential pair OTA is shown in Fig. 2. The use of series–parallel technique allows the implementation of the area efficient current divider circuit. The current mirror in the circuit utilizes the series– parallel association of transistors [11]. By copying several unitary transistors, it is possible to derive wide range of copies of a single bias current. By using high division factor of N 2 , it is possible to obtain the transconductance in terms of nS. The output branch in the circuit is biased with the current of 100 nA. For the design of active high-pass filters, this OTA can be used.

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Fig. 2 Schematic of series–parallel gate-driven PMOS differential pair OTA

2.2 Simulation Results of Proposed OTA The proposed OTA is designed using the technique of series–parallel gate-driven PMOS differential pair. The performance the OTA is verified by gpdk 180 nm CMOS technology using Cadence Virtuoso tool. The OTA circuit is operated at a supply voltage of 1.6 V. Power dissipation, DC gain, unity gain bandwidth, transconductance, gain, and phase margin of circuit are calculated. Transient response of series–parallel gate-driven PMOS differential pair OTA is shown in Fig. 3. For ±100 mV peak to peak of input, output swing of 1.4 mV is obtained. From Fig. 4, DC gain of series–parallel OTA is found to be 21.15 dB and power consumption of 194.336 nW as in Fig. 5. The main reason for the reduction of power is the low-supply voltage and low-frequency operation. As shown in Fig. 6, the gain margin and phase margin are observed to be 38.1 dB and 62.6°. Unity gain bandwidth of the circuit is seen to be 250.3 kHz, and CMRR of 62.96 dB is obtained. Table 1 shows the summary of the proposed series–parallel gate-driven PMOS differential pair OTA. The circuit operates at a voltage supply of 1.6 V. A very low transconductance is also achieved using the modified series–parallel technique and is seen to be 24.63 nS. Table 2 shows the comparison of simulation results of series–parallel gate-driven technology with similar work in the literature. It is observed that the power is reduced to nano Watts. Since very small bias current is given to the circuit, the transconductance is also reduced. Hence, low power and low transconductance are achieved using the series–parallel technique.

Design of Low-Power Active High-Pass Filter Using Operational …

Fig. 3 Transient response of series–parallel gate-driven PMOS differential pair OTA

Fig. 4 DC gain of series–parallel gate-driven PMOS differential pair OTA

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Fig. 5 Power curve of series–parallel gate-driven PMOS differential pair OTA

Fig. 6 Gain margin and phase margin of series–parallel gate-driven PMOS differential pair OTA

Design of Low-Power Active High-Pass Filter Using Operational … Table 1 Summary of proposed series–parallel gate-driven PMOS differential pair OTA

Table 2 Comparison of series–parallel gate-driven OTA simulated results

45

Design parameter

Series–parallel gate-driven technique

VDD (V)

1.6

IBIAS (nA)

100

Bandwidth (kHz)

74.93

Phase Margin

62.6°

Gain Margin (dB)

38.1

UGBW (kHz)

250.3

Gain BW Product (kHz)

1580

Common mode gain (dB)

41.91

DC gain (dB)

21.15

CMRR (dB)

62.96

Transconductance (S)

24.63 n

Power (W)

194.336 n

Design parameter

Reference [11]

Series–parallel gate-driven technique

Technology (µm)

0.18

0.18

Division factor

7

7

VDD (V)

2

1.6

IBIAS (nA)

40

100

Bandwidth (kHz)

1.2

74.93

Transconductance (S)

33 p

24.63 n

Power (W)

2µ

194.336 n

3 Design of Active High-Pass Filter Operational transconductance amplifier can be used in the design of active high-pass filter. Active filters are the filters which makes use of active and passive components. High-pass filter is the filter which attenuates the lower-frequency signals and passes only frequencies of interest. Various structures can be used to implement the active filters. Different structures are the MOSFET-C structure, Gm-C structure, OTAC structure, switched capacitor structure, etc. Among all these structures, Gm-C structure is preferred as it provides simple solution and results in low power and less area.

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Fig. 7 Schematic of simple feedback Gm-C high-pass filter

3.1 Simple Feedback Gm-C High-Pass Filter Schematic of simple feedback Gm-C high-pass filter is shown in Fig. 7. The structure requires very high linearity design. The circuit offers very low power with simple firstorder filter design [14]. The gain of the filter is adjusted using the transconductance Gm. HHP (s) =

sC sC + G m

(3)

The transfer function of simple feedback Gm-C high-pass filter is given by Eq. (3). On substituting τ = GCm in Eq. (3), the transfer function of simple feedback Gm-C high-pass filter is modified as Eq. (4). HHP (s) =

sτ sτ + 1

(4)

3.2 Bi-Quad Gm-C High-Pass Filter Schematic of bi-quad Gm-C high-pass filter is shown in Fig. 8. The structure provides better results than active RC structure in terms of power and frequency but at the cost Fig. 8 Schematic of bi-quad Gm-C high-pass filter

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of linearity. Without the use of resistors, it simplifies the design and reduces some problems caused by resistors. The two capacitors C 1 and C 2 connected to the OTAs determine the filter’s cut-off frequency and affect the Q-factor [14]. HHP (s) =

s 2 C1 C2 s 2 C1 C2 + sC1 G m2 + G m1G m2

(5)

The transfer function of bi-quad Gm-C high-pass filter is given by Eq. (5). On substituting τ1 = GCm1 and τ2 = GCm2 in Eq. (5), the transfer function of simple feedback Gm-C high-pass filter is modified as Eq. (6). HHP (s) =

s 2 τ1 τ2 s 2 + sτ1 + 1

(6)

3.3 Gain Boosted Gm-C High-Pass Filter The schematic of gain boosted Gm-C high-pass filter is shown in Fig. 9. The circuit is the second-order high-pass filter. The structure is similar to Taw-Thomas bi-quad structure [15]. The circuit provides improved gain at the cost of power when compared to simple bi-quad Gm-C structure. HHP (s) =

s 2 C1 C2 s 2 C1 C2 + sC1 G m2 + G m1 G m2

(7)

The transfer function of gain boosted Gm-C high-pass filter is given by Eq. (7). On substituting τ1 = GCm1 and τ2 = GCm2 in Eq. (7), the transfer function of gain boosted

Fig. 9 Schematic of gain boosted Gm-C high-pass filter

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Gm-C high-pass filter is modified in Eq. (8). HHP (s) =

s 2 τ1 τ2 s 2 + sτ1 + 1

(8)

4 Simulation Results of Active High-Pass Filters All the circuits operate at supply of 1.6 V using Cadence Virtuoso tool using 180 nm CMOS technology. The cut-off frequency, dB gain, and power dissipation of active high-pass filter are calculated.

4.1 Implementation of Simple Feedback Gm-C High-Pass Filter AC response of simple feedback Gm-C high-pass filter is shown in Fig. 10. The filter is implemented using the proposed series–parallel OTA in unity gain mode. In Fig. 11, the power curve of the simple feedback Gm-C high-pass filter is shown. The

Fig. 10 AC response of simple feedback Gm-C high-pass filter

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Fig. 11 Power curve of simple feedback Gm-C high-pass filter

Table 3 Analysis of simple feedback Gm-C high-pass filter in 180 nm technology

Capacitor C 1 (pF)

Gain (dB)

Power dissipation (nW)

Cut-off frequency (Hz)

2

3.48

194.3

2.28 k

11

3.68

194.3

1.56 k

20

3.92

194.3

678.24

cut-off frequency of the filter is 1.34 kHz for C = 10 pF. The power dissipation of 194.3 nW is seen but with a reduced gain of around 3.65 dB. Table 3 gives the complete analysis of simple feedback Gm-C high-pass filter. As the value of capacitor varies, the cut-off frequency also changes. The first-order simple feedback Gm-C structure offers very minimum power but at the cost of gain.

4.2 Implementation of Bi-Quad Gm-C Filters AC response of bi-quad Gm-C high-pass filter is shown in Fig. 12. The high-pass filter is implemented using the proposed series–parallel OTA in 180 nm CMOS technology. In Fig. 13, the power curve of the bi-quad Gm-C high-pass filter is represented. The cut-off frequency of the filter is 387.202 Hz for C 1 = C 2 = 10 pF. The power dissipation of 385.42 nW is seen but with a gain of around 4.71 dB. The complete analysis of bi-quad Gm-C high-pass filter is given in Table 4. The

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Fig. 12 AC response of bi-quad Gm-C high-pass filter

Fig. 13 Power curve of bi-quad Gm-C high-pass filter

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Table 4 Analysis of bi-quad Gm-C high-pass filter in 180 nm technology Capacitor C 1 (pF)

Capacitor C 2 (pF)

Gain (dB)

Power dissipation (nW)

Cut-off frequency (Hz)

10

2

3.93

385.42

598.7

10

11

4.23

385.42

367.28

10

20

4.88

385.42

244.554

value of capacitor C 1 uses a constant value of 10 pF. As the value of capacitor C 2 varies from 2 to 20 pF, the cut-off frequency also reduces. The increased power is due to the increase in the size of the bi-quad filter. The gain is slightly improved when compared to that of the simple feedback circuit. Bi-quad structure also results in low-frequency signals.

4.3 Implementation of Gain Boosted Gm-C High-Pass Filter Gain boosted high-pass filter is implemented using the proposed series–parallel OTA in 180 nm CMOS technology. AC response of gain boosted Gm-C high-pass filter is shown in Fig. 14. The power curve of the gain boosted Gm-C high-pass filter is shown in Fig. 15. For C 1 = C 2 = 10 pF, the cut-off frequency of the filter is 651.8 Hz. The circuit acts as gain boosting circuit and the gain is improved to 18.36 dB; whereas, increased power of 777.34 nW is obtained due to the increase in size of the circuit.

Fig. 14 AC response of gain boosted Gm-C high-pass filter

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Fig. 15 Power curve of gain boosted Gm-C high-pass filter

Table 5 Analysis of gain boosted Gm-C high-pass filter in 180 nm technology Capacitor C 1 (pF)

Capacitor C 2 (pF)

Gain (dB)

Power dissipation (nW)

Cut-off frequency (Hz)

10

2

18.07

777.34

1.85 k

10

11

18.19

777.34

929.36

10

20

18.36

777.34

621.81

Table 5 gives the complete analysis of bi-quad Gm-C high-pass filter. The value of the capacitors is varied to check the cut-off frequency. Gain boosting circuit offers the second-order filter structure using four Gm cells. As the name suggests, the gain is improved than the simple bi-quad filter structure.

5 Conclusion Design of low-transconductance low-power operational transconductance amplifier using series–parallel PMOS differential pair technique is proposed in this paper. The OTA operates at low voltage and hence the power is reduced. The transconductance of designed OTA is controlled by the supply voltage and bias current. This OTA provides very low-power consumption which is in terms of 194.3 nW with minimized transconductance of 24.63 nS. The proposed OTA is then used to realize the firstorder and second-order active high-pass filters. Further, gain of the circuit is improved

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using gain boosting filter structure. The gain, power and the cut-off frequency of the filters are calculated. All designs have been simulated using gpdk 180 nm CMOS technology using Cadence Virtuoso tool at 1.6 V supply. The designed filters provide Butterworth response with reduced power consumption for low-frequency applications.

References 1. Kumngern M, Dejhan K (2009) Voltage-mode low-pass, high-pass, band-pass biquad filter using simple CMOS OTAs. In: IEEE conference on international instrumentation and measurement technology (I2MTC’09), May, 2009, pp 924–927 2. Mathad RS (2014) Low frequency filter design using operational transconductance amplifier. In: IEEE conference on international scientific research (IOSR), pp 21–28 3. Garradhi K, Hassen N, Besbes K (2016) Low-voltage and low-power OTA using sourcedegeneration technique and its application in Gm-C filter. In: 11th international conference on integration, design & test symposium (IDT), Dec 2016, pp 221–226 4. Perez Bailon J, Marquez A, Calvo B, Medrano N, Sanz-Pascual MT (2018) A 1 V–1.75 µW Gm-C low pass filter for bio-sensing applications. In: 9th IEEE Latin American symposium on circuits & systems (LASCAS), Feb 2018, pp 1–4 5. Minaei S, Yuce E (2007) High-order current-mode low-pass, high-pass and band-pass filter responses employing CCCIIs. In: 6th international conference on in information, communications & signal processing, Dec 2007, pp 1–4 6. Gaonkar S, Sushma PS (2016) Modelling, design and analysis of high CMRR two stage gate driven operational transconductance amplifier using 0.18 µm CMOS technology. In: International conference on computing for sustainable global development, 2016 7. Sushma PS, Gaonkar S, Gurumurthy KS (2016) Design of high gain bulk-driven miller OTA using 180 nm CMOS technology. In: IEEE international conference on recent trends in electronics information communication technology, Sept 2016 8. Gaonkar S, Sushma PS, Fathima A (2015) Design of high CMRR two stage gate driven OTA using 0.18 µm CMOS technology. In: International conference on computer communication and informatics, May 2015 9. Arbet D, Rak M, Stopjakov V (2012) Comparison of gate-driven and bulk-driven current mirror topologies. IEEE J Solid State Circuits 41(12) 10. Zhao T, Liu X, Zhang G, Su Y (2016) Design of a programmable and low-frequency filter for biomedical signal sensing applications. In: IEEE international congress on image and signal processing, bio-medical engineering and informatics, 2016, pp 1746–1750 11. Arnaud A, Fiorelli R, Galup-Montoro C (2006) Nanowatt, sub-nS OTAs, with sub-10-mV input offset, using series-parallel current mirrors. IEEE J Solid State Circuits 41(9) 12. Geiger RL, Sanchez-Sinencio E (1985) Active filter design using operational transconductance amplifiers: a tutorial. In: IEEE conference on circuits and devices 13. Thanapitak S (2014) An 1-V, 74-dB, sub-Hz Gm-C filter based on a modular transconductance reduction technique. In: 11th IEEE international conference on electrical/electronics, computer, telecommunications and information technology engineering, May 2014, pp 1–5

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14. Gaonkar S, Sushma PS (2016) Modeling, design and analysis of high CMRR two stage gate driven operational transconductance amplifier using 0.18 µm CMOS technology. In: 3rd IEEE international conference on computing for sustainable global development, Mar 2016, pp 329– 334 15. Lu J, Yang T, Jahan MS, Holleman J (2014) A low-power 84-dB dynamic-range tunable Gm-C filter for bio-signal acquisition. In: 57th IEEE international midwest symposium on circuits and systems, Aug 2014, pp 1029–1032

Green Communication in Wireless Body Sensor Network—A Review P. Rachana and Durga Prasad

Abstract In trending research domains, wireless sensor network has become an emerging area in domains like green communication, health monitoring, smart energy home, building automation, etc. Wireless sensor node possesses limited processing capability, storage, and energy resources. Wireless body area network (WBAN) is a new arena in the wireless sensor network intended to provide a cutting edge in healthcare applications and useful in managing the abnormalities in parameters like ECG, respiration and temperature, and soon. The extant of sensor network for prolonged period is hinged on the amount of energy consumed during its operation. The power cost is dependent on the lowest consumption of power at the wireless sensor nodes which also empowers the enhanced energy efficiency. Green communication is an essential mechanism to improve the life span of WBAN. In this paper, major algorithms pertaining to various layers of WBAN architecture and few techniques that are leading to green communication are discussed. Keywords Energy efficiency · Nodes · Cluster · Sensor · Path

Abbreviations TDMA ECG LEACH IoMT QoS

Time-division multiple access Electrocardiogram Low-energy adaptive clustering hierarchy Internet of medical things Quality of service

P. Rachana (B) · D. Prasad Department of Electronics & Communication, NMAM Institute of Technology, Nitte, Karkala, Udupi 574110, Karnataka, India e-mail: [email protected] D. Prasad e-mail: [email protected] © Springer Nature Singapore Pte Ltd. 2020 S. Kalya et al. (eds.), Advances in Communication, Signal Processing, VLSI, and Embedded Systems, Lecture Notes in Electrical Engineering 614, https://doi.org/10.1007/978-981-15-0626-0_5

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1 Introduction In today’s human life, technological advancement has brought a new revolution and has transformed every field like smart cities, environment monitoring, home automation, and prediction. Usually, elderly people are affected by chronic diseases. Hence, they have to be residing in hospitals and kept under the supervision of medical professionals. According to a survey, people aged between 55 and 75 years will be doubled by 2050 [1]. Deaths due to chronic illness have been increased drastically these years. Hence, chronic or fatal diseases are the main causes of the untimely death of elderly people as well as the youth [2]. Lack of timely diagnoses and treatment is the common reason for these deaths. If these diseases are identified at their initial stages, the effect would not be severe. Patients still face challenges in the healthcare sector despite the advancements in computing and transmission technology. India is facing population growth but there is a lack of a number of healthcare centers with prime facilities especially in rural areas [3, 4]. WBAN was introduced in order to address healthcare challenges. This technology consists of biomedical sensor nodes (BSN) that can be worn on or implanted in the human body [5]. The physiological information from the human body is sensed, processed, and then sent to the medical center for further processing [6]. This will make a faster diagnosis of the patient’s problems and treatment can be initialized within a safe period. During these processes, there must be limited energy to be spent by the radio or communication block of the body sensor node. Energy efficiency has been improvised for wireless sensor network applications by many researchers in recent years [7–9]. The energy efficiency of sensor nodes is being strengthened by green communication techniques which aim at reducing the environmental brunt in communication [10]. Energy harvesting techniques along with the energy management algorithms are to be incorporated in wireless body sensor networks. Hence, it is urged to rely on algorithms that are fine-tuning the parameters at respective layers of the body sensor nodes as well as the power harvesting techniques to support the algorithms.

2 Health Monitoring System New paradigm in wireless monitoring system consists of few wireless body sensor nodes networked with Internet of Thing (IoT)-based body node coordinator [11, 12]. But today’s cloud technology allows the retrieval of the data from anywhere [13]. A state-of-the-art block diagram of a body sensor network with a hospital scenario is shown in Fig. 1. Each room consists of patients worn with body sensor nodes. All the sensor nodes upload the sensed data into the IoT-based access point using specific network technology. Then, the information will be made available in the cloud which can be retrieved for the analysis of parameter. The following are some of the works carried out in health monitoring and management systems.

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Fig. 1 IoT- and cloud-based body sensor network [14]

2.1 Vital Sign Monitor This is a mini patient monitoring system which works on a sensor network-based telemedicine system. This system examines the parameters such as respiration rate, heart rate, and ECG [1, 15]. This system utilizes Bluetooth technology which is All in One (AIO) wireless system and contains a fixed sensing element for efficient transmission. Using sensing hardware, the parameters such as ECG, heart rate, and respiration rate are obtained [16]. The vital sign monitor includes, – – – –

Transmission Acquisition Server validation and processing Emergency data upload to specialist

Through Bluetooth Low Energy (BLE), the information is transferred to smart phone. The information is securely transmitted to the server by an android application which acts as a coordinator. The beamed information from a remote server reaches a private network or network within the hospital. To compile the data, the application is hosted by the remote server. In case of emergency, the data is transmitted by the teleconsultant in the server to the specialist. High power efficiency is the prime characteristics of vital sign monitor. Through Android application, the secured data are observed by the doctor and if required, a link is established with the patient [17].

2.2 Real-Time Monitoring of Vital Signs Using Wireless Technique This system illustrates about portable system with wireless transmission capabilities in real time for the acquisition, processing, storing, and visualization of electrical activity of the heart. The ECG and BP signals are transmitted from data acquisition unit. Doctors can examine the ECG report of the people from rural and regional areas.

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This system is more applicable in emergency condition. Using ZigBee module, a wireless transmission is designed in which ECG signal is transmitted and displayed [18]. There are new amendments introduced for IoT-based systems such as IEEE 802.15.4e and experiments have been carried out by researchers on healthcare sector [19].

3 Energy-Efficient Protocols Across Different Layers The lower layers in the WBSN reference models are physical, medium access control, and network layers. Hence, the power management contributions to these layers are discussed below.

3.1 Role of Physical Layer on Energy Efficiency The lowermost layer, physical layer, is the majorly contributing layer in the energy management system as there is a radio block in the body sensor node. By switching off the radio which consumes high power and putting them to low power mode, energy efficiency can be achieved. During short idle timings, sleeping and rate adaptation parameter keeps the interfaces of network into sleep mode which optimizes the power. This method makes use of “duty cycle adjustment.” To design a new network, a technique called as “subnetting” which saves power in the configuration of active wireless sensor node is referred.

3.2 Role of Data Link Layer on Energy Efficiency The frames are divided into number of slots and then transmitted using TDMA scheduling is adopted in Multi-hop Sleeping MAC Protocol [20]. This reduces the collision probability and enhances the throughput. The data are transmitted to the destination following multiple paths from each node in “Efficient Cognitive Radio Protocol.” The power-save mode keeps the idle node in sleep and activates it at the time of reception and the energy is conserved. By avoiding the collisions, improving duty cycles and clustering, the energy conservation is achieved by the data link layer [21]. On the basis of traffic activity, sensor MAC introduced an enhanced version called “Timeout-MAC” which uses adaptable schedules. The nodes are put to sleep more frequently, using a down link scheduling and thus energy is conserved in “sleepoptimal fair attention (SOFA) scheduler.”

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3.3 Role of Energy Efficiency on Network Layer Adaptive contention window (ACW) examines the characteristics such as traffic conditions, residual energy, and success of data transmission. MAC layer issues are dealt by ACW which reduces the energy consumption and retransmission. Selection of nodes with good residual power reduces the untimely usage of power by the network. The energy conservation mechanism will be introduced while routing the packets effectively. This avoids possible failure of data reception and reduces retransmission rate in the nodes. More channel share and throughput are achieved with successful nodes which adjust the neighbor’s back-off time. In order to overcome long delay issues, the node energy level consideration is a prime objective in “min-max battery cost routing (MMBCR)” at the beginning of the packet transmission [22]. This mechanism improves the transmission capability of the network.

4 Algorithms An energy-efficient algorithm is a small piece of program, with decision-making capability, leading to an increased lifespan of the sensor node. Some of the wellknown algorithms are considered below.

4.1 Dijkstra’s Algorithm This algorithm is the most conventional algorithm, which determines the shortest path for delivering the packets. To recognize the shortest path to a destination, it works on the concept of neighboring node of candidate and source’s own computation. The main attribute of this algorithm is that, it determines the shortest path from a source to all destinations at any instant of time.

4.2 TDMA Scheduling in Convergecast The time domain is divided into timeslots in TDMA. In each timeslot multiple, spatially separated, transmissions which are non-interfering can be organized. The timeslots are allocated to nodes or edges by TDMA scheduling. The number of timeslots required for each node to communicate with the other nodes is reduced by these algorithms [23].

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4.3 Energy-Efficient Clustering Scheme (EECS) EECS resembles well-known LEACH protocol, but with some enhancement in the evolution of clusters and election of cluster head. The clusters are formed by dynamic sizing of nodes which is based on the distance of the node from the coordinator node. If the distance between the cluster and coordinator is large, it requires more transmission energy which is solved by using this algorithm [24].

4.4 Energy Conservation Clustering In order to minimize the intra-cluster energy, ability is introduced to sensor nodes in this algorithm which then controls the transmission power range. A special node called s-node is introduced which works as up-linker for a cluster. The sink receives the aggregated data from the s-node. The coordinator is situated far from the environment of the sensor node. After installation, the coordinator and sensor nodes are kept static. The newly sensed information from all nodes are gathered, aggregated, and transmitted to sink node periodically. The nodes will remain identical based on the energy content and processing abilities. All sensor nodes in the network will be identified by a Unique Identifier (ID). Based on the distance to intended recipient, the sensor node can adjust the amount of transmission power. Using the received signal strength, the distance between the nodes can be determined provided the power of the transmitting node is known. The distance is notified based on the received signal strength [25].

4.5 Virtual Circle Combined Straight Routing The main purpose of this tree-based routing scheme is to calculate the shortest path for sending the data to the intended receiving node. This algorithm contemplates the movement of the accessing node. Many-to-one communication method is used by the sink node, where data are sent to single node by many nodes. The entire network is covered based on the selection of number of cluster heads [26, 27].

4.6 Swap Rate Algorithm (SRA) The low-level energy of the node is determined using SRA algorithm. The main goal is to achieve higher reliability by swapping the tasks of low- and high-level energy nodes. In order to obtain uniform distribution, it has to consider the problem

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of network interruption. The low energy which is detected is distributed and hence termed as low-level energy detection algorithm.

4.7 Border Detection Algorithm Under common communication radius, two nodes can communicate. During the swapping process, there should not be any network interruption between border and communication nodes [28].

4.8 Adaptive Energy Optimization Algorithm (AEOA) A major factor of effectively managing the information of the disabled patients will be handled by adjusting the characteristics of the healthcare platform. An algorithm to optimize the energy usage based on the channel features of the nodes is proposed as the energy levels are associated with power drain in the IoMT system. This algorithm allocates the power level and wireless channel slot for elderly patients using IoMT system [29].

4.9 Power-Efficient Gathering in Sensor Information Systems (PEGASIS) This algorithm is constructed on the basis of effective power calculation. PEGASIS is dependent on LEACH. However, the algorithm does not provide portability for sensor hubs [30].

4.10 Low-Energy Adaptive Clustering Hierarchy-Centralized (LEACH-C) LEACH-C protocol is an improvement of LEACH. Base Station (BS) selects cluster head (CH) based on the location of node and residual energy in this algorithm. The information regarding the residual energy of the nodes as well as the location of each node are transmitted to BS in the setup phase. Base station estimates the average energy from the collected energy information. If the energy level of the node is greater than the average energy level, the node will be elected as CH. The identification code of the cluster head will then be transmitted to all nodes by the BS [31].

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4.11 Energy-Efficient Routing (EER) Technique EER protocol is based upon allocating a path cost to all the available routes and it chooses the minimum cost for data transmission. There are three parameters to determine the path cost: the number of nodes in the route, the amount of energy per message, and the left out energy in power sources after the transmission along the routes. The amount of energy in the system is represented by the sum of the remaining energy in the power source of the nodes that reach the sink node. The information about nodes as input is given by the cluster selection process [32]. This algorithm suits well for energy conservation.

4.12 Adaptive Greedy-compass Energy-aware Multipath Routing Protocol (AGEM) To minimize the energy consumption among nodes, this protocol performs load balancing. This is performed by a process called smart greedy forwarding [33].

4.13 Neural Network-Based Smart Sampling and Reliable Routing Protocol In order to achieve efficient energy and reliable packet routing, the neural data are collaborated with smart sampling. The received signal strength indicator (RSSI) is conserved in BS by establishing the beacon signals from BS and receiving the reply from sensor nodes [34].

4.14 Geographic Opportunistic Routing Scheme The main goal of this routing scheme is to enhance the QOS. It transmits an exact amount of payload on host machine. Delay, jitter, and throughput are the parameters that are required in this scheme. If any node wants to transmit packets, then this routing scheme will establish multi-hop communication [35].

4.15 Geographic Routing in Wireless Sensor Networks This routing method is used to enhance the scalability and network’s efficiency. Based on the relay position of sensor nodes, the next hop can be determined [36].

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4.16 Hexagonal Data Dissemination Protocol Over a geographic region, a virtual infrastructure is created by this routing protocol. Data caching and look-up queries are the two parameters proposed in this protocol. The aim is to enhance latency in the performance of the network and energy efficiency. Hexagonal cells are used for the geographic routing in a region. Location and wellknown network boundaries are the prerequisites of this approach [37].

4.17 Energy-Efficient Grid-Based Routing This technique creates grid-like structure called clusters. Based on the physical dimension of cell, header will be selected. The sink node which is present in a network forms dynamic topology. The dimension moves along the boundary line of cluster. To reduce the energy consumed in a network, a routing path is established which minimizes the cell headers. The main goal of this technique is to establish a routing path toward a BS by minimizing the number of cell headers and hence reducing network’s energy consumption. With the variable speed, sink node moves along the boundary of the sensor field. The data are sent with variable transmission rates by the nodes in a network. Thus, the routing scheme introduced major minimization in energy consumption for the network and thus it increases network lifetime [38].

4.18 Backbone-Based Virtual Infrastructure Approach This approach makes use of single-level multi-hop clustering. Across the sensor field, the formation of clusters takes place and the cluster head is selected. The network overhead is reduced by creating a tree structured framework. The main goal is to reduce the number of clusters which limits the scale of network [38].

4.19 Energy Harvesting in WBAN Energy harvesters are recognized as the energy scavengers. The other forms of energy such as kinetic energy, thermal energy, and electromagnetic energy are converted into electrical energy [39].

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4.20 Piezoelectric Mechanism At variable frequencies, the energy harvesting is possible by using piezoelectric transduction mechanism in WSN applications. They are effortless to fabricate. This process involves conversion of an energy that is absorbed by a transducer from WSN environment to an electrical voltage. This energy can be accumulated in power sources (batteries) for later use [40].

4.21 Energy Harvesting in Body Movement or Human Gaits For energy harvesting devices, the human gaits can be used as energy sources. Some of the human gaits through which energy harvesting can be implemented are acceleration pulse due to heel strike, acceleration due to leg swing and force due to weight of a person [41].

4.22 Thermoelectric Generator Thermoelectric generator is one form of energy harvesters that converts the heat steam flow into an electrical output power due to Seebeck effect [42].

4.23 Microbial Fuel Cells By utilizing the exo-electrogenic bacteria on anode from organic waste water, the electrical signal is generated. It can be implemented in the system that needs to keep track of energy source in a wireless sensor network application [43, 44]. The power thus obtained from any of the techniques may be used for power source of the sensor node as an extra power. Based on the amount of power supplied, the lifespan of the network will be improved. One such protocol is discussed below.

4.24 Energy Harvesting Routing Protocol for Wireless Sensor Networks (EHWSN) EWHSN protocol has a network model which forms a quad with cluster head and other members of the network. Selection of cluster head, base station process, and change of cluster head are the three phases of this protocol. The cluster head is placed at a position where the rate of energy harvesting is large. In this protocol, frequent

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change of CH is not required and there is less probability of energy getting drained off from every sensor node [45]. Thus, this technique makes use of harvesting principle with the routing process.

5 Conclusion The healthcare management sector is one of the major applications of wireless sensor network due to which there is a hike in the average age of human beings. Wireless body area network comprising of IoT-based coordinator, uploading the sensed data to cloud platform is attracting health management system and caretakers. Energy efficiency is one of the major lifespan deciding factors of the network that urges the designer to utilize algorithms to regulate the energy of the body sensor nodes. In this paper, we have reviewed about algorithms, protocols, schemes, techniques, and approaches for energy efficiency improvement on lower layers of wireless body sensor networks. These algorithms in association with energy harvesting techniques have lead to green communication. By these methods, we can optimize the consumption of energy and significantly improve the network’s lifetime. Future work includes the design and testing of green communication system in real time.

References 1. Movassaghi S, Abolhasan M, Lipman J, Smith D, Jamalipour A (2014) Wireless body area networks: a survey. IEEE Commun Surv Tutor 16(3):1658–1686 2. Mukhopadhyay SC (2015) Wearable sensors for human activity monitoring: a review. IEEE Sens J 15(3):1321–1330 3. Visaria L, Ved RR (2016) India’s family planning programme: policies, practices and challenges. Routledge, India 4. Singh S, Badaya S (2014) Health care in rural India: a lack between need and feed. South Asian J Cancer 3(2):143 5. Takei K, Honda W, Harada S, Arie T, Akita S (2015) Toward flexible and wearable humaninteractive health monitoring devices. Adv Healthc Mater 4(4):487–500 6. Anwar M et al (2018) Green communication for wireless body area networks: energy aware link efficient routing approach. Sensors 18:1–17. https://doi.org/10.3390/s18103237 7. Cardei M, Thai MT, Li Y, Wu W (2005) Energy-efficient target coverage in wireless sensor networks. In: Proceedings IEEE 24th annual joint conference of the IEEE computer and communications societies, vol 3. pp 1976–1984 8. Elshrkawey M, Elsherif SM, Wahed ME (2018) An enhancement approach for reducing the energy consumption in wireless sensor networks. J King Saud Univ-Comput Inf Sci 30(2):259– 267 9. Sarkar A, Murugan TS (2019) Cluster head selection for energy efficient and delay-less routing in wireless sensor network. Wirel Netw 25(1):303–320 10. Anwar M, Abdullah AH, Altameem A, Qureshi KN, Masud F, Faheem M, Cao Y, Kharel R (2018) Green computing for wireless body area networks: energy efficient link aware medical data dissemination approach. Sensors 18(10):3237–3237

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11. Couturier J, Sola D, Borioli G, Raiciu C (2012) How can the internet of things help to overcome current health care challenges. Commun Strat 87:67–81 12. Rodrigues JJ, Segundo DBDR, Junqueira HA, Sabino MH, Prince RM, Al-Muhtadi J, De Albuquerque VHC (2018) Enabling technologies for the internet of health things. IEEE Access 6:13129–13141 13. Rodgers MM, Pai VM, Conroy RS (2015) Recent advances in wearable sensors for health monitoring. IEEE Sens J 15(6):3119–3126 14. Prasad D, Chiplunkar NN, Nayak KP (2016) Performance analysis of the physical and medium access control layer parameters with effect of varying transmission power using IEEE 802.15.4 standard for wireless body sensor network. In: 6th international conference on advances in computing & communications (ICACC 2016), Elsevier’s Science Direct Procedia of Computer Science, Cochin, pp 639–646 15. Prasad D, Chiplunkar NN, Nayak KP (2017) A trusted ubiquitous healthcare monitoring system for hospital environment. Int J Mob Comput Multimed Commun (IJMCMC) 8(2):14–27 (IGI Global Publications) 16. Imani S, Bandodkar AJ, Mohan AV, Kumar R, Yu S, Wang J, Mercier PP (2016) A wearable chemical–electrophysiological hybrid bio-sensing system for real-time health and fitness monitoring. Nat Commun 7:11650 17. Priya L, Hariprasad R, Raghul R (2014) Real time monitoring of vital signs using wireless technique. In: International conference on green computing communication and electrical engineering (ICGCCEE), Coimbatore, pp 1–7 18. Shivakumar NS, Sasikala M (2014) Design of vital sign monitor based on wireless sensor networks and telemedicine technology. In: International conference on green computing communication and electrical engineering (ICGCCEE), Coimbatore, pp 1–5 19. Momoda M, Hara S (2015) A cooperator-assisted wireless body area network for real-time vital data collection. EURASIP J Wirel Commun Netw 1:238 20. Ye W, Heidemann J, Estrin D (2002) An energy-efficient MAC protocol for wireless sensor networks. In: Proceedings twenty-first annual joint conference of the IEEE computer and communications societies, vol 3. pp 1567–1576 21. Su H, Zhang X (2008) CREAM-MAC: an efficient cognitive radio-enabled multi-channel MAC protocol for wireless networks. In: 2008 international symposium on a world of wireless, mobile and multimedia networks, pp 1–8 22. Muhammad B, Yusof KM (2019) Green mesh network of UAVs: a survey of energy efficient protocols across physical, data link and network layers, pp 1–6 23. Sengaliappan M, Marimuthu A (2014) Enhanced tree routing algorithms in wireless sensor network. In: International conference on green computing communication and electrical engineering (ICGCCEE), Coimbatore, pp 1–11 24. Chunawale A, Sirsikar S (2014) Minimization of average energy consumption to prolong lifetime of wireless sensor network. In: IEEE global conference on wireless computing & networking (GCWCN), Lonavala, pp 244–248 25. Tinker MS, Chinara S (2015) Energy conservation clustering in wireless sensor networks for increased life time. In: Second international conference on advances in computing and communication engineering, Dehradun, pp 7–10 26. Nake NB, Chatur PN (2016) An energy efficient grid based routing in mobile sink based wireless sensor networks. In: Second international conference on science technology engineering and management (ICONSTEM), Chennai, pp 1–5 27. Kaur N, Narula AK (2017) MVGDRA: modified virtual grid based dynamic routes adjustment scheme for mobile sink-based wireless sensors networks 28. Pavithra NG, Sumithra MG, Shalini E (2016) Efficient energy management in wireless sensor networks using node rotation. In: Online international conference on green engineering and technologies (IC-GET), Coimbatore, pp 1–5 29. Pirbhulal S, Wu W, Mukhopadhyay SC, Li G (2018) Adaptive energy optimization algorithm for internet of medical things, pp 269–272. https://doi.org/10.1109/icsenst.2018.8603601

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30. Sangeetha K, Shanthini J, Karthik S (2018) A review on energy conservation techniques in wireless sensor networks, pp 1–5. https://doi.org/10.1109/icsns.2018.8573621 31. Vimal V, Nigam JM (2017) Ensuring uniform energy consumption in non-deterministic wireless sensor network to protract networks lifetime. World academy of science, engineering and technology. Int J Electron Commun Eng 11(9) 32. Elbassiouny SO, Hassan AM (2015) Energy-efficient routing technique for wireless sensor networks under energy constraints. In: International wireless communications and mobile computing conference (IWCMC), Dubrovnik, pp 647–652 33. Bouatit MN, Boumerdassi S, Djama A, Milocco RH (2017) Energy-efficient preventive mechanism for fault tolerance in wireless multimedia sensor networks. In: IEEE 86th vehicular technology conference (VTC-Fall), Toronto, pp 1–5 34. Vinutha CB, Nalini N, Veeresh BS (2017) Energy efficient wireless sensor network using neural network based smart sampling and reliable routing protocol. In: International conference on wireless communications, signal processing and networking (WiSPNET), Chennai, pp 2081– 2085 35. Zeng K, Lou W, Yang J, Brown DR III (2007) On throughput efficiency of geographic opportunistic routing in multihop wireless networks. Mob Netw Appl 12(5):347–357 36. Gupta HP, Rao SV, Yadav AK, Dutta T (2015) Geographic routing in clustered wireless sensor networks among obstacles. IEEE Sens J 15(5):2984–2992 37. Hawbani A, Wang X, Kuhlani H, Karmoshi S, Ghoul R, Sharabi Y, Torbosh E (2017) Sinkoriented tree based data dissemination protocol for mobile sinks wireless sensor networks. Wirel Netw, 1–12 38. Khan AW, Abdullah AH, Razzaque MA, Bangash JI (2015) VGDRA: a virtual grid-based dynamic routes adjustment scheme for mobile sink-based wireless sensor networks. IEEE Sens J 15(1):526–534 39. Wang Z, Leonov V, Fiorini P, Van Hoof C (2009) Realization of a wearable miniaturized thermoelectric generator for human body applications. SensS Actuators A Phys 156:95–102. https://doi.org/10.1016/j.sna.2009.02.028 40. Elahi H, Eugeni M, Gaudenzi P (2018) A review on mechanisms for piezoelectric-based energy harvesters. Energies 11:1850. https://doi.org/10.3390/en11071850 41. Ylli K, Hoffmann D, Willmann A, Becker P, Folkmer B, Manoli Y (2015) Energy harvesting from human motion: exploiting swing and shock excitations. Smart Mater Struct 24:025029. https://doi.org/10.1088/0964-1726/24/2/025029 42. Akhtar F, Rehmani MH (2017) Energy harvesting for self-sustainable wireless body area networks. IT Prof 19(2):32–40 43. Crepaldi M, Chiolerio A, Tommasi T, Diana HD, Canavese G Stassi S, Demarchi D, Pirri FC (2013) A low complexity wireless microbial fuel cell monitor using piezoresistive sensors and impulse-radio ultra-wide-band. Proc SPIE Int Soc Opt Eng 8763:876311–876319. https://doi. org/10.1117/12.2017553 44. Tommasi T, Chiolerio A, Crepaldi M Demarchi D (2014) A microbial fuel cell powering an alldigital piezoresistive wireless sensor system. Microsyst Technol 20. https://doi.org/10.1007/ s00542-014-2104-0 45. Geetha N, Sankar A, Pankajavalli PB (2014) Energy efficient routing protocol for wireless sensor networks—an eco-friendly approach. In: 3rd international conference on eco-friendly computing and communication systems, Mangalore, pp 105–109

Outage Performance Analysis of Hybrid FSO/RF System Using Rayleigh and K-Distribution U. Anushree and V. K. Jagadeesh

Abstract In this work, the outage probability of hybrid FSO/RF system using decode and forward (DF) relay is derived. Rayleigh distribution is used for modeling of the radio frequency communication (RF) link and K-distribution is used for modeling free space optical communication (FSO) link. Decode and forward relaying scheme is considered, which decodes the received data and then retransmits the re-encoded data and removes the noise present. The expressions are derived for probability density function (PDF), cumulative distributive function (CDF), and outage probability in terms of Meijer G-function. Keywords K-distribution · Rayleigh distribution · Decode and forward · PDF · CDF · Outage probability

1 Introduction Radio frequency (RF) systems support both line-of-sight (LOS) and no-line-of-sight (NLOS) transmission and reception of data. It is also able to transmit large quantities of data over extremely large distances. However some of the disadvantages of the RF systems are it suffers from radio interference, electrical interference, scarcity of the spectrum due to increasing demand, requires more time for installation, lowers data rates, not cost-effective, and results in some of the health issues. With the increase in the demand and limited spectrum, it is difficult to offer secure and reliable communication to all the users by using only RF systems. All these disadvantages led to the development of new systems, such as FSO. In FSO communication, the data are transmitted using the light propagating in open space. There are several advantages of FSO such as low cost, easy installation, U. Anushree (B) · V. K. Jagadeesh Department of Electronics and Communication Engineering, NMAM Institute of Technology, Nitte, Karkala, Udupi, Karnataka, India e-mail: [email protected] V. K. Jagadeesh e-mail: [email protected] © Springer Nature Singapore Pte Ltd. 2020 S. Kalya et al. (eds.), Advances in Communication, Signal Processing, VLSI, and Embedded Systems, Lecture Notes in Electrical Engineering 614, https://doi.org/10.1007/978-981-15-0626-0_6

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no radio frequency interference, requires very less time for installation, no licensing is required, low complexity, very high bandwidth, low transmission power, and no electrical interference. FSO is a LOS-based technology. Since the transmission media is open space, it is not possible to have the transmitter and receiver in LOS. FSO provides higher data rates of about 1.25 Gbps. Even though it provides the higher data rates, it suffers from the atmospheric attenuation which results in the reduction in intensity of signal as the distance increases which leads to the degradation of the system. FSO systems can be used as a solution when the RF link fails or there is overload of traffic in the RF link. Whenever the RF link fails, FSO system can be used as an alternate path for the data transmission since it requires very less time for installation, no licensing is required, less complexity, and also low cost. Both FSO and RF systems have several advantages over each other. Hence, this led to the development of hybrid FSO/RF system that incorporates both of these systems. Here, the disadvantage of one system is overcome by another system. The RF system can be used when the information has to be transmitted over larger distances or where there is no line of sight existing between the transmitter and receiver. Hence, combining both these systems leads to combining of the advantages of both systems. Hence, it provides reliable communication over larger areas for a large number of users with higher data rates. Decode and forward (DF) relay improves the performance of the system by reducing the noise in the signal. DF relay first decodes the received signal to obtain the original that was transmitted earlier by the sender. Then, the decoded information is re-encoded and retransmitted to the desired receiver. In this system, since the data are first decoded and then encoded and transmitted, the noise is not amplified as it is removed during the decoding process. In this work, the expressions are derived for probability density function (PDF), cumulative distributive function (CDF), and outage probability for combined RF and FSO system using the Meijer G-function. Meijer G-function is used for deriving the expressions since it is easily available in software packages like MATLAB. The channel is modeled using K-distribution and Rayleigh distribution for FSO and RF link, respectively. The plot for outage probability versus signal-to-noise ratio (SNR) is obtained for different values of SNR and various values of α.

1.1 Related Work In paper [1], the performance of FSO system considering the K-distribution is evaluated. In paper [2], the performance analysis of the RF/FSO system is carried out, where Rician distribution is used for characterizing the RF link and Gamma–Gamma distribution is used for characterizing the FSO link. Nakagami-m and Gamma– Gamma distribution are used in [3] to model the RF and FSO channel, respectively. In paper [4], outage performance for hybrid RF/FSO system is carried out using

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Rayleigh distribution for RF system and Gamma–Gamma distribution for FSO system. In paper [5–7] the performance of hybrid RF/FSO is studied.

2 System Model Hybrid FSO/RF system consisting of decode and forward relay is shown in Fig. 1. The source does not directly communicate with that of the destination, but through relay since there is no LOS between the source and destination. Hence, there are two links, one link that exists between the source and relay, other between the relay and destination. The source to relay is characterized by K-distribution and relay to destination is characterized by the Rayleigh distribution. DF relay is used to convert the light signals into the RF signal. The overall SNR γ , for a DF-based system in [3], is given as, γ = min(γ1 , γ2 )

(1)

where γ 1 is the SNR of the FSO and γ 2 is the SNR of the RF system.

2.1 Modeling of FSO Link For strong atmospheric turbulence, K-distribution can be used for modeling FSO link, i.e., between the source and relay. The PDF f γ 1 (γ ) as given in [1] for K-distribution is f γ 1 (γ ) =

∝(

∝−1 2

) γ ( α−3 4 )

(∝)γ1 (

α+1 4

)

 √  K α−1 2 α I

(2)

where γ1 is the average SNR of the relay to destination, G(.) is Gamma function and is given in [8], K  (.) is the  th order Bessel function, α is discrete number of scatters as defined in paper [1], and I is the irradiance. The PDF can also be represented in the form as shown below [1], Fig. 1 Channel model for hybrid FSO/RF system

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⎞ ⎛ 

  ∝−1 α−3  ) ( ) ( γ ⎟ ∝ 2 γ 4 ⎜ K α−1 ⎝2 α f γ 1 (γ ) = ⎠ α+1 ( ) γ 4 1 (∝)γ1

(3)

We can express K  (.) as Meijer G-function, i.e.,  K v (r ) =

1/2G 2,0 0,2

 r 2  − 4  v2 , − v2

(4)

Using (4) in (3), we get   ) γ ( α−3 4 ) γ 1/2G 2,1 f γ 1 (γ ) = α+1 1,3 α ( ) γ 1 (∝)γ1 4 ∝(

∝−1 2

− α−1 , − 1−α 2 2

 (5)

The CDF Fγ 1 (γ ) is obtained as,  Fγ 1 (γ ) =

∞

f γ 1 (γ )dγ

(6)

0

As given in [3] we have,     γ  1 1 2,1 G α Fγ 1 (γ ) = (α) 1,3 γ1  α, 1, 0

(7)

2.2 Modeling of RF Link Rayleigh distribution can be used for modeling the RF link when there are large number of objects in the free space that scatter the RF signal along its path to the receiver and also when there is no proper LOS between the source and the destination. The PDF f γ 2 (γ ) for Rayleigh distribution as given in [9] is,  γ 1 exp − γ2 γ2

f γ 2 (γ ) =

(8)

where γ2 is the average SNR of the source to relay. The CDF Fγ 2 (γ ) can be obtained as,  Fγ 2 (γ ) 0

∞

f γ 2 (γ )dγ

(9)

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Substituting (8) in (9) and the upon simplification as done in [9] we get, 

γ Fγ 2 (γ ) = 1 − exp − γ2

(10)

3 Performance Analysis The equation for the outage probability of the overall system is derived using the PDF and CDF equations derived for individual systems. The outage probability is used to define the performance of the system.

3.1 Probability Density Function The PDF of system based on DF relay is given in [3] as shown below, f γ (γ ) = f γ 1 (γ ) + f γ 2 (γ ) − f γ 2 (γ )Fγ 1 (γ ) − f γ 1 (γ )Fγ 2 (γ ) Substituting Eqs. (5), (7), (9), and (10) in (11) we get,     ) γ ( α−3 4 ) γ  − 2,1 1/2G 1,3 α f γ (γ ) = α+1 , − 1−α γ1  α−1 (∝)γ1 ( 4 ) 2 2        1 1 γ  1 1 γ γ 2,1 − + G exp − exp − α γ2 γ2 γ2 γ2 (α) 1,3 γ1  α, 1, 0 ⎡ ∝−1 α−3    ⎤  − ∝( 2 ) γ ( 4 ) γ  ∗ 1/2G 2,1 1,3 α ⎢ (∝)γ ( α+1 ⎥ γ1  α−1 , − 1−α 4 ) −⎣  1 (12) ⎦ 2 2   γ 1 − exp − γ2      ∝−1 α−3 γ  γ ∝( 2 ) γ ( 4 ) 1 − 2,1 1/2G exp − f γ (γ ) = α + α+1 1,3 , − 1−α γ1  α−1 γ2 γ2 (∝)γ1 ( 4 ) 2 2

     1 2,1 γ  1 1 γ − exp − G 1,3 α γ2 γ2 (α) γ1  α, 1, 0

    ∝−1 α−3 ∝( 2 ) γ ( 4 ) γ  − 2,1 − 1/2G 1,3 α α+1 , − 1−α γ1  α−1 (∝)γ1 ( 4 ) 2 2 ∝(

∝−1 2

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    ∝−1  α−3 γ  γ ∝( 2 ) γ ( 4 ) − 2,1 ∗ 1/2G 1,3 α + exp − , − 1−α γ2 (∝)γ1 ( α+1 γ1  α−1 4 ) 2 2 (13)

       1 1 γ  1 γ γ 1 − G 2,1 exp − α = exp − 1,3 γ2 γ2 γ2 γ2 (α) γ1  α, 1, 0

     ∝−1 α−3 γ ∝( 2 ) γ ( 4 ) γ  − 2,1 + exp − 1/2G 1,3 α (14) , − 1−α γ2 (∝)γ1 ( α+1 γ1  α−1 4 ) 2 2        γ  1 γ 1 1 2,1 G 1− α f γ (γ ) = exp − γ2 γ2 (α) 1,3 γ1  α, 1, α     ∝−1 α−3 ∝( 2 ) γ ( 4 ) γ  − 2,1 + 1/2G 1,3 α (15) α+1 , − 1−α γ1  α−1 (∝)γ1 ( 4 ) 2 2 

3.2 Cumulative Distributive Function For the system based on DF relay CDF is given as [3], Fγ (γ ) = Fγ 1 (γ ) + Fγ 2 (γ ) − Fγ 1 (γ )Fγ 2 (γ )

(16)

Substituting (7) and (10) in (16) we get,      γ γ  1 1 2,1 + 1 − exp − G 1,3 α Fγ (γ ) = (α) γ1  α, 1, 0 γ2

      1 γ  1 γ 2,1 G − 1 − exp − α γ2 (α) 1,3 γ1  α, 1, 0

(17)

Simplifying (17) we get,        1 γ  1 γ 1 2,1 G = exp − 1− α γ2 γ2 (α) 1,3 γ1  α, 1, 0

    ∝−1 α−3  ∝( 2 ) γ ( 4 ) γ −  + 1/2G 2,1 α+1 1,3 α , − 1−α γ1  α−1 (∝)γ1 ( 4 ) 2 2

      γ 1 γ  1 γ 2,1 + exp − G = 1 − exp − α γ2 γ2 (α) 1,3 γ1  α, 1, 0

(18)

(19)

Outage Performance Analysis of Hybrid FSO/RF System …

      γ  1 γ 1 2,1 G Fγ (γ ) = 1 − exp − α 1− γ2 (α) 1,3 γ1  α, 1, 0

75

(20)

3.3 Outage Probability One of the factors that defines the performance of a system is the outage probability. In fading environment, the power of the signal received is not a constant value, i.e., it varies randomly. Hence, the received signal SNR is also not constant and varies randomly. Hence, the outage probability gives the probability that the information sent cannot be recovered from the received signal, i.e., probability that the received SNR is less than the preset threshold. The probability of outage in the given system as defined in [3] is given as, POUT (γth ) = Fγ (γth )

(21)

Substituting (20) in (21) we get,       γth  1 γth 1 2,1 G α 1− POUT (γth ) = 1 − exp − γ2 (α) 1,3 γ1  α, 1, 0

(22)

where γth is the preset threshold.

4 Results The graphs are plotted for outage probability POUT (γth ) vs average SNR and are shown in Figs. 2 and 3. In Fig. 2, γth is taken as 10 dB and α is assumed as 2 in the first case and then 1 in the second case. Comparing the plots for α = 2 and that of α = 1, it can be seen that when α = 1, the probability of outage has decreased by a small amount as compared to α = 2, since there is reduction in the discrete number of scatters. In Fig. 3, γth is taken as 20 dB and α is assumed as 2 in first case and then 1 in the second case. Upon comparing the plots for α = 2 and that of α = 1, it can be observed that with α = 2 there is a slight increase in outage probability when compared to α = 1 due to increase in the number of scatters. On comparing both the graphs, we can see that the values obtained for POUT (γth ) when γth = 10 dB is less compared to γth = 20 dB.

76 Fig. 2 Outage probability vs average SNR (dB) for α = 1, 2 and γth = 10 dB

Fig. 3 Outage probability vs average SNR (dB) for α = 1, 2 and γth = 20 dB

U. Anushree and V. K. Jagadeesh

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5 Conclusions In this work, the outage performance of hybrid FSO/RF system is obtained by considering K-distribution for FSO and Rayleigh distribution for RF link. The expressions are obtained for the probability of the outage and also for CDF and PDF for hybrid system using the equations of the individual systems. Further, it was seen that with the increase in the values for α, the probability of the outage increased by a slight amount. Here, α is the discrete number of scatters. Hence, as the number of scatters in the environment increases, the probability of outage also increases. With the increase in SNR, the outage probability of the system reduces. With the increase in γth , the probability of outage also increases. Hence, it can also be noted that as the number of scatters increases, the outage probability also increases and with the increase in SNR values, the probability of outage reduces.

6 Future Works In this paper, only the outage probability is derived for the hybrid system that is used for evaluating the performance of the system. Whereas bit error rate, capacity, and also moment generating functions can also be derived further for the evaluation of the performance of the system. The plots for each of these individual parameters that are used for evaluation can be obtained for better understanding of the system. Instead of using K-distribution for FSO, various other channel models can be used. Similarly, we can use a different model for RF link. Here, we have considered only FSO link which exists between sender and DF relay and RF link that exists between DF relay and the receiver. In future, we can design a system with both the links between sender to relay and relay to receiver, so that we can switch between the two links based on the requirements such as number of active users or if failure occurs in one of the links, also based on the environmental conditions such as fading, atmospheric attenuation we can switch to another link.

References 1. Neha M, Sairam D (2016) Outage analysis of relay assisted FSO systems over K-distribution turbulence channel. In: International conference on electrical, electronics, and optimization techniques, pp 2965–2967 2. Saidi H, Tourki K, Hamdi N (2016) Performance analysis of PSK modulation in DF dual-hop hybrid RF/FSO system over gamma gamma channel. In: International symposium on signal, image, video and communications, pp 23–216 3. Anees S, Bhatnagar MR (2015) Performance evaluation of decode and forward dual-hop asymmetric radio frequency free space optical communication system. Inst Eng Technol J, 1–9

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4. Bag B, Das A, Ansari IS (2018) Performance analysis of hybrid FSO systems using FSO/RF-FSO link adaptation. IEEE Photon J 5. Jagadeesh VK, Ansari IS, Palliyembil V, Muthuchidambaranathan P, Qaraqe KA (2016) Channel capacity analysis of a mixed dual-hop radio-frequency–free space optical transmission system with Málaga distribution. IET Commun 10(16):2119–2124 6. Jagadeesh VK, Palliyembil V, Ansari IS, Muthuchidambaranathan P, Qaraqe KA (2018) Performance analysis of relay assisted mixed dual-hop RF-FSO systems with pointing errors. In: International telecommunications conference, 06 July 2018, pp 15–29 7. Palliyembil V, Vellakudiyan J, Muthuchidamdaranathan P, Tsiftsis TA (2018) Capacity and outage probability analysis of asymmetric dual-hop RF–FSO communication systems. IET Commun 12(16):1979–1983 8. Zedini E, Soury H, Alouini MS (2016) On the performance analysis of dual-hop mixed FSO/RF systems. IEEE Trans Wirel Commun 15(5):3679–3689 9. Ansari IS, Yilmaz F, Mohamed-Slim A, On the performance of mixed RF/FSO dual-hop transmission systems

Development of Reliable On-Board Computer of STUDSAT-2 Rakshith Devadiga, Sachin Kainthila, Abhishek Bangera, Amshak Shanbhogue, Durga Prasad and K. S. Shivaprakasha

Abstract Small satellites in recent years are emerging in the space innovation and accomplishing the objectives set by bigger satellites. The mission life of this class of satellites is short due to the confinement in mass and energy storage. In addition to this, the commercial off-the-Shelf (COTS) components used in the development challenge the mission life of this satellite due to its higher failure rates. This paper portrays the design of reliable on-board computer of STUDSAT-2, a twin nanosatellite mission being under development by undergraduate students. The paper describes the redundancy method incorporated in the design of satellite at different levels. Finally, the power budget analysis is summarized in the results. Keywords STUDSAT-2 · Attitude determination and control system (ADCS) · Electrical power system (EPS) · Command and data handling (C & DH)

1 Introduction Centre for Small Satellite Research (CSSR) is an R&D from NMIT, Bengaluru, India, is currently working in the area of small satellite research and development. The centre has its heritage for launching the first Indian Pico-satellite, STUDSAT-1 in 2010 which is designed and developed by a team of engineering students. Team STUDSAT is continuing with the second mission STUDSAT-2, a twin nano-satellite which will be launched together into the orbit. Figure 1 shows the model of STUDSAT-2. R. Devadiga · S. Kainthila · A. Bangera · A. Shanbhogue · D. Prasad · K. S. Shivaprakasha (B) Department Electronics and Communication, NMAMIT, Nitte, Udupi, Karnataka 574110, India e-mail: [email protected] R. Devadiga e-mail: [email protected] S. Kainthila e-mail: [email protected] D. Prasad e-mail: [email protected] © Springer Nature Singapore Pte Ltd. 2020 S. Kalya et al. (eds.), Advances in Communication, Signal Processing, VLSI, and Embedded Systems, Lecture Notes in Electrical Engineering 614, https://doi.org/10.1007/978-981-15-0626-0_7

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Fig. 1 STUDSAT-2 (India’s first twin nano-satellite)

The main objective of STUDSAT-2 is to mitigate the issue of space debris. In this contrast, the team has developed a Drag-Sail mechanism to de-orbit the satellite within 180 days after the end-of-mission life. Camera, Inter-Satellite Link (ISL) and Beacon data relay system are the payloads. The other important objectives of the two nano-satellites, STUDSAT-2A and STUDSAT-2B are to demonstrate: • • • •

Antenna deployment Double deployment of solar panels Inter-satellite communication In-orbit separation of two satellites.

1.1 Subsystems of STUDSAT-2 The satellite system of STUDSAT-2 is shared as six subsystems, i.e. structure, attitude determination and control system (ADCS), electrical power system (EPS), command and data handling (C & DH), communication and payload as shown in Fig. 2. The team has ground station facility, Nitte Amateur Satellite Tracking Centre (NASTRAC) to track and receive signals from the satellites which are in UHF and VHF range. Fig. 2 Subsystems of STUDSAT-2

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2 On-Board Computer of Studsat-2 2.1 Overview On-board computer (OBC) is the brain of satellite which is designed to monitor and control the real-time operations of a satellite through sensors, actuators, communication modules and other components. It takes control of the satellite proximately after its launch and continues to remain in command until the end of the mission.

2.2 Reliaility of OBC Since OBC is a crucial subsystem which can define the status of operation of the entire mission, it should be well reliable. Even small malfunction may result in entire mission failure. So, reliability engineering plays a key role in the design of OBC. The design of highly reliable systems’ subjected to available resources and design constraints. Reliability of a system can be improved through either improving component reliability or employing redundancy techniques.

2.3 Redundancy Method for OBC There are several redundancy methods exist for space applications. Based on the literature review, the team has decided to adopt standby redundancy for OBC of STUDSAT-2 because of its lower failure rates in standby mode. The warm-standby technique is employed in the design of OBC of STUDSAT-2 based on power and mass constraints. The design ensures redundancy of OBC at system level, subsystem level and also at communication interface level.

2.4 Redundancy Architecture of STUDSAT-2 Figure 3 shows the OBC architecture of STUDSAT-2 where ‘Master’ will be in ‘Run’ mode and ‘Redundant’ system will be in ‘Standby’ mode. Communication between the two is achieved through controller area network (CAN) bus and interprocessor communication (IPC) between C & DH and ADCS subsystem is achieved on universal synchronous/asynchronous receive/transmit (USART) interface. (1) System Level In Fig. 4, the on-board real-time clock (RTC) in the redundant system allows it to auto-wakeup from standby mode. Upon periodic wakeup, OBC will check the

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Fig. 3 Redundancy architecture in STUDSAT-2

Fig. 4 Redundancy architecture in STUDSAT-2

activeness of the master OBC. If the master is active, redundant system will continue to stay in ‘Standby’ else it will switch to ‘Run’ mode and coup the satellite OBC operations. (2) Subsystem Level OBC of STUDSAT-2 has dual controllers, each processing C&DH, and ADCS subsystem tasks. Failure of any subsystem in the master OBC will be replaced by corresponding one in the redundant system as shown in Fig. 5.

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Fig. 5 Redundancy architecture in STUDSAT-2

Fig. 6 Redundancy architecture in STUDSAT-2

(3) Interface Level Interface failure between master-redundant OBC systems and between C & D H and ADCS subsystem is evaded by offering alternative communication line as shown in Fig. 6.

3 Results and Analysis The test set-up of OBC is shown in Fig. 7.

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Fig. 7 Test set-up

3.1 State Flow Analysis of OBC for Redundancy Architecture Figure 8 shows the MATLAB Simulink block diagram of OBC architecture in Project STUDSAT-2. Both the master and redundant system functionalities are designed and simulated by state flow technique. The whole redundancy operation is achieved at three levels. State flow logic of master OBC is shown in Fig. 9 and state flow logic of redundant OBC is shown in Fig. 10. In level 1, initially, master will write {111} to external memory and it keeps checking the memory which it has written {111}. Meanwhile, the redundant system checks the same external memory location for {111}. If the contents are matched, redundant will overwrite {000} on same memory location confirming the liveliness of the master and goes to sleep mode, whereas the master Fig. 8 MATLAB Simulink block diagram of OBC architecture

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Fig. 9 State flow logic of master OBC

Fig. 10 State flow logic of redundant OBC

continues the mission sequence execution. The flow is repeated periodically for a predefined time. In the case of occurrence of error or failure of memory, the secondlevel check will be initiated. There are two chances to cause the failure 1. Failure of OBC 2. Failure of memory. In level 2, redundant OBC sends a message (1010) to master OBC through CAN1 and master OBC acknowledges (0101). After receiving the acknowledgement, redundant OBC goes to the sleep mode. If it fails to receive an acknowledgement, level-3 check will be initiated. There are two chances of cause of failure 1. Failure of OBC 2. Failure of CAN1.

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In level 3, redundant OBC repeats the same check sequence on CAN2. If the master fails to acknowledge on this level, then failure handling methods are proceeded as discussed in Sect. 4. There are two chances for the cause of failure 1. Failure of OBC 2. Failure of CAN2.

4 Power Budget Analysis • The power consumption of OBC in STUDSAT-2 is calculated considering four systems operating in two different modes that are run and standby. • The duty cycle of master OBC in run mode will be 100% whereas for redundant OBC it will be 10%. • For 100% duty cycle orbit period of 96 min (that is 5760 s) is considered. • The power consumption of a system in master board is 3.3 V × 96.24 mA × (96 min/60) = 508.147 mWh • The total consumption of master board is 1.016 Wh • Similarly, the consumption of a system in redundant board is = 3.3 V × 47.39 mA × (9.6 min/60) = 25.021 mWh in RUN mode • In standby mode, it is 3.3 V × 4.25µA × (86.4 min/60) = 0.020 mWh • The total consumption of redundant OBC is (25.021 mWh + 0.020 mWh) × 2 = 50.082 mWh (Since both the master and redundant OBCs have two systems for C&DH and ADCS operations, the power consumption is multiplied by 2). • The total power consumption of an on-board computer in STUDSAT-2 is 1.066 Wh.

5 Conclusion The reliable design of OBC using redundancy technique increases the mission tenure of the satellite. The effect of less reliable COTS components can be effectively overcome by incorporating redundancy at system level, subsystem level and interface level. The OBC system maintains the simplicity in hardware and software design due to the choice of identical OBC as the redundant to master. The incorporated system may add an insignificant amount of cost, mass and power which very much obeys the principle of nano-satellite. But the warm-standby redundancy method increases the power efficiency of the satellite while still meeting the power budget of the mission.

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Acknowledgements The authors sincerely thank the Small Satellite Review Committee of ISRO and all the scientists of ISRO for their support. The authors are grateful to Visvesvaraya Technological University (VTU) Belagavi and the Consortium of colleges for their monetary and technical support. The authors thank the Principal and the Management of N. M. A. M. Institute of Technology, Nitte for their wholehearted support for the project. The authors are thankful to professors and core members of Team STUDSAT. The authors are thankful to the Project Director, Research Associates of Centre for Small Satellite Research (CSSR), NMIT, Bengaluru.

Bibliography 1. Arun Kumar K, Kannan T, Karthik R, Sandya S, Yaji S (2016) On-board computer redundancy for Twin Nano Satellite, STUDSAT-2, LAMSYS-2016 2. Dasiga S, Rajulu B, Iyer NR (2014) Open source RTOS implementation for on-board computer in STUDSAT-2. In: IEEE AeroSpace conference, 2014 3. Lamichhane K, Kiran M, Kannan T, Sahay D, Sandhya S (2015) Embedded RTOS implementation for Twin Nano-Satellite. In: IEEE metrology for aerospace, 2015 4. Asbury MJA, Johannessen R (1995) Single points of failure in complex aviation systems of communication navigation and surveillance 5. Yao J, Nakashima Y, Saito M, Hazama Y, Yamanaka R A flexible, self-tuning, fault tolerant functional unit array processor. In: IEEE computer society, 0272-1732/14 6. Tannous O, Xing L, Rui P, Xie M, Ng SH Redundancy allocation for series-parallel warmstandby systems. In: IEEE, 978-1-4577-0739-1/11 7. Amari SV Redundancy optimization problem with warm-standby redundancy, In: IEEE, 9781-4244-5103-6/10 8. Gohil S, Basavalingarajaiah A, Ramachandran V Redundancy management and synchronization in avionics communication products. In: IEEE, 978-1-4577-0592-2/11 9. Vinci E, Saotome O Reliability of on-board computer for ITASAT university satellite. In: IEEE, 978-1-4244-7785-2/10 10. Pillay R, Punnekkat S, Dasgupta S An improved redundancy scheme for the optimal utilization of onboard computers. In: IEEE, 978-1-4244-4859-3/09

Design Techniques of Flash ADC: Review Akshatha Kumary and Satheesh Rao

Abstract Most of the signals available in nature are analog. Since sensor operates in analog domain, data converters play an important role in transformation of these signals to digital form or vice versa in real-world applications. Various techniques are used to develop analog-to-digital converters (ADC) and these are designed in trade-off of power, speed and area. Few of the techniques are Flash type, successive approximation, sigma-delta, counter type ADC, dual-slope ADC, etc. Each type has its own advantages and limitations. For high-speed applications, Flash ADC is considered to be best candidate. Optimized comparator and decoder designs can contribute in reduction of power consumption. Since electronic devices are becoming portable, Flash ADCs are integrated with SoC configuration. Linear operation, overall size reduction and improved performance are expected features of the design to achieve the same. Keywords Flash ADC · Comparator · Thermometer code · Power dissipation and encoder

1 Introduction Flash type ADCs are popular among other ADC; it is faster than other designs. Resolution, settling time, differential nonlinearity (DNL), integral nonlinearity (INL), power dissipation and reference access are most commonly parameters to measure performance of ADC. Number of digital output produced by ADC is known as its resolution and it is represented in terms of bits. Settling time of an ADC is time required for output to reach specified value. The variation between ideal and actual output of successive DAC code is described as DNL error. The deviation of transfer A. Kumary (B) · S. Rao Department of ECE, NMAM Institute of Technology, Nitte, India e-mail: [email protected] S. Rao e-mail: [email protected] © Springer Nature Singapore Pte Ltd. 2020 S. Kalya et al. (eds.), Advances in Communication, Signal Processing, VLSI, and Embedded Systems, Lecture Notes in Electrical Engineering 614, https://doi.org/10.1007/978-981-15-0626-0_8

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function of actual output from ideal output is known as INL error. Maximum power utilized for conversion activity of ADC is defined as power dissipation. Generally, analog voltages are quantized/sampled and encoded to get digital equivalent. Sampling rate of ideal ADC is at least twice the maximum frequency of the measured signal. Input analog voltage compared with reference voltage to generate each bit of binary number output. To achieve higher accuracy, reference voltage must be constant. High-speed comparators are used to build comparator. The outputs of the comparators are a thermometric code and it is converted to binary by priority encoder. A large number of comparators are employed in parallel to generate digital signal in one cycle. Hence, count of comparators increases with resolution need to be processed. If Flash ADC designed for n number of bits, then 2n − 1 comparators are required. The number of bits present in output determines resolution of the ADC. For 4-bit, 15 comparators and for 8-bit, 255 comparators are required to design ADC. For each additional bit, number of comparators are doubled. The increase in circuit components results in high power consumption. Hence, flash converters are usually limited to 8-bits. Large number of circuit components is another drawback of Flash ADC compared SAR or other type of ADC. Flash ADCs are fastest data converters. But they are costlier than other type of ADCs due to circuit complexity and higher power consumption. Circuit can be optimized by reducing comparators used in the conversion. The reduction in comparator count reduces circuit complexity, cost as well as power consumption. Converter accuracy depends upon reference voltage ranges used to define digital output. Most ADCs require that their reference voltage is within quite a narrow range whose maximum value is less than or equal to the ADC’s supply V DD .

2 ADC Architecture This review paper provides comparison of different techniques used for design of Flash ADC. Low-power Flash ADC circuit designed by Hsia and Lee [1] uses Inverters. Two 4-bit ADCs are cascaded to build 8-bit ADC. Overall reduced input impedance causes reduced power consumption. Due to reduction in input capacitance, input impedance decreases. This will reduce power consumption. This design has been implemented with TSMC 0.35 µm technology. Total 634 transistors are available in this design with 0.9 mW power dissipation and 100 MHz operating frequency. Inverters are used to get the reference voltages. Ali et al. [2] proposed a power-efficient decoder for 2 GHz, architecture of 6bit CMOS Flash ADC. Thermal decoder which is used to get binary output using comparator output found to be a limitation for Flash ADC operation. This issue has been resolved by using parallel ADC-decoder designed using neural network logic. This is appropriate for ultra high-speed applications. Power dissipation is observed to be 19 mW. The design is implemented using Cadence 180 nm technology.

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Sung [3] presented time-interleaved Flash-SAR design which is suitable for high speed applications. Combination of Flash and SAR type ADC used to design the converter. Low-resolution Flash ADC reduces decision cycles and increases conversion speed. Behavioral model of the design is studied using Simulink model. Proposed architecture produces 6-bit output with 1.2 GS/s. Hiremath and Ren [4] proposed speed reconfigurable switching encoder. It is applicable for high-speed designs. Thermometric-code to digital-code conversion speed is a critical parameter for Flash ADC to reach ultra high-speed applications. Based on thermometric code, encoder adjusts itself and produces appropriate resolution of outputs. Nine multiplexers and ten comparators are combined to form comparator circuit of a 6-bit Flash ADC [5]. Each comparator utilizes one CMOS latch and SR latch. As per conventional method, comparator requires 63 comparators. Hence, power consumption and size of the circuit are reduced. Circuit operates same as that of conventional Flash ADC. The architecture can work with 1 GHz conversion speed and 90 nm technology used for implementation. 4-bit Flash ADC using inverter threshold comparator design [6] utilizes a small amount of power compared to conventional method. ITC is variation of thresholdmodified comparator circuit (TMCC). TMCC contains two inverters where output of first inverter will be saved in second inverter. 15 ITCs are designed in such a way that each one has different V th and overall voltage range is divided into 16 steps and only one inverter will be activated at a time. Hence, output can be encoded. Threshold voltage varied by selecting appropriate ‘W’&‘L’ values of MOSFET. Total power consumption of simulated circuit is 16.82 µm. Akiyama and Waho [7] described a novel architecture of a 6-bit 500-MHz Flash ADC. Comparator and encoder designs are optimized to operate with low power. Area occupied by the design also reduced. Encoder circuit modified with currentmode CMOS threshold logic gates instead of conventional voltage-mode encoder circuit. Transistor count can be reduced to 1/6th of conventional design. Pipelined operation of ADC is possible with combined architecture of latched comparator and encoder design. Figure of merit also reduced when compared to conventional design. Sai Kumar et al. [8] presented design of a high-speed 4-bit Flash ADC, which works with 10 GHz sampling frequency. Comparator and encoder circuits can be optimized to obtain minimum power consumption and high speed. Modified double tail comparator produces thermometric code. Analog signal converted to thermometric code by using reference voltage is provided to double tail comparator. Encoder has been designed with pseudo-CMOS logic. Basically, AND–OR–Invert (AOI) logic used to convert thermometric code to binary without any intermediate state. Hence, design contains less number of transistors. Design implemented using 180 nm technology and power consumption is found to be 0.686 mW. A modified Flash ADC circuit design is modeled by Veeramachanen et al. [9]. The design can operate with variable-power and variable-resolution. Circuit consumes power based on resolution requirement and can be used to process high-frequency signals. Peak detector included in design which can help to adjust resolution based on peak-to-peak value of the voltage. This feature is suitable for wireless applications.

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Author has noted exponential reduction in power with respect to linear change in resolution. Design implemented using 65 nm CMOS technology. Quantum voltage comparator [10] used in ADC structure where voltage comparator logic is used. This technique can be utilized in deep-submicron CMOS Flash ADC. The design operates at low voltage. The design has been verified at lower level of voltages. 6-bit and 8-bit QVC Flash ADCs are designed and both are working at high speed and consuming less power. Even noise rejection ratio also improved. Simulation performed using 0.07 µm technology. The comparative analysis of various 2-bit magnitude comparators [11] is provided and hybrid PTLI CMOS logic implemented which is found to be best among seven designs provided in the paper. Area calculation is carried out by counting the number of transistors. With CMOS based 4-bit Flash ADC uses only four comparators. HSPICE 90 nm technology is used to analyze behavior of architecture and it consumes 26 mW power. 4-bit Flash ADC designed using TIQ (Threshold inverting Quantization) technique comparator [12]. This design does not require resistive ladder, and binary code will be generated based on comparison of input signal and reference voltage. The reference voltage is produced by internal switching frequency of inverters. Thermometric code is converted to digital code using transmission gate. A TIQ-based ADC is built by integrating with pseudo-dynamic NMOS encoder [13] in design. The encoding circuit provides high sampling rate of 7 GS/s with reduced power consumption. Overall power consumption is 1.987 mW with voltage supply 1.2 V. High-speed comparator design using domino logic [14] is implemented to construct ADC. Current-comparison technique with domino logic is performed instead of conventional resistive ladder technique. 64-bit comparator is simulated with 22 nm technology, which consumed 51% less power compared to standard domino circuit. Different techniques are compared in Table 1 with relative data.

3 Conclusion Flash ADCs are the fastest data converters. But they are costlier than other type of ADCs due to circuit complexity and higher power consumption. Circuit can be optimized by reducing comparators used in the conversion. The reduction in comparator count reduces circuit complexity, cost as well as power consumption. Converter accuracy depends upon reference voltage ranges used to define digital output. Most ADCs require that their reference voltage is within quite a narrow range whose maximum value is less than or equal to the ADC’s supply V DD . Various designs are used to optimize Flash ADC parameters. Comparators and encoders are essential parts of ADC which can be used to optimize the design. Each design has either improved speed or reduced power and size. However, they normally consume more power than other ADC. High-speed comparators are cascaded to design Flash ADCs. Thermometric code is produced as output of the comparator. Priority encoder converts it into binary number or digital. Flash ADC yields output in one cycle. But still the architecture can do analog-to-digital conversion at higher

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Table 1 Comparison of various Flash ADC structures Flash ADC design

Design technique with technology used for simulation

Improved feature of the design

8-bit [1] with voltage supply 3.3 V

CMOS inverter-based comparator using 0.35 µm technology (Cadence tool)

Power dissipation: 0.9 mW with speed 100 MHz

6-bit [2] with voltage supply ±0.9 V

Neural network based parallel decoder using 0.18 µm technology (Cadence tool)

Power dissipation: 18.9 mW with sampling rate >2 GHz Area: 25,000 µm2

6-bit [3]

Time interleaving technique using ADC Simulink

Conversion speed: 1.2 GHz

4-bit [4] with voltage supply 1.2 V

Reconfigurable encoder using 90 nm technology (Cadence tool)

Power dissipation: 46 µW

6-bit [5]

Low-power CMOS technique with 90 nm technology (micro wind tool)

Power dissipation: 2.38 mW

4-bit [6] with voltage supply 1.1 V

Inverter threshold comparator with 45 nm technology (Cadence tool)

Power dissipation: 16.82 µW, operating frequency: 100 kHz

6-bit [7]

Encoder using current-mode threshold logic gates with 0.35 µm technology (Cadence tool)

Power dissipation: 113 mW, operating frequency: 500 MHz

4-bit [8] with voltage supply 1.8 V

Encoder design using pseudo-dynamic CMOS logic with 180 nm technology (Cadence tool)

Power dissipation: 0.686 mW Operating frequency: 10 GHz

4-bit/5-bit/6-bit [9] with voltage supply 1.2 V

Variable-resolution based on input peak-to peak-voltage with 65 nm technology (Cadence tool)

Average power consumption: 12 mW Speed: 800 MS/s

6-bit and 8-bit [10] with voltage supply 0.7 V

Comparator with QVC technique with 0.07 µm technology (SPICE model)

Sample rate 2.7 GS/s

2-bit comparator [11] with voltage supply 0.6–1.2 V

Comparator designed using hybrid PTLI CMOS technique (HSPICE 90 nm technology)

Low power consumption

4-bit with operating voltage 1.2 V [15]

Encoder designed using multiplexer technique (90 nm technology using HSPICE)

Power dissipation 23 mW and sampling rate 2 GS/S

4-bit [12] with operating voltage 0.8 V

Comparator designed using TIQ technique (using Cadence)

Power dissipation 14.08 µW and delay 200 µs (continued)

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Table 1 (continued) Flash ADC design

Design technique with technology used for simulation

Improved feature of the design

4-bit [13]

Encoder designed using pseudo dynamic technique using Cadence 90 nm technology

Speed 7 GS/s

64-bit comparator [14]

Comparator designed using current comparison-based domino logic (using 22 nm technology in Cadence)

Reduces area and power consumption

4-bit with 1.8 V operating voltage [16]

Comparator designed using low offset dynamic technique with 180 nm Cadence technology

Power dissipation 1.5 mW

speed with medium accuracy. Flash ADCs work based on an analog reference voltage. Output generated by comparing input analog signal with reference voltage. Since accuracy of the output is directly affected by the reference, bits produced by output defines resolution of Flash ADC. Higher number of bits can reduce approximation of output. In this paper, various Flash ADC designs are compared and presented in table. Each design can achieve a parameter by comprising with remaining parameter.

References 1. Hsia SC, Lee WC (2005) A very low-power Flash A/D converter based on CMOS inverter circuit. In: Proceedings of the 9th international database engineering & application symposium (IDEAS’05). IEEE, pp 107–110 2. Ali SM, Raut R, Sawan M (2005) A power efficient decoder for 2 GHz, 6-bit CMOS FlashADC architecture. In: Proceedings of the 9th international database engineering & application symposium (IDEAS’05). IEEE, pp 123–126 3. Sung BRS et al (2009) A time-interleaved flash-SAR architecture for high speed A/D conversion. IEEE, pp 984–987 4. Hiremath V, Ren S (2011) A novel ultra high speed reconfigurable switching encoder for Flash ADC. In: IEEE Aerospace and electronics conference (NAECON), pp 320–323 5. Reddy MS, Rahaman ST (2013) An effective 6-bit Flash ADC using low power CMOS technology. In: 15th international conference on advanced computing technologies (ICACT). IEEE, pp 1–4. 6. Devadiga R, Rao S (2018) Design of 4-bit Flash ADC using inverter threshold comparator in 45 nm technology. In: 2018 international conference on inventive research in computing applications (ICIRCA). Coimbatore, pp 978–982 7. Akiyama S, Waho T (2006) A 6-bit low-power compact Flash ADC using current-mode threshold logic gates. In: 2006 IEEE international symposium on circuits and systems. Island of Kos, pp 3938–3941 8. Sai Kumar K et al (2018) A high speed flash analog to digital converter. In: Proceedings of the second international conference on I-SMACI. IEEE, pp 283–288 9. Veeramachanen S, Kumar AM, Tummala V, Srinivas MB (2009) Design of a low power, variable-resolution Flash ADC. In: 2009 22nd international conference on VLSI design. New Delhi, pp 117–122

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10. Yoo J, Choi K, Ghaznavi J (2003) Quantum voltage comparator for 0.07 µm CMOS flash A/D converters. In: IEEE computer society annual symposium on VLSI, pp 281–281 11. Sharma G, Arora H, Chawla J, Ramzai J (2015) Comparative analysis of 2-bit magnitude comparator using various high performance techniques. In: IEEE communication and signal processing, pp 0079–0083 12. Sireesha R, Kumar A (2015) Design of low power 0.8 V Flash ADC using TIQ in 90 nm Technology. In: International conference on smart technology and management, pp 406–410 13. Nazir L, Khurshid B, Mir RN (2015) A 7 GS/s, 1.2 V. Pseudo logic encoder based Flash ADC using TIQ technique. In: Annual IEEE India conference, pp 1–6 14. Manikandan A, Ajayan J, Kavin Arasan C (2015) High speed low power 64-bit comparator designed using current comparison based domino logic. In: International conference on electronics and communication systems, pp 156–161 15. Megha R, Pradeepkumar KA (2014) Implementation of low power Flash ADC by reducing comparators. In: International conference on communication and signal processing, pp 443– 447 16. Biswas S, Das JK, Prasad R (2015) Design and implementation of 4 bit Flash ADC using low power low offset dynamic comparator. Electrical, electronics, signals, communication and optimization, pp 1–6

Pedal Effects Modeling for Stringed Instruments by Employing Schemes of DSP in Real Time for Vocals and Music D’Souza Dony Armstrong, Shastrimath V. Veena Devi and V. N. Ganesh

Abstract In this paper, it is proposed to put forward musical sound effects processing system based on virtual analog modeling and digital signal processing techniques. The effects used most commonly by musicians such as, fuzz, phaser, distortion reverb, echo, flanger tremolo, vibrato, etc., are generated by analog circuits. Here, we propose to generate these effects by using the concept of digital signal processing filters. The proposed system works on wave files and also on the buffered audio which is fed from the microphone input of computer. The proposed system is built around by using the codes in Scilab/Octave and the sequences of effects are sequenced depending on the musicians/artists choice. The various concepts of filtering in digital signal processing are used. The results obtained are compared with the commercially available systems. Keywords Fuzz · Distortion · Flanger · Vibrato · Reverb

1 Introduction The use of different audio effects in musical instruments nowadays are becoming more and more popular and at the same time, expensive and are not easily accessible to everyone. The sophisticated music processing boxes seen in the live performances, studio etc., are in much demand. Hence, in order to have the same effects for an amateur musician or artist, the feel of all the processing effects enhance his/her creativity by having the feel and to know the various effects in which context, it can D. Dony Armstrong (B) · V. N. Ganesh ECE Department, MITE, Mijar, India e-mail: [email protected] V. N. Ganesh e-mail: [email protected] S. V. Veena Devi ECE Department, NMAMIT, Nitte, India e-mail: [email protected] © Springer Nature Singapore Pte Ltd. 2020 S. Kalya et al. (eds.), Advances in Communication, Signal Processing, VLSI, and Embedded Systems, Lecture Notes in Electrical Engineering 614, https://doi.org/10.1007/978-981-15-0626-0_9

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be used and for which instrument it suits best at a very cost-effective way. It will be a boon for the budding musician or studio artist. In the recent times, music has been extensively used in the field of theater, films, and concerts to produce and make the feel of the environment more realistic. Audio extraction of required information from audio files, microphones, and sensors has become an important aspect in the field of healthcare, music, forensics, and entertainment industry [1, 2]. The basic musical sound processing of the sound produced by the musical instrument are dated way back to early nineteenth century where the amplifiers were designed and some circuits incorporated within the system, stated in reference [3]. The mathematical modeling of the audio signals and effects have been in the main frame since the early nineteenth century by having different sounds generated for the enhancements of the feel of audience by employing electronics circuits for achieving the different audio effects [4] for the instruments such as guitar, etc. The virtual modeling of the effects for the musical instrument was achieved by using signal processing tools like MATLAB, Octave, and Scilab to generate various effects like chorus, flanger, delay, echo, distortion, fuzz, tremolo, etc. [5]. The another type of modeling techniques were reviewed from [6] where in author took into account the key properties of music signals, such as the presence of multiple, coordinated sources, the existence of structure at multiple temporal levels, and the peculiar kinds of information being carried [6] which can be used to extract from the musical score. By using the harmonic model for obtaining a proper model, fundamental frequencies and phases were considered [7]. The system performance was limited by ignoring voiced and unvoiced parts and output were made independent of the voiced estimator. However, the author did not take into consideration the noises and filtering required. A flexible framework was proposed in order to extract the audio effects used in the order in the generation of audio by observing the spectral contents of the signals [8] and different window sizes were considered to identify the wave by comparing different background models for the sources [4]. Experimental evaluations have also shown that the framework could achieve satisfying results depending on the sources being under test both on key audio effect detection and semantic inference of the auditory context [8]. Simple low-frequency oscillators were used to generate some modulation to the sounds as in the reference [9] known to produce effects such as tremolo effect, flanger effect. From reference [10], the circuits may be seen as modeling of the various effects of the sound produced by musical instrument. The state-variable filters with variable cut-off frequencies and band are used in order to produce the wah-wah effect. Similarly by using a set of comb filters with variable delay co-efficient, the chorus, [11] delay, and flangers are obtained. Here, we consider the properties of human ear for perception beyond 10 and 25 ms repetition intervals [6]. In order to have more versatility in the system, the input may be from a microphone or wave file [12] for in order to add effects after the file has been recorded in order to hear it in different combinations in music composition scenarios.

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Fig. 1 Block diagram of proposed system

2 System Overview The block diagram depicting the overview of the proposed system is shown in Fig. 1. The musical instrument with a transducer to pick up the sound signals may be capacitive or inductive based on the requirements. Buffers are used in order to store the [13] values of analog-to-digital converter which have to be stored for brief amount of time while the processor is processing the data of the a fixed no. of bits. The processor output is then given to a buffer and digital-to-analog converter in order to overcome the conversion and processing time limitations [5]. By proper impedance matching, the signals are then given to the amplifiers.

3 Methodology The methodology involves basically five steps: 1. 2. 3. 4. 5. 6.

Data acquisition. Data storage. Selection of the desired effects. Data processing by suitable processor. Provision to store the processed data. Output the data in real time.

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3.1 Data Acquisition The data acquisition step is the step in which the data is to be acquired and then converted to digital data form, which could be done by using [14] any conventional analog-to-digital converter. For the need of faster conversion, flash ADC’s may be preferred. By using the commands, r = audiorecorder(8000, 16, 2);

(1)

recordblocking(r, 0.025);

(2)

The data is sampled at 8 kHz, 16-bit data, and 2-channel audio and recorder is blocked and then once again recorded after the specified time for the data to be stored as a wave file [15]. This wave file is the data and then the operations are performed on this data within the time before which the data recording starts again [16]. Thus, having a buffering of sometime provided by using the play and pause instructions.

3.2 Data Storage The data is stored in the form of matrices in the computer memory and is stored as an array of two rows or two columns [13]. The data is accessed by accessing the required elements of the array or matrix, which is advantages as the required elements only can be selected and the right or left channels can be selected or operated upon.

3.3 Selection of the Desired Effects The desired effects are selected from the choice menu option which chains or cascades the desired order of effects as shown in flow chart in Fig. 2. The various effects built on analog systems/circuits are designed or modeled into as expressions with some variables and passing those values in a window or frame to be processed and give out the desired effects [5]. The distortion and other effects are modeled by considering soft, moderate, and hard clipping.

3.4 Data Processing by Suitable Processor Since the audio data which is to be processed is a continuously incoming data stream, it has to be processed at very high-speed rate. The execution time must be very low

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Fig. 2 Effects chain selector

and the instructions must be very less. The processor may be used with the capabilities of signal processing such as the DNX, Blackfin [16] series which are the processors used in commercially available audio processing and synthesizer equipments.

3.5 Provision to Store the Processed Data 1. The data after being processed will be requiring a small amount of memory to store the processed data. Virtual memory has to be kept maximum [17, 1]. 2. In case of the looping stage, the output may be required to be stored in a RAM. So that it required to reproduce the same sound over and over again in a loop [12, 6].

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3.6 Output the Data in Real Time The Processed data is then written as wave file by using the Octave command known as wavwrite. It’s written as, wavwrite(y, Fs, bits)

(3)

where y the proceeds signal matrix or vector Fs the sampling frequency bits number of bits maybe 8/16/32 bits. The instructions SOUND(Y, FS) sends the signal in vector Y (with sample frequency Fs) out to the speaker on platforms that support sound. Values in Y are assumed to be in the range −1.0 ≤ y ≤ 1.0. Values outside that range are clipped. Stereo sounds are played, on platforms that support it, when Y is an N-by-2 matrix. SOUND(Y ) plays the sound at the default sample rate of 8192 Hz. SOUND(Y, FS, BITS) plays the sound using BITS bits/sample if possible. Most platforms support BITS = 8 or 16 [5]. Soundsc(y, Fs) does the same as Sound(y, Fs) except that the data is scaled so that the sound is played as loud as possible without clipping [7, 18]. The mean of the dynamic range of the data is set to zero after the normalization [19]. The complete system working flow flowchart is depicted in Good Fig. 3. After initializing the system and once the program is loaded or deployed with deployment file, if effects have to be added to the existing wave file or to real-time input from mic has to be selected and the order of effects from the effects chain are taken and written into and the output obtained may be written as a wave file or given directly as an output.

4 Results and Conclusions The tests are conducted for the input signals from three musical instruments: 1-Violin, 2-Guitar, and 3-Bass Guitar. The program is tested for the clips of 1 and 5 s for all the three instruments and compared with the commercially available Digitech RP 90 guitar processor. The program execution time is got by using the tic and toc command in MATLAB for a 1-s clip and 5-s clip the results obtained are tabulated in Table 1. The waveform of input signal from a guitar play of one second is shown in Fig. 4. The output is heard and the responses are depicted in the figures given below for the effects of wah-wah, fuzz, tremolo, delay, chorus, flanger of and also with outputs obtained from the commercially available Digitech RP90. The frequency spectrum of the one-second sound clip played from guitar is shown in Fig. 5.

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Fig: 3: Effects chain selector Table 1 Comparison of execution of different sound waves

Effect

1-s clip

5-s clip

Pre amp

0.03

0.3

Fuzz

0.0383

0.781

Distortion

0.04

0.7923

Overdrive

0.0415

0.8

Wah-wah

0.0821

1.9

Phaser

0.055

0.9

Tremelo

0.27

1.352

Vibrato

0.039

0.881

Delay

0.05

0.86

Echo

0.06

0.95

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Fig. 4 Input signal waveform for a one-sec guitar clip

The wave of fuzz effect output obtained is shown in Fig. 6. The frequency spectrum of the output of fuzz effect is shown in Fig. 7. The output of the wah-wah effect by using the stone-second guitar clip sound is shown in Fig. 8. The frequency spectrum of the output of wah-wah unit is shown in Fig. 9. The tremelo unit output is shown with the comparison of guitar one-second clip and its effects obtained clip is shown in Fig. 10. The sweeping low-frequency wave for tremelo effect is shown in Fig. 11. The frequency spectrum of the tremelo unit is shown in Fig. 12. The output waveform of chorus effect with the delay chain set to 10 ms is shown in Fig. 13. The frequency response of the chorus effect is shown in Fig. 14. The output of the Eeho unit with delay set to 50 ms is shown in Fig. 15. The frequency spectrum of the output of echo effect is shown in Fig. 16. The expander output waveform with input and output is shown in Fig. 17. Frequency spectrum of the output through expander is shown Fig. 18. As seen by the waveforms, the results obtained are satisfactory within the given constraints. By comparing the results obtained and listening to the audio wave file obtained, it is seen that the clarity is better in proposed system and the other effects like

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Fig. 5 FFT of the input one-second guitar clip

Fig. 6 Output of fuzz unit

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Fig. 7 FFT of the fuzz signal

Fig. 8 Output of wah-wah unit

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Fig. 9 FFT of the wah-wah unit signal

Fig. 10 Output of the tremolo unit signal

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Fig. 11 Triangular wave of the LFO

Fig. 12 FFT of the output of the tremolo unit

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Fig. 13 Output after passing through chorus

Fig. 14 Output after passing through chorus

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Fig. 15 Output after passing through echo

Fig. 16 FFT of the output after passing through echo

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Fig. 17 Output after passing through expander of proposed system and Digitech RP90

Fig. 18 Output after passing through expander

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wah-wah, fuzz, echo, delay, reverberation, flanger, chorus, expander, and compressor have a very good frequency response, i.e. the output of the proposed system does not produce unwanted frequencies.

References 1. Hsu C-L, Wang D, Roger Jang J-S, Hu K (2012) A tandem algorithm for singing pitch extraction and voice separation from music accompaniment. IEEE Trans Audio, Speech, Lang Process 20(5), July 2012 2. Moffat D, Ronan D, Reiss JD (2015) An evaluation of audio feature extraction toolboxes. In: Proceedings of the 18th international conference on digital audio effects (DAFx-15), Trondheim, Norway, November 30–December 3, 2015 3. Zölzer U (ed) (2002) DAFX—Digital audio effects. Wiley, New York, NY, USA 4. Cohen I, Hélie T (2010) Real-time simulation of a guitar power amplifier. In: 13th international conference on digital audio effects, DAFx 2010 proceedings 5. D’Souza DA, Shastrimath VVD (2019) Modelling of audio effects for vocal and music synthesis in real time. Presented at ICCMC -2019 at Erode 6. Poepel C, Dannenberg RB (2005) Audio signal driven sound synthesis. In: Proceedings of the international computer music conference, Barcelona, Spain, Sept 2005, pp 391–394 7. Ye AJ, Kobayashi T, Murakawa M, Higuchi T (2014) Robust acoustic feature extraction for sound classification based on noise reduction. In: IEEE international conference on acoustic, speech and signal processing (ICASSP) 2014 8. Cai R, Lu L, Hanjalic A, Zhang H-J, Cai L-H (2006) A flexible framework for key audio effects detection and auditory context inference. IEEE Trans Audio, Speech, Lang Process 14(3), May 2006 9. Pakarinen J, Penttinen H, Välimäki V et al (2009) Review of sound synthesis and effects processing for interactive mobile applications. Report 8, Department of Signal Processing and Acoustics, Helsinki University of Technology 10. Gang R, Bocko G, Lundberg J, Rossener S (2011) A real-time signal processing framework of musical expressive feature extraction using MATLAB. In: 12th international society for music information retrieval conference (ISMIR 2011) 11. Pakarinen J, Valimaki V, Fontana F, Lazzarani V, Abel JS (2011) Recent advances in real-time musical effects, synthesis, and virtual analog models. EURASIP J Adv Signal Process 2011. Article ID 940784. Sound and music technology research group, National university of Ireland Maynooth, Ireland 12. Välimäki V, Pakarinen J, Erkut C, Karjalainen M (2006) Discrete time modelling of musical instruments. Rep Prog Phys 69(1):1–78 13. D’Souza DA, Lasrado S, Ganesh VN (2012) Virtual analog and digital effects model for vocal and musical sound synthesis. ICECE-2012 conference, vol 1. IRNET, Bangalore, pp 247–251 14. Kim H, Kim T, Park J (2012) A real time singing voice removal system using DSP and multichannel audio interface. Int J Multim Ubiquitous Eng 7(2), April 2012 15. Müller RM, Ellis DPW, Klapuri A, Richard G, Sagayama S (2011) Introduction to the special issue on music signal processing. IEEE J Sel Topics Signal Process 5(6), October 2011 16. Buffa M, Lebrun J (2018) Real-time emulation of a Marshall JCM 800 guitar tube amplifier, audio FX pedals, in a virtual pedal board. In: Proceedings April 2018, pp 179–182 17. Lazzarini V, Timoney J, Lysaght T (2008) The generation of natural-synthetic spectra by means of adaptive frequency modulation. Comput Music J 32(2):9–22

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18. Degottex G, Erro D (2014) A uniform phase representation for the harmonic model in speech synthesis applications. EURASIP J Audio, Speech, Music Process 2014:38 19. Cooper CM, Abel JS Digital simulation of brassiness and amplitude-dependent propagation speed in wind Instruments. In: Proceedings of the international conference on digital audio effects, Graz, Austria, Sept 2010

Design and Development of Piezo-Stepping Voltage Drive for Piezoelectric Stack Actuator Nutana Shetty, K. Sushith and Muralidhara

Abstract Voltage and frequency control is the most common requirement to drive the piezoelectric stack actuators. Because of inefficient amplifiers and nonlinear behavior of piezoelectric stack actuator, control over the frequency and voltage of piezoelectric actuator is a difficult task. In this paper, a design of high-frequency drive circuit for piezoelectric stack actuator is presented. The drive circuit contains a high-frequency power electronic device to control the piezoelectric stack actuators with different frequency and constant pulse voltage. Output frequency response for multiple piezoelectric stack actuators is determined using MATLAB. Simulation is carried out to analyze drive circuit with electrical equivalent model of piezoelectric stack actuator. Experimental results are presented for single piezoelectric stack actuator driven at 100 V V dd and frequency 100 and 50 Hz. Keywords Piezoelectric stack actuator · Piezo-stepping voltage driver · Frequency response · Simulation

1 Introduction Piezoelectric stack actuator is an electrically controlled device. In a piezoelectric stack actuator, displacement is generated in response to the voltage applied to the actuator. The piezoelectric stack actuators have characteristics such as fast response, high stiffness, fine resolution and low steady-state power consumption. Hence, the piezoelectric stack actuators are gaining importance in high-precision applications such as positioning, vibration control systems [1], hydraulic pumping applications N. Shetty (B) ECE Department, NMAM Institute of Technology, Nitte, Karnataka, India e-mail: [email protected] K. Sushith · Muralidhara Department of Mechanical Engineering, NMAM Institute of Technology, Nitte, Karnataka, India e-mail: [email protected] Muralidhara e-mail: [email protected] © Springer Nature Singapore Pte Ltd. 2020 S. Kalya et al. (eds.), Advances in Communication, Signal Processing, VLSI, and Embedded Systems, Lecture Notes in Electrical Engineering 614, https://doi.org/10.1007/978-981-15-0626-0_10

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[2, 3] and micro-EDM applications [4, 5]. Piezoelectric stack actuator is electrically considered as a capacitor and displacement is proportional to applied voltage to the actuator [6]. The piezoelectric stack actuator is generally driven with op-amp-based drive circuit. The op-amp-based drive circuit is not efficient for high-power applications [7, 8], But it is good choice for low-power applications. For high-power applications of piezoelectric stack actuator, switch-mode-controlled drive circuit is efficient. The switch-mode power electronics-based drive circuit for driving piezoelectric stack actuators have become more popular [9] because of its high efficiency, reduced weight and size. In this work, a piezo-stepping voltage drive for piezoelectric stack actuator is designed and developed using switch-mode power electronics devices. This voltage drive can be used to drive the piezoelectric stack actuator using high-frequency pulse voltage to generate pulsed displacement. This drive is specially designed to control the lock–release actuator in piezo-stepping actuator which is described in the upcoming section. In this paper design of high-frequency piezo-stepping voltage driver for MLA10 × 10 × 20 piezoelectric stack actuator is discussed. The piezo-stepping actuator is described in Sect. 2. Section 3 deals with the electrical modeling of piezoelectric stack actuator using Van Dyke model to examine the performance of piezoelectric stack actuator drive circuit. The piezo-stepping voltage driver unit design is explained in Sect. 4. The frequency response of the output stage of piezo-stepping voltage driver is shown in Sect. 5. The simulation and experimental results are discussed in Sects. 6 and 7.

2 Description of Piezo-Stepping Actuator Piezoelectric stack actuator is used in piezo-stepping actuator as a lock–release and push–pull actuators. Figure 1 shows the design of a piezo-stepping actuator. The piezo-stepping actuator can be used for different micro-positioning applications. The design consists of two push–pull actuators and two lock–release actuators. Each of the push–pull and lock–release actuator comprises of a parallel prestressed structure

PushPull Actuator 2

Slider Push-Pull Actuator 1 Lock Release actuator 1

Fig. 1 Design of piezo-stepping actuator

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assembled with a single piezoelectric stack actuator. Push–pull actuators are used to displace the slider forward and backward with micrometer accuracy. The lock–release actuators are used to hold or release the slider. Hence, a fixed micrometer range of displacement is required by the lock–release actuator to hold or release the slider in the piezo-stepping actuator. For the forward motion of the slider, lock–release actuator 2 and push–pull actuator 2 are activated depending on control algorithm of stepping actuator. Meanwhile, for the backward motion of the slider, lock–release actuator 1 and push–pull actuator 1 will be replaced in control algorithm of stepping actuator. The developed piezo-stepping voltage drive can be used for lock–release actuator in piezo-stepping actuator. Because the voltage drive circuit is only capable to generate a fixed voltage amplitude. Hence, this cannot be applicable for push–pull actuator, which requires various voltage amplitude.

3 Electrical Behavior of Piezoelectric Actuator To design a drive circuit for a piezoelectric stack actuator, the electrical modeling of the piezoelectric actuator is mandatory. The behavior of piezoelectric stack actuator in an electrical domain is equivalent to a capacitor with nonlinear capacitance. Van Dyke model is deriving the electrical and mathematical model of the piezoelectric actuator [10, 11], this model is used for analyzing the behavior of piezoelectric stack actuator in simulation. The Van Dyke model of piezoelectric stack actuator is shown in Fig. 2. The nonlinear capacitance C p which represents the electrical branch of actuator is connected parallel with series RLC which represents motional branch of piezoelectric stack actuator includes mechanical damping, effective mass, and stiffness of piezoelectric stack actuator. The parameters of motional branch are obtained from the electromechanical modeling [12]. Table 1 shows the motional branch parameters of MLA10 × 10 × 20 piezoelectric stack actuator. Fig. 2 Van Dyke model of piezoelectric stack actuator

Table 1 Motional branch parameters of MLA10 × 10 × 20

Parameters

Value

Lm

1.98 µH

Cm

3.5 µF

Rm

2

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4 Piezo-Stepping Voltage Driver Unit The piezo-stepping voltage driver unit has microcontroller, IR2110 gate driver and MOSFET-based half-bridge converter. The computer focus command-pulsed voltage signal is applied to the microcontroller. The microcontroller unit generates two digital outputs and frequency of these two outputs depends on input frequency of pulsed voltage signal. The circuit diagram of piezo-stepping voltage driver is shown in Fig. 3. The output of the microcontroller is about 5 V, this voltage level is not able to turn ON the nchannel MOSFETs (Q1 and Q2). To turn ON MOSFET, its gate voltage should be 10 V higher than the drain voltage. The solution is to use a voltage level shifter to raise the microcontroller output signal voltage from 5 to 10 V. IR2100 utilizes a bootstrapping capacitor C to maintain a voltage difference of approximately 10 V above the drain to source voltage at upper side of MOSFET Q1. There are so many MOSFET drivers available in the market to achieve the same objective, but for this design, a two-output IR2110 is used. The IR2110 have High and Low side drive device, exceeds all requirements for driving the MOSFETs in the half-bridge and is capable of up to 500 V at a current rating of 2A at fast switching speeds. Operation of IR2110 device is controlled through stepping signals generated from Arduino microcontroller. The outputs signal from Arduino microcontroller is be fed to the HIN and LIN pins of IR2110 simultaneously. The output pins HO and LO of IR2110 are connected to gate of MOSFETs Q1 and Q2, respectively. When HO

Fig. 3 Circuit diagram of piezo-stepping voltage driver

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is high, MOSFET Q1 is turn ON and piezoelectric stack actuator is charging to maximum voltage level of VDD, at this point, LO pin of IR2110 is Low, hence MOSFET Q2 is turn OFF. When HO pin of IR2110 is low, MOSFET Q1 is turn OFF, at this point LO pin of IR2110 is high, hence MOSFET Q2 is turn ON. The stored charge in piezoelectric stack actuator will discharge through resistor R3 .

5 Frequency Response for Output Stage of Piezo-Stepping Voltage Driver The frequency response of output stage of piezo-stepping voltage drive is necessary to find out the maximum operating frequency the piezoelectric stack actuators with series resistance R3 . Bode plot for output stage of piezo-stepping voltage driver is obtained using MATLAB software. The output stage of piezo-stepping voltage driver is same as lowpass RC filter and transfer function is 1 Vout  = Vin R3 ∗ C p S + 1

(1)

where, C p is the capacitance of piezo stack actuator R3 is the discharging resistance. Figure 4 shows Bode plot of output stage of piezo-stepping voltage driver using single MLA10 × 10 × 20 piezoelectric stack actuator with series 20  resistor. The capacitance of single piezoelectric stack actuator is 4.4 µF. Hence, maximum cut-off frequency obtained is 11.3 K rad/s and phase angle is 45°. Figure 5 shows Bode plot output stage of piezo-stepping voltage driver using of two parallel MLA10 × 10 × 20 piezoelectric stack actuators with series 20  resistor. The capacitance of the two parallel MLA10 × 10 × 20 piezoelectric stack actuators is 8.8 µF. Hence, maximum cut-off frequency obtained is 5.67 K rad/s. The obtained cut-off frequency for output Fig. 4 Bode plot for output stage of piezo-stepping voltage driver using single MLA10 × 10 × 20 piezoelectric stack actuator

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Fig. 5 Frequency response for output stage of piezo-stepping voltage driver using two MLA10 × 10 × 20 piezoelectric stack actuator

Table 2 Frequency response for output stage of piezo-stepping voltage driver

Number of MLA10 × 10 × 20 piezoelectric stack actuators

Cut-off frequency F c in rad/s

1

11,363

2

5681

3

3787

4

2840

5

2272

6

1893

stage of piezo-stepping drive with single and multi piezoelectric stack actuators given in Table 2.

6 Simulation Results The performance of the piezo-stepping voltage driver model has been verified by using MATLAB/Simulink. Figure 6 shows Simulink model of piezo-stepping voltage driver with electrical model of MLA10 × 10 × 20 piezoelectric stack actuator. This Simulink model is designed by using half-bridge converter topology. In this circuit, pulse generator 1 and pulse generator 2 are used to drive the MOSFET1 and MOSFET2, respectively. MATLAB simulation of piezo-stepping voltage drive is carried out for two different input frequencies of 50 and 100 Hz. Figures 7 and 8 shows simulation results of applied voltage, load current versus time for MLA10 × 10 × 20 piezoelectric stack actuator at frequency of 100 and 50 Hz, respectively. The total current drawn by MLA10 × 10 × 20 is 620 mA for a frequency 100 Hz and 300 mA for an input frequency of 50 Hz at 100 V V dd .

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Fig. 6 Simulink model of piezo-stepping voltage driver with electrical model of MLA10 × 10 × 20 piezoelectric stack actuator

Fig. 7 Simulation results of current-carrying MLA10 × 10 × 20 piezoelectric stack actuator with pulse input voltage of 100 V V dd at 100 Hz frequency

7 Experimental Results Figure 9 shows block diagram of experimental setup for controlling MLA10 × 10 × 20 piezoelectric stack actuator using piezo-stepping voltage driver. The NI-PXIe 6363 is a data acquisition system which is used to acquire and generate digital and analog signals through LabVIEW interface. The pulse voltage signal is generated from NI-PXIe 6363 DAQ through LabVIEW software which is given to the piezostepping voltage driver. The Piezo-stepping voltage drive is used drive the MLA10 × 10 × 20 piezo stack actuator at fixed output voltage and variable frequency. The operating frequency of MLA10 × 10 × 20 piezoelectric stack actuator is same as pulse voltage signal frequency which is generated from LabVIEW. OptoNCDT

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Fig. 8 Simulation results of current-carrying MLA10 × 10 × 20 piezoelectric stack actuator with pulse input voltage of 100 V V dd at 50 Hz frequency

Fig. 9 Block diagram of experimental set up for controlling MLA10 × 10 × 20 piezoelectric stack actuator using piezo-stepping voltage driver

2220 laser displacement sensor measures the displacement of MLA10 × 10 × 20 piezoelectric stack actuator. The sensor output is connected back to the NI-PXIe 6363 system to acquire the data and displayed using LabVIEW software. The general photographic view of the prototype of piezo-stepping voltage driver is shown in Fig. 10. Figure 11 shows plot of pulse input voltage, experimental displacement versus time of MLA10 × 10 × 20 piezoelectric stack actuator is done at 100 Hz frequency by applying 100 V pulse voltage. The maximum displacement obtained is 12 µm. Figure 12 shows plot of pulse input voltage, load current versus time for MLA10 ×

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Fig. 10 View of developed piezo-stepping voltage driver

MOSFETs

Arduino uno

R2

IR2110

MLA10x10x20 Piezo Stack

Fig. 11 Plot of displacement of MLA10 × 10 × 20 piezoelectric stack actuator with pulse input voltage of 100 V at 100 Hz frequency

10 × 20 piezoelectric stack actuator at 100 Hz frequency. The total current carrying for MLA10 × 10 × 20 is 640 mA and maximum current at transient condition is 5A. Figure 13 shows plot of input pulse voltage, experimental displacement versus time of MLA10 × 10 × 20 piezoelectric actuator stack is done at 50 Hz frequency by applying pulse input voltage 100 V. The maximum displacement obtained is 12 µm. Figure 14 shows plot of input voltage, load current versus time for MLA10 × 10 × 20 piezoelectric stack actuator at 100 Hz frequency. The total current drawn for MLA10 × 10 × 20 is 360 mA and maximum current at transient condition is 4A.

124 Fig. 12 Plot of current-carrying MLA10 × 10 × 20 piezoelectric stack actuator with pulse input voltage of 100 V at 100 Hz frequency

Fig. 13 Plot of displacement of MLA10 × 10 × 20 piezoelectric stack actuator with pulse input voltage of 100 V at 50 Hz frequency

Fig. 14 Plot of current-carrying MLA10 × 10 × 20 piezoelectric stack actuator with pulse input voltage of 100V at 50 Hz frequency

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8 Conclusion Piezo-stepping voltage driver is a device that is used to drive lock–release actuators in piezo-stepping actuator at different frequency with fixed pulse input voltage. In this work, piezo-stepping voltage driver is used to operate piezo stack actuators at higher range frequency from 50 to 100 Hz. The simulation of piezo-stepping voltage drive circuit is carried out in MATLAB/Simulink with different frequency. The Van Dyke model is used to represent the MLA10 × 10 × 20 piezoelectric stack actuator in simulation. Frequency response for output stage of piezo-stepping voltage driver is obtained using multiple MLA10 × 10 × 20 stack actuators with series resistive load using MATLAB. Experimental results show that the current drawn by the MLA10 × 10 × 20 piezoelectric stack actuator at 100 and 50 Hz frequency is 640 mA and 330 mA, respectively. Maximum displacement obtained from the MLA10 × 10 × 20 is 12 µm for the applied voltage of 100 V V dd at 50 and 100 Hz frequency. Hence, this piezo-stepping voltage drive is capable to drive a piezoelectric stack actuator based lock–release actuator in piezo-stepping actuator.

References 1. Hwang JY, Kim MK, Lee SH, Kang K, Cho YJ (2007) A study on driving waveform of a piezoelectric inkjet print head. In: International symposium on optomechatronic technologies. international society for optics and photonics, pp 67 170 T-67 170T 2. Nayak S, Rao M, Rao R (2016) Design, analysis and testing of quadratic arm flexurally amplified piezoactuator. IJIRSET 5(Special Issue 9):844–859 3. Nayak S, Rao M, Rao R (2016) Design and simulation of high pressure piezohydraulic pump with active valves. In: 2016 IEEE 6th international conference on electrical, electronics, and optimization techniques (ICEEOT), pp 1608–1613 4. Venugopal TR, Rao M, Rao R (2014) Development of micro-EDM incorporating in-situ measurement system. In: International conference on advances in manufacturing and materials engineering (AMME), Procedia materials science, vol 5, pp 1897–1905 5. Prabhu P, Venugopal TR, Rao M, Rao R (2016) Design fabrication and testing of tool feeding system for in-situ tool grinding in micro EDM. IJIRSET 5(Special Issue 9):855–860 6. Montù G, Dozio GC, Ben Mrad R, Balemi S (2008) High-performance amplifier for stick-slip piezoeletric motors. In: Proceedings of the 8th euspen international conference, 2008 7. Chen L, Li J, Liu L, Yang F (2009) Development of an adaptive driving module for piezo actuated diesel fuel injector. IEEE Conference on Applied Electronics. Pilsen, Czech Republic 8. Bharath SK, Abdul Rehaman MD, Muralidhara (2016) Simulation and design of voltage driver for piezoelectric actuator. Int J Innov Technol Res (IJITR) 4(3–4):3038–3041 9. http://www.cedrat-technologies.com 10. Kim J, Grisso BL, Kim JK, Ha DS, Inman DJ (2008) Fundamentals of electrical modeling of piezoelectric ceramics for analysis and evaluation of sensory systems. IEEE J Quantum Electron, submitted for publication. SAS 2008—IEEE sensors applications symposium Atlanta, GA, 12–14 Feb 2008 11. Parmar C, Waris M, Pandya V, Design of high voltage full bridge driver for piezoelectric actuator for space applications. In: 2016 IEEE 6th international conference on power systems (ICPS)

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12. Fournier M, Brahim M, Porches T, Sosncicki O (2014) New design of high switching power amplifier for driving piezoelectric actuators in aeronautic applications. In: 2014 16th European conference on power electronics and applications https://doi.org/10.1109/EPE.2014.6910827

Hybrid Feature Extraction Technique on Brain MRI Images for Content-Based Image Retrieval of Alzheimer’s Disease K. Chethan and Rekha Bhandarkar

Abstract Alzheimer is a prominent cause of death, ranked sixth in the list. Timely diagnosis of such abnormalities may help to temporarily minimize its worsening. Computer-aided techniques are adapted to the brain MR images for diagnosing and retrieval of Alzheimer disease images. An immense amount of work has been carried on the generic image retrieval systems using content-based information. These image retrieval schemes have their own merits and demerits in their retrieval performance. So, it is required to develop an efficient content-based image retrieval (CBIR) system in the medical field which is still a challenging task. Therefore, a hybrid features extraction technique has been proposed for CBIR wherein contrast feature, texture-based features and morphological operated features of brain MRI images are extracted and these features are hybridized by applying fusion technique for better Alzheimer disease detection. The proposed approach of feature extraction techniques is evaluated using support vector machine (SVM) and decision tree (DT) classification scheme for pattern learning and classification. Based on the results of feature extraction techniques, SVM and DT achieve an overall accuracy of 91.25 and 86.66% with better precision, recall, sensitivity and specificity. Keywords Content-based image retrieval (CBIR) · Magnetic resonance imaging (MRI) · Discrete wavelet transform · Alzheimer’s disease

1 Introduction Alzheimer’s disease is a sort of dementia. It leads to problems related to memory, thinking capability and behavior of the person [1, 2]. Moreover, Alzheimer’s is an intensifying disease, wherein the side effects gradually get worse over several years and become extreme enough causing trouble in handling the routine tasks [2]. In K. Chethan (B) · R. Bhandarkar Department of ECE, NMAM Institute of Technology, Nitte, Karkala, India e-mail: [email protected] R. Bhandarkar e-mail: [email protected] © Springer Nature Singapore Pte Ltd. 2020 S. Kalya et al. (eds.), Advances in Communication, Signal Processing, VLSI, and Embedded Systems, Lecture Notes in Electrical Engineering 614, https://doi.org/10.1007/978-981-15-0626-0_11

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initial stages, the memory loss is mild, later on patient fails to carry on a conversation and it becomes tough for them to react to environment [2, 3]. Digital images are considered as one of the best and dominant sources for information exchange but a vast amount of digital image data causes diverse complexity issues for providing relevant images over the Internet. This process of providing relevant images according to the query image is known as image retrieval [4, 5]. Some of the image retrieval techniques are: (a) Keyword-based image retrieval (b) Content-based image retrieval (c) Semantic gap-based image retrieval. Content-based image retrieval (CBIR) is a well-known approach and has attracted research and industrial application due to its significant impact on information processing over Internet-based applications. Therefore, CBIR is adapted in medical imaging. According to the working procedure of CBIR, identical is provided based on the query input image defined by the user. In this representation, retrieved images are grouped in decreasing order of similarity depending on the visual property parameters such as shape, texture, and color, etc. [6]. In this process, accurate ranking and collection of images are demanded by real-time applications. A general architecture of CBIR system is depicted in Fig. 1. In today’s medical scenario, images are stored with limited content description, since medical data is expanding day-by-day for proper search of desired medical image which leads to content-based image retrieval system in medical imaging system (CBMIR) [7]. CBMIR is an important process for medical imaging systems which provides potential benefits such as clinical decision support and medical research [8]. Clinical knowledge and diagnostic systems have shown that medical image analysis and its visual characteristics have good impact on better diagnosis, where comparing the past and current medical image, their analysis of features has become a primary approach for diagnosis, moreover, decision-making process can help to develop the recommendation system for diagnosis application. In general, image retrieval approach with relevance feedback is performed by applying following stages: (i) displaying only a few numbers of retrieved images, (ii) indication

Fig. 1 CBIR architecture

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of images based on relevancy and non-relevancy, (iii) feedback process for database learning and (iv) new image selection. This process is repeated several times until the desired performance is not achieved. This process requires a lot of human effort and causes complexity which is not feasible to implement for real-world applications. The CBMIR plays a crucial role as a result of which enormous amount of images being generated by the hospitals every day, labeling and classifying abnormalities by human involvement is a tedious task and may not even be accurate [2].

2 Literature Survey Multiple researches have been presented recently which shows a significant benefit of CBIR in medical application. Rashedi et al. [9] developed an adaptive approach of feature selection using swarm optimization and mixed gravitational search algorithm. Ferreira et al. [10] presented a relevance feedback scheme for image retrieval using a genetic optimization strategy. Faria et al. [11] introduced an approach for MRI image search using partial least square-discriminant analysis (PLS-DA) and principal component analysis (PCA). Unay et al. [12] developed region-of-interest retrieval for brain MRI images. In this process, local binary patterns (LBP) and Kanade-LucasTomasi feature points are extracted. Montazer et al. [13] introduced an approach of CBIR where scale-invariant feature transform (SIFT) descriptor are used for feature extraction and k-means clustering approach is incorporated. For image matching and classification, feature representation is an important task. Lai et al. [14] developed a CBIR model focusing on feature optimization and developed an interactive genetic algorithm, wherein the color image features such as mean value, standard deviation, GLCM features and edge-histogram features are utilized as a feature vector. Sidiropoulos et al. [15] proposed an approach for image retrieval by applying an adaptive hierarchical density histogram by partitioning an image into a two-dimensional area. This process computes point density histogram of the image region and extracted descriptors are combined as global and local properties of the image. Iakovidis et al. [16] developed an approach for medical image retrieval system using PAtterns for Next-generation DAtabase system (PANDA) framework for pattern representation and management. This process also considers both lowand high-level features for feature space representation for image retrieval. Also, the block-based feature computation scheme is applied to estimate the feature space using an expectation–maximization algorithm. Though several works have been accomplished to improve the medical diagnostic systems, still image indexing, feature extraction complexity and retrieval performance are challenging tasks for researchers. Hence, these issues need to be discussed to obtain the satisfactory CBMIR system. The major contribution of the work is as follows:

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(i) A hybrid model is developed for feature extraction. (ii) A comparative classification study is presented using different classification schemes.

3 Proposed Methodology As per the literature review, defining the stages of Alzheimer disease is a challenging task. Therefore, computer vision techniques have been developed for the detection of stages of Alzheimer disease. In the initial phase, the novelty of the work lies in the approach for image enhancement that uses probability density function and segments the obtained histogram into upper and lower regions. The histograms thereupon are updated using logarithmic computation and final enhanced image can be obtained which is required for further processing. After completion of pre-processing, feature extraction with the help of intrinsic mode functions is carried out, where several important features such as spectral entropy feature, spectral magnitude, peak frequency and spectral energy features are extracted and feature vectors are formulated. The performance of feature extraction technique for Alzheimer disease prediction is validated with different classifiers. In CBIR, feature extraction, similarity measurement, indexing systems play an important role and are responsible for image retrieval performance. Digital images contain low- and high-level features which show a considerable impact of database training for retrieval system. Adaptive low- and high-level feature selection can provide the desired performance. Images carry low-level features like as color, shape, texture and object along with high-level features. Any machine interprets images as low-level features, similar to this, CBIR considers low-level features for image indexing. This is a gap between image descriptors, high-level semantics which need to be bridged. Medical images consist of huge amount of information and retrieval accuracy is considered as the main objective in the medical field. Hence, a combined feature extraction model is developed and the flowchart is shown in Fig. 2. Firstly, in the image acquisition stage, a database is built comprising of MRI images of different Alzheimer’s patient. Next, each image in the database is subjected to enhancement process by applying histogram equalization to enhance the features followed by texture-based feature extraction using discrete wavelet transform (DWT) and qualitative features are extracted using morphological operation. An attribute vector is formed by combining the texture-based features and morphologically operated features.

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Fig. 2 Efficient hybrid model of feature extraction technique

3.1 Feature Extraction Feature extraction is a prominent and essential step in CBMIR, wherein the performance of the system relies upon the representation of an image to form an attribute vector. Whenever the input data is found to be substantially huge to be processed by the system and found to be redundant, transformation techniques are desirable to obtain reduce feature representation to consider relevant features which is extremely significant for further processing. There are several features that lie in the image like color, texture and shape. In order to develop an efficient model for feature extraction, the combination of texture-based features such as wavelet, entropy, energy, homogeneity features along qualitative features like contrast, morphological operated features is extracted. Initially, the texture-based feature extraction is discussed below. (1) Texture-Based Feature Extraction Wavelet transform and wavelet texture feature extraction process are depicted in this section. Wavelet transform technique is considered as the most effective tool for time-frequency analysis of any signal. Generally, wavelet transformation is expressed as:

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    Wψ f (m, n) = f (x), ψm,n (x)dx =

 f (x)ψm,n (x)dx

(1)

  −1/2  |m| According to this ψm,n (x) = ψ x−n and ψ(t)dx = 0. This can help to m represent the signal into a different time and frequency windows. Frequency region of the considered input signal is determined by m which is further estimated in the form of low and high frequency. Time parameters of the signal are determined by n. With the help of these assumptions, the wavelet transform can provide complete information about any signal by analyzing time and frequency domain parameters. If input parameters are in the discrete form, then wavelet transform can be expressed as:    ψ f (x)ψm,n (x)dx (2) Wi, j ( f ) = f (x), ψi, j (x) = where ψi, j (x) can be computed as  ψm,n (x) = ψ

x − im 0 n i0 |i 0 |−i/2 m i0

(3)

In medical image scenario, input images are in the form of multiscale, in this function f (x) can be obtained by applying linear combination of wavelet and scaling functions which are expressed as: f (x) =



c j0 (k)φ j0,k (x)+

k

∞

j= j0

  c j0,k = f (x), φ j0,k (x) = 



d j (k) = f (x), ψ j,k (x) =



d j (k)ψ j,k (x)

(4)

k

f (x)φ j0,k (x)dx

(5)

f (x)ψ j0,k (x)dx

(6)



In the proposed feature extraction process, Haar wavelet with dyadic scale a0 = 2 is used. Dyadic scale with a0 = 2 helps to generate the Heisenberg boxes in wavelet domain which can be helpful to cover all frequencies. In pursuance to obtain the   H  are used, which wavelet ψ(x) and scaling function φ(x), the filter banks G, are represented by low-pass and high-pass filter coefficients as g[k] and h[k], respectively,

exertion, Haar wavelet is considered whose coefficients are In this g[k] = √12 , √12 and h[k] = − √12 , √12 These coefficients are computed by √ using initial weight factor which is 2 for wavelet transform. At this stage, each level of m, convolution product is applied using all possible high-pass and low-pass combinations. In this trial, the decomposed image is comprised into two-levels which produced a total of four numbers of partitions of the input image. Wavelet coefficients of each pixel can be obtained by concatenating feature vector as:

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x(i, j) = P 1 (i, j), P 2 (i, j), . . . , P 4 (i, j) 





(7)

To obtain the texture characteristics of input image, mean filter is applied to absolute values of wavelet coefficients: j+1 i+1 1

|Pn (m, n, . . .)| Cˆ n (i, j, . . .) = 4 m=i−1 n= j−1

(8)

Finally, DWT texture feature vector can be given as follows:

x(i, j) = P 1 (i, j), P 2 (i, j), . . . , P 4 (i, j) 





(9)

In accordance with the conventional techniques of feature extraction, huge numbers of features are extracted where some of the features are not correlated to the projected class problem. In this phase, a feature selection technique is required where sometimes relevant features also ignored resulting in inaccurate classification. To overcome these issues, a novel approach of texture feature formulation using a wavelet transformation scheme is presented. (2) Contrast Contrast measures the luminous variations to distinguish the objects in an image [17]. Contrast carries many second-order qualitative features like brightness, morphological features, etc. Contrast is zero for a constant image. This can be calculated as shown in Eq. 10. Contrast =

N −1

Pi, j (i − j)2

(10)

i, j=0

In morphological features, local contrast of the raw image is being highlighted based on multiscale morphology. The traditional approach of contrast enhancement has been continued in the system of mathematical morphology, wherein the intensity values and attributes belonging to particular scale are extracted and altered to improve the local contrast of the image and these features are combined in order to obtain the reconstructed image. (3) Energy It provides the intensity of pixels at an appropriate region of an image [17]. As per the intensity of image brightness estimates, the energy is unity for a constant image. It can be computed as shown in Eq. 11. Energy =

N −1

i, j=0

(Pi j )2

(11)

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(4) Entropy Entropy gives the abundance of information content and measure of uncertainty in an image [17]. It carries texture information of an image. This can be calculated using Eq. 12. Entropy =

N −1

  − ln pi j pi j

(12)

i, j=0

(5) Homogeneity Homogeneity is characterized as the condition of being homogeneous. The arrangement and placement of similar nature of image texture elements is an imperative property of many textures. Also, various texture properties like regularity and fineness/coarseness can be evaluated by applying autocorrelation function to an image. Homogeneity is unity along with a diagonal element of GLCM. This can be computed as shown in Eq. 13. Homogeneity =

N −1

Pi j 1 + (i − j)2 i, j=0

(13)

(6) Morphological Operations The way of representing and describing certain components of an image such as region shape, skeletons, boundaries are usually extracted by an operation known as morphology. The basic operations are carried out using a structural element and image wherein a small-sized structural element, i.e., 3 × 3 is chosen which is comparatively smaller than an image. Erosion and dilation are the two commonly used operators are utilized in order to perform morphological operations on binary image, wherein using erosion, the boundaries of foreground pixels also known as white pixels are eroded away so that size of foreground pixels diminishes and those areas in which the white pixels were eroded are filled with holes. The mathematical definition of erosion is given by: A  B = {Z |(B), ⊆ A}

(14)

Similarly, dilation is opposite to erosion in which the foreground pixels are enlarged at the borders as a result of the pixels grow in size, while the background holes within it shrink. The mathematical definition of dilation is given by:   A ⊕ B = Z |B , ∩A = ∅ 



where ∅ = empty set, B = reflection of collection B, B = Structural element.

(15)

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At this stage, we have numerous features which can be hybridized into a single vector for feature vector formulation. These features are processed and learned using machine learning techniques, which is discussed in the next section.

3.2 Support Vector Machine Classification In order to classify the images, the support vector machine (SVM) classification technique is utilized. A brief discussion about SVM classifier is presented in this section. SVM is considered as the most promising technique which helps to find the optimal separation between classes based on the data edge and class distribution. According to this process, classes are separated linearly in a given q-dimensional space. Let us consider that training data is expressed as {xi , yi }, i = 1, . . . , r and yi ∈ {−1, 1}, Hyperplane can be expressed as w · x + b = 0 where w denotes the normal to the hyperplane, x is a point which lies on the hyperplane and b denotes bias. For linear separable classes, hyperplane can be given as w · xi + b ≥ +1 and w · xi + b ≥ −1. Combination of these two class representation can be given as yi (w · xi + b)−1 ≥ 0. At this stage, training data points which are located on this hyperplane are known as support vectors and used for establishment of optimal hyperplane for classification.

3.3 Decision Tree Classification The algorithm of decision tree classifier is presented in this section as follows: Input: Query image feature Q f , trained dataset, trained label, Query image label, target class Tc Output: Decision tree, predicted class and statistical performance Step 1: input query image attributes and class label i.e. {F, C} → {Feature, Class} Step 2: Tree build initialization with initial splits and entropy as Entropy = 0 Step 3: If training class and target attributes are the same as T = Tc then set the attribute as Tt Step 4: return the attribute as a single node tree as Tt Step 5: check feature of query image if empty then return without any attribute and tree formulation. Step 6: otherwise Step 7: Select initial query image features and compute the entropy Step 8: compute entropy and initiate the root value Step 9: Consider the root value corresponding to the query image attribute.

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Step 10: Update testing feature work according to the initial feature vector and class {Q f → Tt } Step 11: if Tt → empty, go to step 3 Step 12: update the feature vector and add the branch as {Tt1 , Tt2 , . . . , Ttn } ∈ Q f Step 13: formulate sub-tree from the updated feature vector and compare with the target labels Step 14: Return the decision for the corresponding input labels Step15: Compute the statistical performance as classification accuracy and confusion matrix.

4 Results and Discussion To quantify the developed feature extraction model, an experimental study is carried out using OASIS medical imaging database [18]. This database repository contains two types of database of brain MRI known as: (a) cross-sectional MRI and (b) longitudinal MRI wherein both databases consider young, middle age, demented and non-demented older adults for the acquisition of database. • Cross-sectional MRI data: In this set, the cross-sectional brain MRI database of 416 subjects is considered between the ages of 18–96. For each user, 3–4 T1weighted MRI scans are obtained [19]. In this, both men and women participated in database acquisition. 100 users are diagnosed with mild to moderate Alzheimer disease and these users are found to be above the age of 60. • Longitudinal MRI data: This database contains MRI images of 150 users who are aged 60–96. Total of 373 sessions of MRI imaging is considered for image acquisition. For each patient, 3–4 T1-weighted MRI scans are acquired for both right-handed men and women. In this, 72 are considered as non-demented and 64 are considered as demented, 51 are considered with mild to moderate Alzheimer disease. In order to identify the clinical diagnosis status of each user, clinical dementia rating (CDR) analysis is utilized in this database. CDR is a computational process which considers six domains of each user such as: memory, judgment, orientation, problem-solving, functionality, home, hobbies and personal care, etc. [18]. A global CDR rating is generated where 0 rating indicates no dementia, 0.5 denotes very mild dementia, 1 denotes mild, 2 denotes moderate and 3 denotes severe dementia, respectively. The proposed algorithm is being validated with the following input images as shown in Fig. 3. In this work, firstly, the qualitative features like contrast, brightness and morphological features have been extracted as shown in Fig. 4. Next, the GLCM and wavelet texture-based features have been extracted as shown in Fig. 5. Finally, in order to highlight maximum features, both the qualitative features and texture-based

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Fig. 3 Input images for proposed algorithm validation

Fig. 4 a Histogram equalized feature, b threshold feature for brightness and c morphological feature

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Fig. 5 Wavelet features

features are subjected to fusion technique to form a hybrid feature vector as shown in Fig. 6. To evaluate the proposed feature extraction approach, a comparative classification accuracy performance analysis using a support vector machine and decision tree classifier is performed by dividing the complete database into three classes as class1, class-2, and class-3 based on their CDR score. Performance of support vector machine is presented in Table 1. From Table 1, the proposed approach of feature extraction is evaluated using support vector machine classifier which obtains overall accuracy of 91.25% with better precision, recall, sensitivity and specificity performance for each class. Similarly, the performance is measured with the help of decision tree classification scheme as depicted in Table 2. The performance of the decision tree highlights the statistical performance measurement of the proposed approach using a decision tree that achieves overall accuracy as 86.67% which is comparatively less when compared with the support vector

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Fig. 6 a Fused image of qualitative features and b fused Image of qualitative and texture features

Table 1 Statistical performance measurement using SVM Class

Sp

Sen

Pr

Rec

Acc

C1

0.97

0.95

0.97

0.95

91.25%

C2

0.97

0.72

0.90

0.72

C3

0.91

1

0.84

1

where Sp specificity, Sen sensitivity, Pr precision, Rec recall, Acc accuracy

Table 2 Decision tree classification performance Class

Sp

Sen

Pr

Rec

Acc

C1

0.96

0.91

0.95

0.91

86.66%

C2

0.91

0.92

0.80

0.92

C3

1

0.91

1

0.91

machine classification approach. Figure 7 represents a graphical representation of comparative analysis in terms of specificity and sensitivity for both classifiers. Additionally, another statistical comparative performance is analyzed, whereas precision and recall parameters are depicted. Figure 8 depicts precision and recall performance wherein compared precision and recall of both support vector machine and decision tree classifier are possessed. This study shows that the proposed approach with the combination of support vector machine classifier can achieve better performance.

5 Conclusion In this work, an improved feature extraction approach for medical image retrieval is proposed. To improve the performance, feature extraction technique is mainly focused where multiple features are hybridized to formulate a feature vector. For

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Fig. 7 Comparative performance analysis

Fig. 8 Precision and recall performance

medical imaging application, texture feature extraction plays an important role which is carried out using wavelet feature extraction by partitioning image into multiple blocks and GLCM features are also extracted which is combined with wavelet features. Furthermore, contrast feature histogram equalization, brightness and morphological features are identified and fused for extracting better feature in Alzheimer detection. These feature vectors are trained successfully using SVM and DT classifier.

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It is observed that support vector machine classifier and decision tree classifier yields an overall accuracy of 91.25 and 86.67% with a better precision, recall, sensitivity and specificity performance for each class.

References 1. https://www.hearingsol.com/articles/dementia-and-hearing-loss-linked/ 2. Shaju S, Davis D, Reshma KR (2016) A survey on computer aided techniques for diagnosing Alzheimer disease. In: 2016 international conference on circuit, power and computing technologies (ICCPCT) 3. https://www.alz.org/alzheimers-dementia/what-is-alzheimers 4. Bulò SR, Rabbi M, Pelillo M (2011) Content-based image retrieval with relevance feedback using random walks. Pattern Recognit 44(9):2109–2122 5. Yu F, Li Y, Wei B, Kuang L (2015) Image retrieval based on interactive differential evolution. In: 2015 IEEE congress on evolutionary computation (CEC) 6. Alzu’bi A, Amira A, Ramzan N (2015) Semantic content-based image retrieval: a comprehensive study. J Vis Commun Image Represent 32:20–54 7. Jiang M, Zhang S, Li H, Metaxas DN (2015) Computer-aided diagnosis of mammographic masses using scalable image retrieval. IEEE Trans Biomed Eng 62(2):83–792 8. Dhara AK, Mukhopadhyay S, Dutta A, Garg M, Khandelwal N (2017) Content-based image retrieval system for pulmonary nodules: assisting radiologists in self-learning and diagnosis of lung cancer. J Digit Imaging 30(1):63–77 9. Rashedi E, Nezamabadi-Pour H, Saryazdi S (2013) A simultaneous feature adaptation and feature selection method for content-based image retrieval systems. Knowl-Based Syst 39:85– 94 10. Ferreira CD, dos Santos JA, da S Torres R, Gonçalves MA, Rezende RC, Fan W (2011) Relevance feedback based on genetic programming for image retrieval. Pattern Recognit Lett 32(1):27–37 11. Faria AV, Oishi K, Yoshida S, Hillis A, Miller MI, Mori S (2015) Content-based image retrieval for brain MRI: an image-searching engine and population-based analysis to utilize past clinical data for future diagnosis. NeuroImage: Clin 7:367–376 12. Unay D, Ekin A, Jasinschi RS (2010) Local structure-based region-of-interest retrieval in brain MR images. IEEE Trans Inf Technol Biomed 14(4):897–903 13. Montazer GA, Giveki D (2015) Content based image retrieval system using clustered scale invariant feature transforms. Optik-Int J Light Electr Opt 126(18):1695–1699 14. Lai CC, Chen YC (2011) A user-oriented image retrieval system based on interactive genetic algorithm. IEEE Trans Instrum Meas 60(10):3318–3325 15. Sidiropoulos P, Vrochidis S, Kompatsiaris I (2011) Content-based binary image retrieval using the adaptive hierarchical density histogram. Pattern Recogn 44(4):739–750 16. Iakovidis DK, Pelekis N, Kotsifakos EE, Kopanakis I, Karanikas H, Theodoridis Y (2009) A pattern similarity scheme for medical image retrieval. IEEE Trans Inf Technol Biomed 13(4):442–450 17. Haralick R (1979) Statistical and structural approaches to texture. Proc IEEE 67:786–804 18. Marcus DS, Wang TH, Parker J, Csernansky JG, Morris JC, Buckner RL (2007) Open access series of imaging studies (OASIS): cross-sectional MRI data in young, middle aged, nondemented, and demented older adults. J Cogn Neurosci 19:1498–1507 19. Toews M, Wells W III, Collins DL, Arbel T (2010) Feature-based morphometry: discovering group-related anatomical patterns. NeuroImage 49(3):2318–2327

Feature Selection from Gene Expression Data Using SVMRFE and Feed-Forward Neural Network Classifier Nimrita Koul and Sunilkumar S. Manvi

Abstract Correct classification of tumors is an important problem in clinical oncology. Availability of gene expression profiles from DNA microarray experiments has made it possible to use computational techniques to analyze these profiles to identify the molecular biomarkers in samples and hence classify them according to various tumor types. Since gene expression data is very high dimensional and the number of samples is very small compared to the number of dimensions, selection of relevant genes from available gene expression dataset, called as feature selection, is very important to classify samples correctly and efficiently. Various approaches to feature selection have been applied by researchers in literature. In the current work, we have used a method called support vector machine recursive feature elimination for gene ranking with feed-forward neural network as classifier for evaluation of relevance of selected features for the problem of classification of three cancer types using three publicly available gene expression datasets. We compared the classification accuracy and f-score obtained using the proposed method with conventional feature selection-classification pairs—mutual information-random forest classifier, mutual information-support vector machines, particle swarm optimization-support vector machines, principal component analysis-naïve Bayes. The comparison on the basis of confusion matrix parameters—classification accuracy and f-score shows that the proposed method has a better performance as compared to other methods. Keywords Feature selection · Gene selection · Cancer classification · Mutual information component

N. Koul (B) · S. S. Manvi School of Computing and Information Technology, REVA University, Bangalore, India e-mail: [email protected] S. S. Manvi e-mail: [email protected] © Springer Nature Singapore Pte Ltd. 2020 S. Kalya et al. (eds.), Advances in Communication, Signal Processing, VLSI, and Embedded Systems, Lecture Notes in Electrical Engineering 614, https://doi.org/10.1007/978-981-15-0626-0_12

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1 Introduction The data that we use for drawing useful inferences is often for huge in vast volume and not all of it is helpful in drawing meaningful conclusions. A feature is a specific measurable property of data that decides its usefulness to the computational task of analysis being undertaken. In a given dataset, the data values that have an acceptable value of this property for the task being undertaken, are also known as features. The task of classification of data using machine learning algorithms often needs us to select the most relevant data values among all available data such that the algorithm’s accuracy is maximized while having to process the least amount of most relevant input data. In the vast amount of data available for computational analysis today, the number of original features is huge and not all of these are relevant to the machine learning tasks that a researcher may want to perform, therefore, there have been devised many methods to eliminate irrelevant features or select the most appropriate features depending upon the classification problem being tackled. The literature has the methods of feature selection categorized into three groups—filter methods, wrapper methods, embedded methods and the hybrid of these methods called as ensemble approaches. Microarray gene expression data contains the expression values for thousands of genes and very few samples. A lot of these genes are highly correlated and, therefore, even if only one of them under consideration for a classification task, the same classification accuracy results will be obtained faster than using all the correlated features. A big number of these genes are not relevant to investigation of a particular disease; therefore, it is important to filter out these noisy genes so that algorithm can work with only the relevant gene expression values. Rest of this paper is organized as follows—Sect. 1 contains the introduction into various methods of feature selection, Sect. 3 contains a brief walk through the related works in the area of feature selection from gene expression data, Sect. 4 describes the proposed scheme, Sect. 5 discusses the results obtained and analysis thereof, and Sect. 6 concludes the paper and is followed by acknowledgements and references.

2 Feature Selection 2.1 Filter Methods Filter methods [1] rank or score the features based on some inherent property measured by univariate statistics and a threshold score value is used to select the most relevant features. There is no cross-validation. These methods are simple and have been used extensively in literature and have resulted in decent accuracy in the classification tasks. A feature selected by a filter approach, essentially has sufficient measure of the desirable property such that it has an influence on the class label of the sample being classified. In the filter approaches, which select features based

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on information content or mutual information or entropy of input data features, we use the classification accuracy provided by a machine learning classifier algorithm to evaluate the efficacy of selected features and proceed with the most optimal feature subset. Examples of filter methods are—information gain, chi-square test, fisher score, correlation coefficient, and variance threshold.

2.2 Wrapper Methods In wrapper methods [1, 2], the relevance of features is measured based on the performance of a classifier, so these methods optimize the performance of the classifier by repeatedly training the classifier and cross-validation. Predictor is used as a block box and performance of predictor is used as objective function to find the subset of most relevant variables. This subset of features can be found using search algorithms. Evolutionary algorithms like genetic algorithms, particle swarm algorithms, cuckoo search algorithm, etc., are used for this purpose. Wrapper methods are of two types—sequential search algorithms where features are added to an initially empty set and heuristic search algorithms, wherein we broadly classify the wrapper methods into sequential selection algorithms and heuristic search algorithms. In sequential search algorithms, the result set is initially empty and features are added to or removed from it such that the performance of the classifier is maximum. A criteria which increase the classifier performance with minimum number of genes is used. In case of heuristic search algorithms compare different subsets of features for value of classifier performance. These subsets are generated using a search algorithm on original dataset. Examples of wrapper methods are—recursive feature elimination, sequential feature selection algorithms, and genetic algorithms.

2.3 Embedded Methods In the embedded methods the feature selection is used as a part of training proves. An intrinsic metric is used for building a classifier which is used during learning. In case of embedded methods, there is no computation time is taken to reclassify different subsets unlike wrapper methods. Examples of embedded methods are L1 (LASSO) [2] regularization, decision tree, etc.

3 Related Work Feature selection from gene expression data for cancer classification is a wellresearched area and there are many methods proposed for it. Authors in [1] did the pioneering work in establishing that cancers can be classified based on the molecular

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expressions of genes as presented in expression values from DNA microarray technology. They used information theory-based features to select the genes which most correlated with presence of either of the two types of leukemia, acute lymphoblastic leukemia (ALL) or acute myeloid leukemia (AML). Authors in [2] have presented an exhaustive survey of various categories of approaches used for gene selection from gene expression datasets. In [3], authors have proposed a feature selection scheme which divides genes into subsets, finds most informative genes from subsets and then combines these informative genes into an overall set of most informative genes. In [4], authors have used SVMRFE along with minimum redundancy maximum relevancy feature selection algorithm. Wang et al. [5] used t-score and class separability to rank genes which were then classified using supervised machine learning classification algorithms. They constructed subsets of two genes at a time and then applied fuzzy neural network and support vector classifiers for classification. The minimum sized subset that got maximum classification accuracy was retained. In [6], authors have used multiple filter methods and wrapper methods for feature selection from gene expression datasets and presented their comparison. Danaee et al. [7] employed stacked de-noising auto-encoders for feature selection and supervised classification algorithms for classification. Syafiandini et al. [8] has used a multi-modal deep Boltzmann machine for selection of relevant genes. The mean squared error between reconstructed and original features was used to rank the selected features, then kmeans clustering was done to group genes and features that gave highest purity index were shortlisted. Authors in [9] employed multi-category classification using SVM on gene expression datasets. In [10] and [11] also the authors have used SVM and recursive SVM to classify cancer samples from gene expression data.

4 Proposed Scheme In this work, we have carried out gene selection from three cancer datasets using recursive feature elimination as gene ranking technique and feed-forward neural network are classifier to test the classification accuracy of the genes selected. The proposed scheme has been evaluated on five publicly available gene expression datasets for classification accuracy, precision and recall. We compared the classification accuracy and f-score obtained using the proposed method with conventional feature selection-classification pairs—mutual information-random forest classifier, mutual information-SVM, particle swarm optimization-SVM, principal component analysis-naïve Bayes. The comparison on the basis of confusion matrix parameters—classification accuracy and f-score shows that the proposed method has a better performance as compared to other methods.

Feature Selection from Gene Expression Data Using SVMRFE … Table 1 Details of datasets used

147

Dataset

Number of genes

Number of samples

Number of classes

Leukemia

3571

72

2

SRBCT

2308

63

4

Colon

2000

62

2

5 Results and Discussion 5.1 Datasets Used We evaluated our scheme of gene selection and classification on three publicly available gene expression datasets [12] which are described as follows: 1. Leukemia dataset: This dataset has expression values of 3571 genes for 72 patients. There are two classes of cancer: acute lymphoblastic leukemia (ALL) with 47 samples and acute myeloid leukemia with 25 cases. The dataset has been thresholded, filtered, log transformed, and standardized. 2. SRBCT dataset: This data set contains expression profiles of 2308 genes with 63 samples. The samples are divided into four different tumor classes—neuroblastoma, rhabdomyosarcoma, non-Hodgkin lymphoma, and Ewing tumors. The data is standardized to mean equal to zero and variance equal to one for all genes. 3. Colon dataset: This dataset has expression values for 2000 genes and 62 samples. 40 samples belong to colon cancer and 22 are from normal tissue. The dataset is already transformed to base 10 logs and each sample has been standardized to mean of zero and variance of one across genes (Table 1).

5.2 Data Preprocessing The rows corresponding to gene expression values in all three datasets were normalized and thresholded, then log base 10 transformation and standardization to mean zero and variance one was been applied. We used the following three ratios of training to testing set 80:20, 70:30, and 60:40 each repeatedly applied 20 times on each of the three datasets, five-fold cross-validation was applied. Confusion matrix parameters were noted in each run and an average value of classification accuracy and f-score recorded for 20 runs on each dataset and each train and each test ratio. Table 2 shows the results when we compared for a total of 100 features selected using each method. All datasets were downloaded from [12] (Tables 3 and 4).

148 Table 2 Comparison of classification accuracy on leukemia dataset

Table 3 Comparison of classification accuracy on SRBCT dataset

Table 4 Comparison of classification accuracy on COLON Dataset

N. Koul and S. S. Manvi Feature selection method

Classifier

Classification accuracy (%)

Mutual information

Random forest classifier

97.2

Mutual information

SVM

94

Particle swarm optimization

SVM

98

Principal component analysis

Naïve Bayes

95.1

SVMRFE

FFNW

99.1

Feature selection method

Classifier

Classification accuracy (%)

Mutual information

Random forest classifier

95

Mutual information

SVM

89

Particle swarm optimization

SVM

97

Principal component analysis

Naïve Bayes

93

SVMRFE

FFNW

98

Feature selection method

Classifier

Classification accuracy (%)

Mutual information

Random forest classifier

97

Mutual information

SVM

94

Particle swarm optimization

SVM

97.8

Principal component analysis

Naïve Bayes

94

SVMRFE

FFNW

99.2

Feature Selection from Gene Expression Data Using SVMRFE …

149

6 Conclusion Neural networks have shown a wide application in the area of classification tasks. In this work, we applied a feed-forward neural network for classification of tumors after using SVMRFE for feature selection. As expected the classification accuracy has shown an improvement, however, the complexity of neural networks sometimes does out weight the accuracy gains provided by them. Acknowledgements The authors thankfully acknowledge the financial grant received from Department of Science & Technology (DST), Government of India, under the ICPS Scheme 2017.

References 1. Golub TR, Slonim DK, Tamayo P, Huard C, Gaasenbeek M, Mesirov JP, Coller H, Loh H, Downi JR (1999) Molecular classification of cancer: class discovery and class prediction by gene expression monitoring. Science 286(5439):531–538 2. Ang JC, Mirzal A, Haron H, Hamed H (2016) Supervised, unsupervised, and semi-supervised feature selection: a review on gene selection. IEEE/ACM Trans Comput Biol Bioinf 13(5):971– 989 3. Sharma A, Imoto S, Miyano S (2011) A top-r feature selection algorithm for microarray gene expression data. IEEE/ACM Trans Comput Biol Bioinf 9(3):754–764 4. Mundra PA, Rajapakse JC (2010) SVM-RFE with MRMR filter for gene selection. IEEE/ACM Trans Nanobiosci 9(1):31–37. https://doi.org/10.1109/TNB.2009.2035284 5. Wang L, Chu F, Xie W (2007) Accurate cancer classification using expressions of very few genes. IEEE/ACM Trans Comput Biol Bioinf 4(1):40–53 6. Leung Y, Hung Y (2010) A multiple-filter-multiple-wrapper approach to gene selection and microarray data classification. IEEE/ACM Trans Comput Biol Bioinf 7(1):108–117. https:// doi.org/10.1109/TCBB.2008.46 7. Danaee P, Ghaeini R, Hendrix DA (2017) A deep learning approach for cancer detection and relevant gene identification. In: Proceedings of symposium on biocomputing, pp 219–229 8. Syafiandini F, Wasito I, Yazid S, Fitriawan A, Amien M (2017) Multimodal deep boltzmann machines for feature selection on gene expression data. Proc Int Conf Adv Comput Sci Inf Syst 37:293–303 9. Lee Y, Lee CK (2003) Classification of multiple cancer types by multi-category support vector machines using gene expression data. Bioinformatics 19:1132–1139 10. Guyon I, Weston J, Barnhill S, Vapnik V (2002) Gene selection for cancer classification using support vector machines. Mach Learn 46(1):389–422. 11. Zhang F, Kaufman HL, Deng Y, Drabier R (2013) Recursive SVM biomarker selection for early detection of breast cancer in peripheral blood. BMC Med Genomics 6(Suppl 1):S4 12. Dettling M, Bühlmann P (2002) Supervised clustering of genes, Genome Biol 3(12), Article number: research0069.1–research0069.15

Implementation of SAR ADC for Biomedical Applications—A Review Lavita Mendonca and Rekha Bhandarkar

Abstract In recent technology innovations, SAR ADC is a type of architecture commonly used in biomedical applications. The key advantage of SAR ADC is possibility to avoid energy-consuming operational amplifier (OPAMP), less-power consumption features. Along with these advantages of SAR ADC architecture also has challenges to achieve better sampling rate in order to balance speed for satisfactory sampling rate at low power. SAR ADC used for accuracy generally contains satisfactory speed for converting signal which is original in analog form in the area of biomedical application. ADC uses effective part of output fed back to input as feedback. Approximation of signal samples of analog form of signal to digital form is driven by feedback. In the SAR ADC, accuracy is a function precision of matching component used in capacitive array, capability to withstand small changes in signal between corresponding signals at input and output of capacitive array. The measure of speed is a function of DAC and comparators block settling time. In addition to speed, output representation which is the number of bits is responsible for deciding the size of SAR ADC. Keywords Analog-to-digital converter (ADC) · Successive approximation register (SAR) · Comparator · DAC array · Low power · Digital control logic · Biomedical application

1 Introduction The last few decades, importance is given to low-voltage, low-power and high-gain integrated circuits design since the power consumption has become a critical issue. Innovative technology for high-performance analog circuits is becoming increasingly challenging and has become major issue toward reduced supply voltages. This L. Mendonca (B) · R. Bhandarkar Department of ECE, NMAM Institute of Technology, Karkala, India e-mail: [email protected] R. Bhandarkar e-mail: [email protected] © Springer Nature Singapore Pte Ltd. 2020 S. Kalya et al. (eds.), Advances in Communication, Signal Processing, VLSI, and Embedded Systems, Lecture Notes in Electrical Engineering 614, https://doi.org/10.1007/978-981-15-0626-0_13

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challenge has forced designers to develop new innovations more suited for lowvoltage and low-power integrated circuits and it involves much trade-off such as processes, devices, circuits and system architectures. OPAMP is the main building block for ADC architectures. However, the low output impedance of OPAMP makes system power-hungry. Biomedical application areas require effective type of wearable sensors. The major requirement of biomedical devices is compactness and for better performance, energy saving is also a major concern. Design considerations for powerful architecture using CMOS techniques for SAR ADC must be able to meet applications requiring large speed circuits provides ideas for increasing sampling rate. Period of conversion has to be increased to achieve better sampling rate. The conventional SAR ADC is illustrated in Fig. 1. The array of capacitors is DAC block which produces signals which are analog in nature. Comparator block is mainly for quantizing the signal. Logic circuits of digital form will memorize the comparator’s outputs and give back to DAC array as feedback to generate the analog form of signals for next step. The comparator is another important basic block of almost all of the ADC designs. Comparator used also plays a vital role for SAR ADC operation. The output acquired from comparator block can be either single-ended or it can also be fully differential, where design hierarchy is responsible to decide the type of output obtained. Analysis of various possible designs investigates various types of techniques for metrics defining efficiency of system. Therefore, the goal is to design comparators which consume lowest possible power and challenges for various other parameters affecting performance of system such as managing sampling frequency through high resolution is also equally important for overall performance growth. DAC array used for ADC design which consists of capacitor array is also responsible for power consumption. The amount of consumed power is a direct function of various important individual blocks used in design of SAR ADC. Every unit capacitor is associated with calculated amount of power dissipation due to its switching action. And for design of high-resolution energy-efficient SAR ADC then there is always a challenge to have comparator whose accuracy is maintained at maximum.

Fig. 1 SAR ADC block diagram

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2 SAR ADC Architecture Pang et al. [1] proposed SAR ADC using splitting comparator techniques which will results in energy-saving array of DAC. The lowest consumption of power also can be achieved. When result obtained is analyzed with the conventional method, the energy during switching of the array of DAC can be dropped 69% at an average. Signal-tonoise-distortion ratios (SNDR) obtained for the ADC is satisfactory at better sampling rate with less-power consumption from lowered supply voltage. Here, DAC array will result in switching sequence to ensure that more energy is saved. Zhang et al. [2] came up with another SAR ADC in CMOS technique. The voltage at the supply is lowered to obtain low-power consumption. The voltage offset of the latch is applied for achieving lower noise by self calibration. A latch design for a kick-back noise which is kept minimum was developed. SAR ADC was effectively fabricated and analyzed for its results, which shows that it is able to achieve average SNDR and dissipates power in very lower range. The system results in effective figure-of-merit (FOM). The core design of ADC occupies reduced area. Mesgarani et al. [3] proposed method for boosting of supply where low voltage and low power is major goal. It is suitable for circuits where mixed-signal design is employed. Since supply voltage is responsible for power consumption supply boosted SAR ADC is essential with respect to energy-saving perspective for applications in biomedical devices that can be designed in an increased threshold voltage CMOS process technology. Boosting of voltage which is given as supply will definitely improvise the range of input common-mode source and provides lowered voltage required for its suitable operation even when supply voltage holds value of near to threshold voltage. SAR was designed for 10 bit in this case. This technique was developed and demonstrated in a CMOS process where NMOS device is holding +0.8V and that of PMOS is −0.9V as threshold voltage, respectively. By using EDA tool results which are obtained due to simulation show that this type of architecture of SAR ADC is able to achieve satisfactory effective number of bits (ENOB), lowered consumption of power with better sampling rate which can be achieved upon reduced voltage supply. Here, SAR ADC achieved an excellent value of FOM. Lu et al. [4] proposed a SAR ADC where technique utilizes the bootstrapped switch for minimizing leakage. This technique resulted in better ENOB. Approach of low power with reduced voltage resulted in a sampling rate which is comparatively less. Capacitive structure of DAC is observed to be small which is recommended for biomedical application areas. This technique will ensures the weakening the leakage because of the approach of lowering the power. However, this technique resulted in high SNDR and ENOB. The results obtained due to measurement show that total DAC capacitance is very small which is of only 2.765 pF, consumption of power is also low with reduced voltage of supply. SAR ADC is capable of achieving required SNDR range. Only limitation of this technique is FOM is less compared to other techniques. Zhang et al. [5] came up with another important description of SAR ADC for ultralow-power applications in CMOS process for medical devices. It makes use of an

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approach of ultra-low-power, ADC architecture is kept simple where the number of transistors is reduced, reduced voltage, circuit techniques, which minimizes leakage are employed. SAR architecture requires capacitive DAC which results in sampling with recommended switching scheme. Without the requirement of any additional reset voltage and switch required for bootstrapping. In addition to this, a dual-supply usage makes SAR logic which is suitable to work efficiently at voltage value 400 mV. When single-supply is used, ADC consumes reasonable power at lowered sampling rate. It is observed that power consumption can be lowered when dual-supply mode is used instead of single-supply and the ENOB achieved remains same in both the modes. Leakage is the main cause for 24% of the total power consumed which indicates lowest possible in this methodology of SAR. Chiang et al. [6] presented a new power optimization technique, called adaptive tracking for successive approximation ADC recommended for biomedical application areas. A very small modification in the digital logic used will result in tracking technique. The work is found to be comparable with the band-limited sample set values of bio-potentials. Reduced power consumption is also supported with respect to different varieties of SAR ADCs. This kind of tracking scheme is capable of saving and benefiting 30% better overall power in a commonly used SAR ADC. In addition, while compared to those binary SAR ADCs slightly more reduction in overall power is possible. Weighted DAC will uses capacitor split method at MSB position. By using charge sharing arrays of capacitors 8% of overall power can be reduced providing efficiency improvement. Yadav et al. [7] presented a ten-bit architecture of SAR ADC which is intended for biomedical application areas. Achievement of very minor range power consumption makes technique more suitable to fulfill needs of biomedical devices. A highly recommended reduced power design technique has been employed. This technique makes SAR ADC architecture as simple as possible by reducing overall transistor number which results in providing area efficiency. Along with suitable voltage which is given as supply SAR ADC is able to achieve sampling rate intended for signals commonly called bio-potential signals. This methodology was successful to achieve average SNDR which is satisfactory, reduced power with largest FOM value. Yu et al. [8] came up with a technique of SAR ADC which makes use of master and slave DAC technique. Method was successful to decrement 93% of the energy dissipation caused when analyzed with the result of normally used DAC array. Performance with improved SNDR ratio, where consumption of power is also limited to minor value. Sampling rate is found to be effective with the suitable supply voltage, with area of internal core kept minimum. Yang et al. [9] proposed design of SAR ADC with goal of satisfying ultra-lowpower. The SAR ADC is offered with ultra-low-voltage, with specialized structure which is single-ended. In addition to this sampling technique used in this case is based on top plate. To improvise linearity of circuit which is used for sampling major role is played by bootstrapped switch. The correction of errors caused due to decision during initial few conversions is done by using an algorithm based on non-binary redundancy. The experimental observations obtained using CMOS process, it was

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155

noted that ADC architecture consumes lowest power when offered with minimum voltage as supply. Yang et al. [10] came up with a new innovative calibration method. The amount of split capacitive mismatch present at MSB-side is measured with the help of LSB-side. It is responsible for reduction in overall chip area and will save from any mismatch caused due to capacitive array The design, in this case, focuses on digital part using Verilog Hardware description language. The results obtained through effective simulation show reduced supply voltage features at low power at better sampling rate and the SNDR observed is also satisfactory when signal used is sinusoidal. This type of calibration method will result in acceptable FOM. Lai et al. [11] proposed a technique for application area of biomedical systems commonly required in implanted systems whose aim is to keep power value as minimum, and to design ADC which gives excellent performance. SAR architecture is found to be the most recommended choice to keep power consumption minimum and to obtain smallest possible area occupied by the die. In this case, a focus is kept to design an effective switching methodology using array of capacitors which leads to improvement in area and energy efficiency. The sampling rate is in an acceptable range while managing suitable SNDR with decrement in power consumption. Lai et al. [12] proposed another SAR ADC methodology. Number of bits present in this ADC is eight bits. Control logic used for SAR will reduces comparator block and power consumption caused due to other digital part of the circuit. Switch used for bootstrapping will generally overcome any limitation caused due to resistance changes in the analog form of switch used for sampling which in turn caused due to variation in signal at input. Observed results indicate that high sampling rate is possible by using this technique along with acceptable SNDR range and low power. The core of SAR ADC occupies small very area. Hu et al. [13] presented an effective SAR ADC for biomedical applications areas requiring signal detection. Total power consumed is effectively reduced while compared to conventional SAR. The area is also optimized by maintaining ENOB. Integrators which consume less power are applied in this architecture. SAR ADC operates at medium sampling rate consuming lowest power whenever a suitable voltage is given as supply. Even though FOM achieved is observed to be poor, SNDR is within acceptable range for better operation of SAR. Delgado-Restituto et al. [14] came up with a ADC of category SAR. The number of bits present in ADC is effective ten bits whose major goal is biomedical areas of applications. The main importance is given to such architecture because energy consumption is managed through lowest switching. The time-domain comparator functions for its ability to perform offset cancelation mechanism. Fan et al. [15] proposed innovative re-configurative techniques for capacitors to improve two main key parameters such as the spurious-free dynamic range (SFDR) and SNDR. These performance parameters have to attained by focusing on effective rate at which sampling takes place for wearable devices benefits in medical applications. Simulation is performed and verified using Monte Carlo technique of simulation. Results obtained through EDA tool give proof that mismatch error is

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commonly found in latest technologies. This technique is suitable for linearity and accuracy requirements. Carandang et al. [16] came up with another better performance SAR ADC. This ADC will be much needed for biomedical applications where signals are usually considered to be slow. The strategy of design of SAR is most preferred for compact device applications of biomedical areas. As a EDA tool for implementation and validation of design Synopsys is used. The experimental results show that sampling rate requirement of biomedical applications is met with lowering of consumed power is possible. Sadollahi et al. [17] presented another efficient SAR ADC architecture which meets area minimized requirement consisting of effective 11-bits. Due to some minor loading effect technique is preferred in the biomedical areas of applications. An efficient switching is essential to save energy which is fulfilled by the capacitive array which can handle the error and dissipates less switching power. The system performance of ADC is improved by weakening loading effect of the previous stage. This is ensured by the role of structure which is single-ended and also by huge capacitance. The design is met in subthreshold range of operation which will obviously result in minimizing power consumption for better efficiency achievement. Along with SAR logic of asynchronous form, the ADC is capable of handling low power by lowered voltage at supply terminal. Guan et al. [18] presented a SAR ADC for applications of biomedical devices. Here, in this case, calibration method is employed which basically operates to avoid errors in capacitive array and corrects those errors which does not match. This type of innovative technique may either occur in CDAC or split CDAC. With voltage of supply, it is possible to convert input form of high voltage signal and without a significant weakening of the input signal. To improvise the conversion rate switching scheme is modified in SAR logic and used. ADC is capable of largest peak value of SNDR range with huge value of FOM. Wan et al. [19] proposed description on pipelined ADC. The implementation and experimental results show powerful sampling rate compared to any other types of ADCs. The eight-bit ADC is capable of achieving extremely good linear characteristics with respect to its performance. Architecture makes use of sample-and-hold circuit which will amplify the signal in this case. However, the technique has huge SFDR and poor SNDR as major drawback but ADC is able to balance lower power criteria (Table 1).

3 Conclusion A brief survey on various available techniques for possible designs of SAR ADCs involving CMOS process technology is carried out. The techniques are analyzed and summarized from different views related to performance. It is possible to design energy saving SAR ADC using different comparator and effective capacitive DAC techniques such as splitting comparator, low kick-back noise latch for minimum

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157

Table 1 Comparison between various ADC’s References

Technology Sampling (µm) rate (S/s)

Power consumption (W)

Supply voltage (V)

FOM SNDR (J/conversion- (dB) step)

[1]

0.18

500 k

42µ

1

124 f

[2]

0.18

2k

455 n

–

220 f

61.8

[3]

0.5

100 k

12 µ

1.2

166.3 f

–

[4]

0.18

1k

2.5 n

0.5

6.8 f

53.05

[7]

0.18

1k

43 n

1

73 f

57.16

[8]

0.18

500 k

28 µ

1

77 f

59.2

[9]

0.18

1k

16 n

0.5

59.1 f

50.4

[10]

0.13

238 k

25.4 µ

0.9

52 f

68

[11]

0.18

200 k

6.2 µ

1.8

18.6 f

67

[12]

0.18

2M

128 µ

1.8

421 f

42.7

[13]

0.18

10 k

73 n

1

8.9 f

60

[14]

0.18

4k

76.2 n

1/0.5

26.3 f

–

[16]

0.9

100 k

20 µW

1.2

–

–

[17]

0.18

10 k

250 n

0.75

28.8 f

60.5

[18]

0.18

1M

6.75 m

1.8/3

0.41 p

86.16

[19]

0.13

250 M

60 m

1.2

–

46.6

58.4

noise, supply boosting technique to improve input common mode and LRBS method for reduced leakage effect. A rail to rail fully differential SAR features low switching energy. Low-power integrator can also used for reduction of comparator noise and quantization noise. However, the dynamic latched comparator is best suitable comparator design which consumes very less power while compared to other techniques. Tracking SAR ADC and pipelined ADC ensures better speed and high resolution. Binary-weighted capacitive array ensures that unit capacitor is kept small which is more preferred to save overall power compared to other DAC techniques such as master–slave DAC, linearity enhancement capacitor reconfiguring technique, novel digital calibration method for capacitive mismatch at LSB-side of array, fast binary window DAC switching. However, the effective design and implementation of SAR ADC is possible by combining low-power dynamic latched comparator with binary-weighted capacitor array along with energy-saving SAR logic using transmission gates to achieve ultralow-power and area optimized design.

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References 1. Pang W, Wang C, Chang Y, Chou N, Wang C (2009) A 10-bit 500-KS/s low power SAR ADC with splitting comparator for bio-medical applications. In: 2009 IEEE Asian solid-state circuits conference, Taipei, pp 149–152 2. Zhang H, Qin Y, Yang S, Hong Z (2010) Design of an ultra-low power SAR ADC for biomedical applications. In: 2010 10th IEEE international conference on solid-state and integrated circuit technology, Shanghai, pp 460–462 3. Mesgarani A, Ay SU (2011) A low voltage, energy efficient supply boosted SAR ADC for biomedical applications. In: 2011 IEEE biomedical circuits and systems conference (BioCAS), San Diego, CA, pp 401–404 4. Lu T, Van L, Lin C, Huang C (2011) A 0.5 V 1 KS/s 2.5 nW 8.52-ENOB 6.8 fJ/conversion step SAR ADC for biomedical applications. In: 2011 IEEE custom integrated circuits conference (CICC), San Jose, CA, pp 1–4 5. Zhang D, Bhide A, Alvandpour A (2011) A 53-nW 9.12-ENOB 1-kS/s SAR ADC in 0.13µm CMOS for medical implant devices. In: 2011 proceedings of the ESSCIRC, Helsinki, pp 467–470. 6. Chiang KC, Artan NS, Chao HJ (2013) A signal-specific approach for reducing SAR-ADC power consumption. In: 2013 IEEE biomedical circuits and systems conference (BioCAS), Rotterdam, pp 278–281 7. Yadav K, Patra P, Dutta A (2015) A 43-nW 10-bit l-kS/s SAR ADC in 180 nm CMOS for biomedical applications. In: 2015 IEEE Asia Pacific conference on postgraduate research in microelectronics and electronics (PrimeAsia), Hyderabad, pp 21–25 8. Yu Y, Huang F, Wang C (2014) A 1V 10-bit 500KS/s energy-efficient SAR ADC using masterslave DAC technique in 180 nm CMOS. In: Technical papers of 2014 International symposium on VLSI design, automation and test, Hsinchu, pp 1–4 9. Yang YK, Liu X, Zhou J, Cheong JH, Je M, Goh WL (2013) A 0.5 V 16 nW 8.08-ENOB SAR ADC for ultra-low power sensor applications. In: 2013 IEEE MIT-S International microwave workshop series on RF and wireless technologies for biomedical and healthcare applications, Singapore, pp 1–3 10. Yang X, Zhou Y, Zhao M, Wu X (2015) A 12 b 238 kS/s SAR ADC with novel built-in digital calibration method for EEG acquisition applications. In: 2015 IEEE biomedical circuits and systems conference (BioCAS), Atlanta, GA, pp 1–4 11. Lai C, Zhao M, Su H, Wu X (2014) A 12 b 200 KS/s SARADC with novel capacitor switching procedure and digital background calibration. In: 2014 12th IEEE international conference on solid-state and integrated circuit technology (ICSICT), Guilin, pp 1–3 12. Lai WC, Huang J, Hsieh CG, Kao F (2015) An 8-bit 2 MS/s successive approximation register analog-to-digital converter for bioinformatics and computational biology applications. In: 2015 IEEE 12th international conference on networking, sensing and control, Taipei, pp 576–579 13. Hu J, Liu M, Liu S, Ding R, Zhu Z (2018) A 10-KS/s 625-Hz-bandwidth 60-dB SNDR noiseshaping ADC for bio-potential signals detection application. In: 2018 IEEE Asia Pacific conference on circuits and systems (APCCAS), Chengdu, pp 46–49 14. Delgado-Restituto M, Carrasco-Robles M, Fiorelli R, Gines-Arteaga AJ, Rodriguez-Vazquez A (2016) A 76 nW, 4 kS/s 10-bit SAR ADC with offset cancellation for biomedical applications. In: 2016 IEEE Asia Pacific conference on circuits and systems (APCCAS), Jeju, pp 421–424 15. Fan H, Heidari H, Maloberti F, Li D, Hu D, Cen Y (2017) High resolution and linearity enhanced SAR ADC for wearable sensing systems. In: 2017 IEEE international symposium on circuits and systems (ISCAS), Baltimore, MD, pp 1–4 16. Carandang J, Fortu J, Mojares J, Santos A (2017) Development of a low power 8-bit successive approximation register ADC in 90 nm process technology for biomedical application. In: TENCON 2017–2017 IEEE region 10 conference, Penang, pp1315–1320 17. Sadollahi M, Temes G (2017) An 11-bit 250-nW 10-kS/s SAR ADC with doubled input range for biomedical applications. In: 2017 IEEE 60th international Midwest symposium on circuits and systems (MWSCAS), Boston, MA, pp 385–388

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18. Guan R, Xue J, Yang C, Jin J, Zhou J (2018) 16-bit 1-MS/s SAR ADC with foreground digitaldomain calibration. IET Circ Devices Syst 12(4):505–513 19. Wan P, Lang W, Fang D, Cui W, Lin P (2011) A 1.2-V 250-MS/s 8-bit pipelined ADC in 0.13-µm CMOS. In: 2011 9th IEEE international conference on ASIC, Xiamen, pp 986–989

Energy-Efficient Communication Using Data Aggregation and Data Compression Techniques in Wireless Sensor Networks: A Survey S. Pushpalatha and K. S. Shivaprakasha

Abstract Wireless Sensor Network (WSN) has been emerging as the most promising technology of future communication. WSNs face numerous research challenges, and one such challenge is the limited batteries in sensors. Thus, the data communication in WSNs has to be energy efficient. As nodes are densely deployed, data sensed by them are more likely to be correlated. This can be considered as an advantage to compress and combine the data from different nodes in WSNs. Ample number of researchers have worked in this area, and a good number of data compression and data aggregation algorithms were proposed in literature. In this paper, an attempt has been made in summarizing and comparing different compression and data aggregation algorithms proposed for WSN applications. Keywords Sensor nodes · Data aggregation · Data compression

1 Introduction WSNs are considered as a network of large number of sensor nodes that are deployed in an unattended environment. They are infrastructure-less networks monitored by a central entity called the Base Station (BS). These networks are application specific, and the design of WSN depends on the application. Energy limitation is one of the major problems in any wireless network. One of the major issues of design consideration for most of the WSN applications is the energy efficiency. Although the advancements in the battery technologies are contributing towards the enhancement of the network lifetime, developing sophisticated in-network algorithms is also very much needed. S. Pushpalatha (B) Department of DECS, VTU Centre for PG Studies, Mysuru, India e-mail: [email protected] K. S. Shivaprakasha Department of ECE, N.M.A.M. Institute of Technology, Nitte, India e-mail: [email protected] © Springer Nature Singapore Pte Ltd. 2020 S. Kalya et al. (eds.), Advances in Communication, Signal Processing, VLSI, and Embedded Systems, Lecture Notes in Electrical Engineering 614, https://doi.org/10.1007/978-981-15-0626-0_14

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In WSNs, large number of nodes are deployed in random fashion for most of its applications. By the virtue of its positions, nodes in WSNs present both temporal and spatial correlations. Thus, there is a good scope for not only the data compression within the nodes but also the aggregation of the data sensed by the nearby nodes. Hence, in-network data compression and aggregation can remove the redundancy and also lessens the unnecessary data forwarding and hence reduces the battery usage in nodes. This paper presents a qualitative analysis of the data compression and aggregation algorithms proposed in literature [1–3]. The remainder of the paper is organized as follows: Sect. 2 details the overview of the concepts of data aggregation and compression algorithms proposed for WSNs. Section 3 presents a comparative analysis of the data aggregation algorithms. Section 4 presents an analysis of the compression algorithms proposed for WSNs. Finally, Sect. 5 gives the concluding remarks of the paper.

2 Data Aggregation and Compression Algorithms in WSNs Data aggregation and data compression are the two efficient ways to reduce the data traffic in WSNs. They not only enhance the network lifetime through lessening the energy consumption but also improve the network performance by reducing the burst traffic in the network and hence achieving the higher network throughput.

2.1 Data Aggregation Data aggregation is a process of collecting information sensed by different nodes in the close proximity, application of suitable algorithms for removing the redundancy and thus assuring energy-efficient communication in WSNs. Large number of nodes in WSNs paves a good chance of dependency of the information sensed by nearby nodes. This fact can be explored, the information collected from the nodes within a close proximity can be combined, and the aggregated information can be sent to the BS instead of the individual data. This technique has proved to be an efficient way of energy conservation in WSNs [4, 5]. Data aggregation is easier in cluster-based routing algorithms. In cluster-based WSNs, nodes are grouped into clusters, and one node in the cluster is made as the Cluster Head (CH). All other members of the cluster communicate the information to the CH, and the CH has to convey the same to the BS. In this approach, data aggregation can be incorporated at CHs so that the CH in each cluster receives, processes and combines the information sent by the cluster members, and only the aggregated data can be transmitted to the BS [6].

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2.2 Data Compression Nodes in WSNs sense a physical change on continuous manner. This would certainly result in the presence of temporal correlation in the data sensed by the sensors. Thus, sophisticated data compression algorithms can be developed so as to reduce the data size in each node before the information transmission. Modern researchers have come up with a new idea of compressive sensing where the compression is also incorporated during the process of sensing itself. This would not only reduce the size of the data transmitted but also enhance the network lifetime. Most of the WSN applications involve long-term monitoring of the physical changes. Such application involves large energy consumption as the nodes sense and transmits the information on regular basis for a long duration. Since data transmission is one primary factor of the energy consumption of sensor nodes, many research efforts focus on reducing the amount of data transmissions through compressed sensing techniques.

3 Comparative Analysis of Data Aggregation Algorithms This section provides a comparative analysis of various data compression and data aggregation algorithms proposed for WSNs. The performance of data aggregation algorithms is dependent on various network parameters. The type of the network is one of the important factors. Dynamic networks pose more complicated issues in the algorithm design. Whether the nodes are homogeneous or heterogeneous also plays an important role in the performance. Finally, the configuration of the network is also an important parameter of interest. The analysis of various data aggregation algorithms proposed in literature has been carried out, and the same is depicted in Table 1.

4 Comparative Analysis of Data Compression Algorithms The data compression algorithms are categorized into two major categories: Lossless and Lossy Compression algorithms. The degree of compression achieved in lossless compression algorithms is upper bounded by the entropy of the source. Any compression beyond that would lead to lossy compressions. Both lossless and lossy algorithms are proposed in literature. The performance of compression algorithm proposed is also dependent on the type of the network. Most of the algorithms use tree-based networks. A qualitative comparison of various data compression algorithms is presented in Table 2.

Type of network

Cluster based

Dynamic network topology

Cluster based

Grid network based

Paper

[7]

[8]

[9]

[10]

Maximization of the network lifetime

Increases the network efficiency

Lessens communication overhead and still assuring safety and reliability

Enhanced network lifetime

Parameter assured

Adaptive routing algorithm (ARA)

SEED algorithm

Secure and Itinerary-based data aggregation algorithm (SCIDA)

data fusion algorithm FTDA

Algorithm used

Table 1 Comparative analysis of data aggregation algorithms

Residual energy of the sensor nodes is considered

Only one node stays active and conveys the sensed information to the CH

Encrypted information is transmitted to the BS

Prediction during the data transmission is accomplished using exponential smoothing prediction model

Algorithm description

Randomly deployed sensors are grouped in grid layouts

CHs are chosen on rotation basis, purely on the residual energy

Not architecture dependent

Nodes have same energy capability and use clock synchronization

Network configuration

Real-time applications

Communication based

Security applications

Environment monitoring, military surveillance

Application

(continued)

Homogeneous

Both homogeneous and heterogeneous

Homogeneous or Heterogeneous

Homogeneous

Type of nodes

164 S. Pushpalatha and K. S. Shivaprakasha

Type of network

Cluster based

Cluster based

Grid-based clustering, static

Tree based, static

Paper

[11]

[12]

[13]

[14]

Table 1 (continued)

Balancing of the residual energy amongst the nodes and extend the network lifetime

Minimizing energy consumption and prolong lifetime

Enhancement of the network lifetime

Performance analysis with respect to energy awareness, network delay and accuracy

Parameter assured

Genetic algorithm

–

State transition algorithm

PFF Algorithm, k-means adopted to variance study and distance-based redundancy searching algorithm

Algorithm used

Algorithm is made up of fitness and selection functions

–

3D models are being used for the arrangement of the sensors with a threshold that is dependent on the geographical characteristics

Similar functions are used to check for the prefix measures amongst the pairs

Algorithm description

A chromosome is the collection of nodes, and each node has a parent ID

Network is grouped into different clusters

State transition is applied to both CH and leaf node

Single-hop transmission is used for the communication between the members and the CH and CH and the BS

Network configuration

Environment monitoring

Real-time applications

Rainfall-induced landslide detection

–

Application

(continued)

Homogeneous

Homogeneous

Homogeneous

Homogeneous

Type of nodes

Energy-Efficient Communication Using Data Aggregation … 165

Type of network

Cluster-chain based

Chain based

Cluster based

Cluster based

Paper

[15]

[16]

[17]

[18]

Table 1 (continued)

Maximization of the network lifetime and reduction of the network latency

Energy efficiency, Swabbing redundant data transmission

Prolonging of the network lifetime

Enhancing network lifetime and energy efficiency, lessening the delay

Parameter assured

Bilayer-based data aggregation algorithms

Voronoi-based genetic clustering algorithm (VBGC)

Cluster-chain mobile agent routing (CCMAR) Algorithm

Algorithm used

TDMA is used as the intra-cluster transmission scheduler, and CSMA is used for inter-cluster communication

Voronoi diagram, Fitness function of GA is used

The advantages of LEACH and PEGASIS were exploited to the fullest extent

Algorithm description

Wireless network is divided into bilayer, and number of CHs to each layer is optimized by GA

The Euclidian distance between sensor node, and CH is considered to evaluate the fitness function

Chain head selection also varies from protocol to protocol

Divides network into a few clusters and operates in two phases

Network configuration

Communication based

Communication based

Military habitant monitoring, Disaster management

Small-scale WSN applications

Application

(continued)

Homogeneous

Homogeneous

Homogeneous

Homogeneous

Type of nodes

166 S. Pushpalatha and K. S. Shivaprakasha

Type of network

Grid network based and tree-based network

Not specified

Cluster based

Paper

[19]

[20]

[21]

Table 1 (continued)

Assure energy conservation and reduced latency

Reduction of the overall network transmission cost

Assurance of minimum-cost forwarding and reduced message overheads

Parameter assured

Bilayer-based data aggregation algorithm and LEACH Algorithm

Hybrid routing algorithm

Straight forward asynchronous distributed algorithm and MCFA (minimum-cost forwarding algorithm)

Algorithm used

TDMA is used as the transmission scheduler for member nodes

Combination of routing algorithm based on entropy coding and the SPT algorithm

Nodes need to broadcast the updated information after attaining lesser acquiring cost using asynchronous algorithm

Algorithm description

Nodes of the network are divided into two layers, and clusters are formed based on the LEACH mechanism

The next hop is decided based on the Entropy coding. SPT algorithm is used to determine the next hops for a node that is near to the sink

Binary tree is used as the service tree, and for the MAC, CSMA protocol is used

Network configuration

Real-time applications

Used in smart grids, secure communication technologies and computational intelligence

Application

(continued)

Homogeneous

Homogeneous

Homogeneous

Type of nodes

Energy-Efficient Communication Using Data Aggregation … 167

Type of network

Cluster based

Cluster based

Tree based

Paper

[22]

[23]

[24]

Table 1 (continued)

Bandwidth utilization and energy conservation

Minimization of the delay (or latency)

Assure energy conservation and stabilization of the clustering method

Parameter assured

DAA, monitoring node selection algorithm and SDFC

Centralized algorithm

Voronoi fuzzy clustering algorithm (VFCA), Voronoi-based genetic clustering algorithm (VGCA), K-Means data relay clustering algorithm

Algorithm used

Reduction of communication overhead of algorithm SDFC, the size of each FMAC is kept fixed

Algorithm is aggregation-tree based and uses distribution scheduling implementation

VFCA is a combination of Voronoi structure and fuzzy C-means clustering algorithm

Algorithm description

At least T nodes are considered to be present between any two data aggregators

Transmission ranges are assumed to be same for all nodes

Voronoi structure is used to divide the region into different cells, and each cluster is assigned with a supervisor node called the CH

Network configuration

Real-time applications

Communication based

Application

(continued)

Homogeneous

Homogeneous

Homogeneous

Type of nodes

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Type of network

Not specified

Cluster based

Paper

[25]

[26]

Table 1 (continued)

Enhancement of energy efficiency, balancing of the energy dissipation and prolonging the network lifetime

Achieving energy efficiency, prolonging the network lifetime

Parameter assured

Energy efficient and balanced cluster-based data aggregation algorithm (EEBCDA)

DAACA algorithm

Algorithm used

CH consumes more energy, and thus, more nodes take part in CH rotation process and share energy load

Operates in three phases: initialization phase, transmission of the packets and operations on pheromones

Algorithm description

CHs send the information to the BS by direct communication

Every node determines its residual energy, and the amount of pheromones of neighbouring nodes are used to estimate the probabilities for choosing the next hop dynamically

Network configuration

Real-time applications

Communication based

Application

Homogeneous

Homogeneous

Type of nodes

Energy-Efficient Communication Using Data Aggregation … 169

Parameter assured

Data size reduction establish a tradeoff between energy, rate and accuracy

Good data compression for the cases not only with high degree of correlation but also with medium degree of correlation

Reference

[27]

[28]

Tree-based network

Type of network

Lossless

Lossless

Type of compression

Table 2 Comparative analysis of data compression algorithms

Modified Huffman coding

Entropy encoded codebook compression (EECC) and pipelined codebook compression (PCC)

Technique used

Operates in phases. In the first phase, the source statistics are collected, and the source coding is performed in the second phase. Root node of the tree is assigned with the largest node number

In EECC, symbols are represented by codewords whose length is proportional to the negative logarithm of its probability PCC assures combining of the sensed data into a single packet

Algorithm description

(continued)

Physical environment monitoring

Medical applications, compression of source codes

Applications

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Parameter assured

Comprehensive survey of recent research on the data compression techniques in WSNs

Compression adaptable to dynamic sources

Reduction in End-end delay

Assure accuracy

Reference

[29]

[30]

[31]

[32]

Table 2 (continued)

Tree-based network

Cluster-based network

Tree, cluster and chain based network

Type of network

Lossless compression

Lossless

Lossless

Lossless

Type of compression

Adaptive Huffman code

Distributed compression techniques and local techniques

Adaptive Lossless Data Compression (ALDC) algorithm

The string-based, distributed source coding techniques and data aggregation techniques

Technique used

The input is scanned, a code is assigned, and the Huffman tree is updated so as to assure optimum state of the tree at all times

Suits for delay sensitive applications as it offers a lesser packet transmission time and less contention on the wireless channel

Compression schemes are adaptable to the dynamic source Adaptive lossless entropy compression is used

Considering data as a sequence of characters, and data compression algorithms are then used to compress the text data

Algorithm description

(continued)

Measuring the temperature in WSN

Compressing temperature and humidity data sets in solar radiations, Seismic and ECG

Real-time, delay tolerant systems, monitoring systems

Long-term environmental monitoring

Applications

Energy-Efficient Communication Using Data Aggregation … 171

Parameter assured

Size reduction of text data

To measure the compression ratios of different algorithms

To measure the compression ratio and compressed file size

Reference

[33]

[34]

[35]

Table 2 (continued)

Tree-based network

Tree-based network

Type of network

Lossless or lossy compression

Lossless

Lossless

Type of compression

RLE, RLL, Huffman, LZ, LZW and HLZ

Shannon Fano, Huffman coding and arithmetic encoding

Bit reduction algorithm for text compression

Technique used

A ‘dictionary’ of complete or partial words in a message is constructed, and the encoding is carried out by indexing to the words in the dictionary

A binary code tree is constructed, and codes are assigned based on the symbol probability

Encoding using a standard 7-bit encoding is reduced to a 5-bit encoding system specific to an application and then pack into a byte array

Algorithm description

(continued)

Environmental monitoring

File storage and distributed system

SMS application

Applications

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Parameter assured

Performance analysis of compression of text data

Enhancement of the network lifetime

To increase the compression ratio compared to RLE

Reference

[36]

[37]

[38]

Table 2 (continued)

Tree-based network

Tree-based network

Type of network

Lossless

Lossless

Lossless

Type of compression

K-run-length encoding

Huffman coding, arithmetic coding

Shannon Fano algorithm, Huffman encoding and LZW

Technique used

For a sequence comprising of the same symbol occurring multiple times, the sequence is replaced by the count indicating the number of symbols of the same type

Huffman coding is a variable length coding algorithm, and arithmetic coding achieves almost the optimum compression

Encoding of the symbols is done based on the probability of occurrence. Symbols that are more likely occur are assigned with shorter code words and vice versa

Algorithm description

(continued)

Multimedia applications

Military surveillance, habitat monitoring, structural monitoring and medical applications

Real-time systems

Applications

Energy-Efficient Communication Using Data Aggregation … 173

Parameter assured

Estimation of the achievable energy gains with a priori compression process

Comparative analysis based on figure of merit

Energy efficiency of sensor nodes

Compression ratio, energy efficiency and reliability

Reference

[39]

[40]

[41]

[42]

Table 2 (continued)

Tree-based network

Type of network

Lossless

Lossless

Lossless

Lossless

Type of compression

Shannon–Fano coding, static Huffman coding

Packet level data compression algorithm

Linear predictive coding

Run-length encoding algorithm, adaptive huffman coding (AHC)

Technique used

Huffman algorithm inputs a list of non-negative weights and constructs a full binary labelled tree using weights

Sensing physical layer protocol, sensing data and processing protocol

This algorithm presents three versions: static version, dynamic version and a dynamic cyclo-static version

First variant works on a byte-by-byte basis, and the second variant fixes the first occurrence position of a symbol and compares with AHC

Algorithm description

(continued)

Used in energy limited systems

Home care, medical applications

Applications

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Parameter assured

Enhancement of the lifetime of CHs

Enhancement of battery life, reliability

Performance measures of different data compression algorithms

To reduce storage and computational resources of a WSN node

Reference

[43]

[44]

[45]

[46]

Table 2 (continued)

Cluster-based network

Type of network

Lossless

Lossless

Lossless

Lossless

Type of compression

S-Lempel–Ziv–Welch (S-LZW)

Bit Reduction algorithm, Huffman Coding, Shannon–Fano Algorithm, RLE, Burrows–Wheeler Transform

Lempel–Ziv–Welch (LZW) Compression

Lempel–Ziv–Welch (LZW) compression in LEACH-C protocol

Technique used

Explores the correlation present between the consecutive samples sensed by a sensor node

Various algorithms proposed for the compression of English text are analysed

A string translation table is generated from the data to be compressed. A mapping of string to a fixed length code is done by the algorithm

Input sequence of a given length is taken, and a corresponding entry in a table for the same is created

Algorithm description

(continued)

Emergency operations, Military surveillance, Habitat monitoring

Personal Area networking, military, civilian applications

Civilian, health care, habitat monitoring

Applications

Energy-Efficient Communication Using Data Aggregation … 175

Parameter assured

Study of the application of rate-distortion codes in building compressed sensing recovery algorithms for stochastic processes

To minimize reconstruction error caused by the spatial interpolation and distributed compression

Reference

[47]

[48]

Table 2 (continued)

Type of network

Lossy

Lossy

Type of compression

Distributed spatial interpolation

Rate-distortion dimension (RDD), compressible signal pursuit (CSP), information dimension

Technique used

Sensed fields are represented as a sum of sparse common component and a sparse innovation component specific to a sensor node

A relationship between the rate-distortion dimension of the source, and its information dimension is established

Algorithm description High-resolution imaging

Applications

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5 Conclusion WSNs are networks with limited energy availability. Since the maximum energy is consumed during the transmission and reception of the data, the process of data compression and aggregation becomes a primary component in design and optimization on these is an immediate need. Efficient data compression and aggregations not only provide energy conservation but also remove redundancies in the data. The major objective of this paper is to present and compare the data aggregation and data compression algorithms in various network topologies proposed for WSN applications. It is clear from the tables that there is no clear winner, and the algorithms are to be chosen depending on the application.

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Spectrum Allocation Policies in Flexi-Grid Optical Networks M. B. Sumalatha, L. M. Aishwarya and C. L. Triveni

Abstract Challenges while designing algorithms in fixed WDM are easier than the flexible optical networks. The major challenges in flexible optical networks are in related with physical layer, routing, spectrum allocation (RSA) and dynamic traffic fluctuations. Spectrum allocation policies are used to minimize the cost of transponder and also to utilize spectrum efficiently. Spectrum allocation policies such as constant spectrum allocation (CSA), dynamic high expansion–low contraction (DHL) and dynamic alternate direction (DAD) used to avoid wastage of bandwidth. For these policies, blocking probability, cost of transponders and regenerators required are calculated using MATLAB software. Keywords RSA · CSA · DHL · DAD

1 Introduction Maximizing the efficiency of the transport network and increasing the capacity of optical networks is a major research challenge. Annual increase of the capacity requirement is more than 30%. WDM systems are aiming higher rates and improved distance transmission. However, the use of rigid, resulting in in-efficient of WDM potential sensitivity of the system, the deployment of a much higher rate than the channel as in Ref. [1].

M. B. Sumalatha (B) · L. M. Aishwarya · C. L. Triveni Department of ECE, Malnad College of Engineering, Hassan, Karnataka, India e-mail: [email protected] L. M. Aishwarya e-mail: [email protected] C. L. Triveni e-mail: [email protected] © Springer Nature Singapore Pte Ltd. 2020 S. Kalya et al. (eds.), Advances in Communication, Signal Processing, VLSI, and Embedded Systems, Lecture Notes in Electrical Engineering 614, https://doi.org/10.1007/978-981-15-0626-0_15

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Due to the rapid growth of the Internet content provider, traffic on contributing to increased uncertainty due to changing models has changed significantly. The simple on–off modulation techniques support bit rates up to 10 Gbps. More complex modulation schemes are used for the bit rates above 100 Gbps as in Ref. [2]. The efficient transmission of optical spectrum beyond 400 Gbps bit rate and modulation to accommodate the optical transmission spectrum efficiency can be achieved through advanced DSP. The technological options including type of modulation, baud rate, number of sub-carriers and bandwidth. Dynamic operation for spectrum allocation spectrum requires transceivers supporting defragmentation as in Ref. [5]. Rigid fixed-frequency division multiplexing (WDM) optical networks will no longer be an effective way to emerging and high dynamic bandwidth hungry maintained. The basic limit is approaching the available spectrum will be occupied by the optical fibre, the research community focus on seeking a more efficient use of available bandwidth and the most advanced optical transport network solutions as in Ref. [7]. Traffic matrix configuration and physical layer are feasible for given transponder in a flexible optical network problem to use or consider the problem either to form a regeneration. With respect to one or more of the requirements of the transmission, configuration is selected. Depending on the demands, transmission is divided into more than one path and using repeaters, if needed as in Ref. [3]. Spectral efficiency in fixed-grid optical network is limited due to inflexible nature of wavelength assignment. Flexi-grid optical network allocates spectrum resources dynamically in order to eliminate restrictions to channels with respect to fixed WDM optical networks as in Ref. [4]. In order to meet future network technology, optical transmission needs better efficiency, elasticity and scalability. Flexi-grid optical network is the promise technology for upcoming high-speed applications. Flexi-grid technology allocates bandwidth according to the requirement of clients. As a result, greatly improving the efficiency of the network has been improved in comparison with fixed DWDM optical networks as in Ref. [8]. The traffic serving in flexible optical network is a major problem because the rate of transmission is dynamically varying with time. Using routing and spectrum allocation algorithm (RSA), route utilizes spectrum around reference frequency and allows to match fluctuations with source rate as in Ref. [6].

2 Flexible Optical Networks The highly dynamic and high bandwidth application-oriented technology required over fixed WDM networks. Traditional fixed WDM networks have static connections and fixed bit rates, i.e. 10, 40 and 100 Gbps. Fixed modulation techniques are differential shift keying and quadrature phase shift keying. The channel-to-channel distance in these modulation formats is 50 GHz.

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Flexible switches and transponders are required for dynamic operation in flexigrid networks. In case of conventional fixed WDM network, the algorithm planning becomes simpler. These considerations set the best time which is defined as the overall network design to reduce costs and network outages. The energy efficiency of the network is maximized in order to fulfil the requirement of competition in the market.

2.1 Spectrum Defragmentation The technology that restores efficient resource utilization by reallocating the fragmented slots in the optical wavelength to more continuous ones for large-capacity communication is called ‘wavelength defragmentation’. The defragmentation is effectively used particularly when optical signal paths are concentrated on a specific section of a mesh network. When some optical paths are forced to make an unnecessarily long detour to avoid congestion and reconfiguration into optimum optical routes can be achieved by reallocating the routes so that they use the vacant slots generated by the disappearance of services using part of an optical path that transits the congested section. This kind of defragmentation is feasible even with the conventional optical network as long as there is an optical switch node that can be controlled by software.

2.2 Off-Line and Online Approaches Dynamic network scheduling approaches are applicable to connections which are dynamic in nature. Static network scheduling approaches applicable to off-line network issues. The method used for the final classification, including network planning. Integer linear programming and mixed integer linear programming mathematical optimization methods can be implemented. They offer benefit of providing relief from these techniques, measure of optimality. However, they may result in high computational complexity. In the dynamic environment, computational problem is a restricting issue. In order to reduce computation time, optimization should be sacrificed.

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2.3 Routing and Spectrum Allocation Routing and wavelength assignment problem is defined as problem of establishing connections in fixed WDM networks. RWA problem is also called NP-complete. Establishment of connections in flexi-grid network is much more complex for several reasons. First, each link is assigned to a single wavelength and spectrum slots combined to form an uneven width channels ensuing in routing and spectrum allocation problem. Breaking the transmission into more than one path to choose and give them the rate of supply of spectrum allocation are based on request rates, and regenerators are placed if needed. The purpose of the RSA algorithm is to serve the traffic with respect to the spectrum usage and transponders expenditure.

3 Spectrum Allocation Policies In order to make dynamic shared spectrum, we need spectral expansion or contraction (SEC) policy. When requested rate exceeds the transponder capability, spectrum allocation policies becomes more useful. In order to manage dynamic traffic in flexi-grid optical networks, spectrum expansion and contraction policies are used for different requested channel rates. Spectrum allocation is done through two ways. Firstly, each link is assigned a path and allocates a reference frequency over that path and use suitable routing and spectrum allocation algorithm techniques. Secondly, spectrum should utilize around reference frequency and matches requested rate fluctuations. Spectrum expansion is nothing but allocating spectrum to its upper slots depending on requested rates, wherein spectrum contraction is defined as spectrum allocation to the lower slots when upper slots are fully filled over a reference frequency. Some of the spectrum expansion and contraction policies to provide time-varying traffic are:

3.1 Constant Spectrum Allocation (CSA) Policy In case of constant spectrum allocation policy, total spectrum is divided into equal number of slots. It never shares it sub-slots with other connections. It is basic for other spectrum allocation policies.

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Suppose an optical fibre having transmission capacity of 400 GHz. This capacity is divided into eight slots. Each slot is carrying the capacity of 50 GHz. Each slot consists of eight sub-carriers. Each sub-carrier is carrying 6.25 GHz. If the demand is 4 units, only four sub-carriers are used, and remaining four sub-carriers are wasted. These remaining four sub-carriers act as blocking frequencies.

3.2 Dynamic High Expansion–Low Contraction (DHL) Policy In case of DHL policy, the requested transmission rate uses upper and lower spectrum slots. It uses adjacent upper spectrum slots first and next uses lower adjacent spectrum until demand is reached. It is the modification of constant spectrum allocation policy. For example, if the demand is 10 units, the complete slot uses eight sub-carriers. But the remaining 2 units are shared with adjacent higher spectrum first. If the upper spectrum is already filled, it uses lower spectrum. If both adjacent slots are already filled, blocking occurs.

3.3 Dynamic Alternate Direction (DAD) Policy It is modification of dynamic high expansion-low contraction policy. It uses both adjacent higher and lower slots with reference frequencies. It fills both higher and lower spectrum symmetrically. Once the upper or lower spectrum is fully filled, then it takes either of the spectrum whichever becomes free.

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3.5 Algorithm for Proposed Policies Step 1 Step 2 Step 3

Choose the network. (6 mesh node network or 14 node one). Assign connectivity matrix based on the choice in Step 1. Identify the x-y axes values for the network’s node positions, and plot the node deployed graph as represent of actual cities or node locations. Step 4 Update the distance matrix. In case geographical distance between the two nodes is not given, Euclidian formula is used. Step 5 Assign the channel physical parameters: maximum spectrum for the operation, sub-carrier spectrum or frequency, number of slots in the total spectrum, hence number of sub-carrier per slots and central frequency or subcarrier. Step 6 For source and destination pair, find possible shortest routes. Step 7 Find out the reach and associated number of regenerators required for each path to carry data from source to destination. Step 8 For three types of spectrum allocation CSA, DHL and DAD. For each pair allocate demand by updating the sub-carriers of each slot over the links that are chosen by the path in Step 6. Step 9 In each allocation, keep track of number of requests failed due to non availability of spectrum as per the allocation policy. Step 10 Calculate the probability of blocking in each case.

3.6 Technical Terms Associated with Spectrum Allocation Policies 3.6.1

Dijkstra’s Algorithm

Dijkstra’s algorithm is used to find shortest path between the nodes in the graph; it can represent the road network. It was invented in 1956 by a computer scientist Edsger W. Dijkstra. He published after three years. There are many variants who found Dijkstra’s algorithm. But mostly used is shortest path between two nodes. For example, the nodes of graph represent cities and costs are represented by the distances between source and destination pair. Dijkstra’s algorithm is used to find the shortest distance between one city and all other cities. The shortest path for any two nodes in a network using Dijkstra’s algorithm can be calculated by Minimum value = Min(Destvalue, Marked value + Edge value)

(3.1)

where ‘Destvalue’ is the value of destination vertex ‘Marked value’ is the value of source vertex ‘Edge value’ is the weight of edge that connects source and destination vertex.

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Euclidean Distance Formula

In mathematics, Euclidean distance or Euclidean metric is distance between two points in Euclidean space. Consider, a point connecting straight lines P(x1, y1) and Q(x2, y2). Distance between P and Q is given by PQ =

3.6.3



(x2 − x1 )2 + (y2 − y1 )2

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Erlang Traffic

The Erlang (symbol E) is a measuring unit used in telecommunications. It is a dimensionless unit. It is used to measure load offered by the telephone switching equipment. In other words, it is used to measure traffic occurred in communications. Offered traffic in Erlang (E) is given by E = λh

(3.3)

where ‘λ’ is the call arrival rate and ‘h’ is the average call-holding time.

3.6.4

Poisson’s Distribution Formula

The requested channel rates are calculated by Poisson’s distribution formula. It is a discrete probability distribution that shows the probability of a given events occurring in a fixed interval of time with knowing mean time and independent of the time since last event. The probability of observing ‘k’ events is given by P( k  events in an interval) = (λk e−λ )/k!

(3.4)

where ‘λ’ is average number of events, ‘e’ is Euler’s number, e = 2.71828. ‘k’ is number which takes values 0, 1, 2, …etc.

4 Results and Discussion The algorithms are implemented using MATLAB, and simulations are carried for various inputs. The six-node network has 18 connections or edges (bidirectional), and the distances are calculated using Euclidian formula, which is used for shortest path calculation and hence modify the Dijkstra’s algorithm to calculate multiple routes.

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The 14-node network has 42 connections. Each network is thought to possess a maximum spectrum = 400 GHz, each sub-carrier uses bandwidth of 6.25 GHz, and each slot supports eight such sub-carriers. The traffic is modelled to follow Poisson’s distribution. The number of requests is limited; hence, all the pairs of sources and destinations are not covered during an execution; hence, the exact results may vary numerically from one execution to other; however, the pattern remains, mostly the same. An Erlang is the demand that uses a sub-carrier for the entire time. As the demand increases, the usage of sub-carriers increases accordingly, but that is not the only case when the need for more spectrum arises. It is also observed that the rate of the service is dependent on the spectrum usage directly. Hence, if the request has a higher demand as well higher rate, utilize the more of the spectrum. Physical property-related results are direct implications of the cost. However, the quality of service is also equally important. Presently two spectrum allocation methods are analysed here those are CSA = constant spectrum allocation, DHL = dynamic high extension and low contraction method and DAD = dynamic alternate direction, a minute variation in performance also is a highly preferred result when large size of data (very large) is being transported over the optical cable. The results of two different networks are as follows. Figure 4.1 Depict the blocking probabilities of the two networks using three different spectrum allocation methods. It is quite clear that for a low traffic, the blocking in six-node networks is comparatively high; however, the important aspect in both the cases is that the DHL outperforms CSA in both the networks’ quality of service-wise. DAD performs better than DHL and CSA. However, it comes with

Fig. 4.1 Blocking probability of six-node network performance

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Fig. 4.2 Blocking probability for 14 node with 10 Gbps rate

the cost that we have to defragment the slots and allocate the sub-carriers for certain demand to be satisfied across the slots. We can also change the required rate, that is 10 Gbps to 40 100 and 400, and check the variation in the blocking probability. Following are some of the results obtained by doing so. The channel spectrum taken is 1200 GHz. Figure 4.2 gives the blocking probability for 10 Gbps for the three allocation policies we have considered. The network chosen is a 14-node network. DAD offers lower blocking probability. Hence, this is the better suited for 10 Gbps rate of transmission. In Fig. 4.3, we have the blocking probability for 40 Gbps for the three allocation policies so far. The network chosen is a 14-node network for all possible combinations of OD pairs. Here also DAD offers lower blocking probability. Hence, this is the better suited for 40 Gbps rate of transmission. As there can be multiple routes for satisfying a demand, the cost depends on the reach and hence the number of regenerators required for the purpose. The first route is the shortest, and second is the next which takes longer route distance and so on. Considering the first three disjoint routes and their reach distances, we get the results in Fig. 4.4. As we can see that route 1 has the smallest number of regenerators, but it comes at blocking cost. The cost is almost doubled for every next route chosen. We know that there are four standard transponders with rates 10, 40 and 100 Gbps. Looking at the transmission tuple, we get that as the rate increased, the signal strength is decreased at shorter distances, and hence, more regenerators may be required. Figure 4.5 shows us exactly see how the variation goes on. This is open secret that 400 Gbps rate requires maximum regenerators.

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Fig. 4.3 Blocking probability for 14 node with 40 Gbps rate

Fig. 4.4 Route-regenerator requirements for multiple paths

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Fig. 4.5 Rate-regenerators requirements for shortest route

5 Conclusion A 6–14 node NSFNET networks are devised, to each of them between OD pairs the reach is calculated and accordingly number of regenerators required is estimated, also for different rate and demands the cost is calculated assuming on 10 Gbps as standard. The blocking probability analysis for CSA, DHL and DAD is plot, and the results show that the DAD is better performer when a bit of extra cost is not an issue as quality is. The complexity and time consumption for DAD are very high. The cost in terms of number of regenerators is estimated for different routes chosen for allocation and also for the various transmission rates that can be used for now. Future work: We can defragment more than two adjacent slots to fit in the requirements until a limit is reached in the spectrum where the slots are already occupied by other requests. That will result in fewer complications in algorithm compared to DAD, but performance will be better DHL. By what margin is it better and is it worth sacrificing the fragments can be answered.

References 1. Varvarigos EA, Christodoulopoulos K (2014) Algorithmic challenges in flexible optical networks. In: International conference on computing, networking and communications (ICNC). Invited paper

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2. Gerstel O et al (2012) Elastic optical networking: a new dawn for the optical layer? IEEE Commun Mag 50(2) 3. Christodoulopoulos K, Soumplis P, Varvarigos E (2013) Planning flexigrid optical networks under physical layer constraints. J Opt Commun Netw 4. Patel AN, Ji PN, Jue JP, Wang T (2012) Routing, wavelength assignment and spectrum allocation algorithms in transparent flexible optical WDM networks. Opt Switch Netw 9(3) 5. Autenrieth A et al (2013) Evaluation of technology options for software-defined transceivers in fixed WDM grid versus flexible WDM grid optical transport networks. Photon Netw Symp 6. Christodoulopoulos K, Tomkos I, Varvarigos E (2013) Time-varying spectrum allocation policies and blocking analysis in flexible optical networks. J Select Areas Commun 31(1) 7. Tomkos I, Azodolmolky S, Sole-Pareta J, Careglio D, Palkopoulou E, A tutorial on the flexible optical networking paradigm: state of the art, trends, and research challenges 8. Chatterjee BC, Sarma N, Oki E (2015) Routing and spectrum allocation in elastic optical networks: a tutorial. IEEE Commun Surv Tutor 17(3) 9. Shen G, Yang Q (2011) From coarse grid to mini-grid to grid-less: how much can grid-less help contention-less? OSA/OFC/NFOEC 10. Harish Kumara HB, Triveni CL (2016) De-fragmentation for spectrum allocation in a flexible optical networks. In: National conference on emerging trends in electronics and communication (NCETEC-16) on 3–4 May 2016 by Dept of ECE at BGSIT, Bellur, ISBN: 978-93-84698-12-6 (Published in ISRASE eXplore Digital Library)

Novel Approach in IoT-Based Smart Road with Traffic Decongestion Strategy for Smart Cities Padma Prasada, Sathisha and K. Shreya Prabhu

Abstract Real world needs to connect to its virtual world to enable anything with just a switch. Internet of things (IoT) makes it possible by interaction between people, objects, environment and virtual data involved with them. The increase in a number of vehicles on road, accidents and delay of emergency services calls for an effective solution, i.e., smart roads. To make effective smart roads within smart cities, it is necessary to employ advanced technology to handle the issues related to normal roads by collecting all the data related to it, process and analyze it and find an alternate solution to it within a small fraction of time. Video monitoring and surveillance are widely used but require personnel to monitor the situation and analyze it followed by an appropriate decision which is not recommended for real-time situation. Road traffic density information is an important parameter that can be exploited in avoiding traffic congestion. This paper proposes an alternative solution in real-time world where different sensors from roadside unit (RSU) capture traffic congestion information based on the vehicle crossing over the given span of time, transmit to base station where it is collected and perform big data analytics. This information is made available to the user via custom-designed Android application, keeping the user updated with the present scenario of the road he/she shall take. Keywords Smart city · Smart road · RSU · Traffic decongestion · Android

P. Prasada · Sathisha (B) · K. Shreya Prabhu Department of ECE, MITE, Mangalore, India e-mail: [email protected] P. Prasada e-mail: [email protected] K. Shreya Prabhu e-mail: [email protected] © Springer Nature Singapore Pte Ltd. 2020 S. Kalya et al. (eds.), Advances in Communication, Signal Processing, VLSI, and Embedded Systems, Lecture Notes in Electrical Engineering 614, https://doi.org/10.1007/978-981-15-0626-0_16

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1 Introduction Increased traffic density calls for an immediate improvement in fuel efficiency, reduced congestions, non-accident-prone travel and improving driving experience. Traffic controlling and traffic congestion have always been a big concern on Indian roads. Extensive study on the field of traffic flow theory includes road capacity planning and estimating average commute times. Data involved in this analysis is large, and the time consumed is enormous. Ability to detect traffic scenario in advance could provide quick solution. In general, there is a need for Smart Transportation System (STS) for smart mobility. Smart roads should exist that integrates real-life data with high fidelity simulations of the system and its networks. High fidelity is an important parameter as slightest faults such as mis-timed traffic lights or wrong data regarding the roads ahead might add up to already congested roads or may even lead to accidents. Smart roads could save lives by reducing accidents, could reduce fuel cost and losses in turn improving economic benefits and could provide business opportunities that include transportation, construction, manufacturing, data analytics and electronics. Traffic density could be considered as key factor for effective traffic management as it is available in real time. Time estimation and recommendation of alternative routes with less traffic using real-time traffic density information could help in the case of emergencies. During accidents, reference information barely changes, in turn helping the investigating authorities in understanding the cause of accidents. This could help in taking necessary measures at those places to avoid further accidents. This could help in implementing traffic law enforcements. There already exist various vehicles detecting technique involving video traffic surveillance [4], radar, infrared, ultrasonic and microwave detectors. But these are not recommended due to disadvantages of high cost, inaccuracy and inadequate capacity, difficulties in installation, maintenance and implementation. Cheaper techniques involve systems with combination of sensors and IoT. Real world needs to connect to its virtual world to enable anything with just a switch. Connecting giants of components forming a network forms IoT which involves people–people, people–things or things–things. Devices will be able to communicate without a human involved by merging digital world with physical world. There are around 8.4 billion IoT devices in use in 2017, and the number will increase rapidly in coming years. Analyst, IDC, has analyzed that IoT will be implemented in three major industries, manufacturing, transportation and utilities. Implementing IoT technology in creating Smart Transportation Systems can provide the solution for effective traffic management. User needs to have an android application that gives real-time information on all possible routes to the destination, routes that have traffic congestion at that particular time period or any other emergency scenarios like accidents, road construction issues or vehicle breakdowns before the user enters the road. Traffic congestion information is captured by onboard sensors and Wi-Fi systems. Efficient sensors in roadside unit (RSU) detect the vehicles and keep a count of vehicles passing in unit period of time

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as it passes by. This data is passed onto the roadside systems. Data acquired from roadside systems is all the possible alternate routes that take him to the destination. This information may be displayed on car display and Android application with the help of Google Maps. Google Maps accessing technique will be used to represent different real-time traffic conditions on the live map. Depending upon the density of traffic, roads can be classified as heavily congested, lightly congested or average congested. On the other hand, while a vehicle enters the area, it gets paired with the Wi-Fi systems in that area. Some of the necessary information such as vehicle details and some other vital data will be recorded in the database. This also helps in tracking vehicles and checking their location in case of missing cases, theft or any other crime. The system uses the combination of the data from the sensors as well as Wi-Fi systems. This approach proposes a protocol that implements communication between two vehicles. Vehicle-to-vehicle (V2V) and vehicle-to-infrastructure (V2I) communications assist in reducing the traffic congestion by gathering vital information in advance. Achieving low latency in delivering emergency warnings in any condition is addressed in this paper.

2 Related Work Magnetic sensor nodes in cat’s eye placed at roadside exchange information about cars passing them by their magnetometers between them to establish an ad hoc network. This can also be utilized in assisting drivers when they trying to overtake a vehicle and be informed about the vehicles coming from opposite direction [1]. Djahel et al. [2] considering three levels of emergency scenarios, adaptive TMS is proposed. When traffic service request for emergency is received, its authenticity is checked and then changes in necessary traffic policies are implemented. In cases of medium- and low-level condition of emergency, only the traffic lights and rerouting are suggested. This is designed using a set of controllers, sensors and connected vehicle system. Velocity information is collected from a single vehicle from GPS, and machine learning analysis is performed on the data. This implementation does not involve any central server; communication is not required during detection; hence, no privacy or security issues are involved [3]. SDN method can be implemented in three ways to vehicular networks [4]. Centralized coordinators are in the form of independent fog devices in one method, in second logically centralized coordinator is implemented by interconnection of many fog devices, and in third, cloud itself serves as main centralized coordinator. Maximum Boolean derivative on graphics triangular accumulation and lines of motion is designed to control a smart traffic light in a CTMS infrastructure. This also generates control signals based on opinion polls, social media data, etc. [5].

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Capabilities of TMS should also include security and safety issues, and nation’s economic growth. This can be achieved by implementing WSNs, M2M communication, mobile sensing and social media. Comparison of existing approaches toward traffic prediction based on parameters like accuracy, scalability, parametric, data source constraints, privacy and security issues gives clear overview of pros and cons of each of the existing technologies [6]. Fog computing platforms comprising of virtual sensing zones, access zones, M2M gateways and cloud system are applied to attain location awareness, enabling high mobility through V2V and V2I interactions [7]. To overcome issues with interoperability between different standards, protocols and systems in IoT-based TMS, software agents are used for designing distributed online traffic simulation framework [8]. Using embedded PCs, controlling the traffic lights dynamically through Web IOPI REST API is proposed using Raspberry Pi [9]. Based on the speed of vehicles between two points, the density of vehicles on that road is calculated. If the road is more congested, vehicle movement will be comparatively slower than when it is less congested [10]. Based on this notion, wider roads can be planned at places where congestion is high. Similarly, roads that connect to lesser number of houses are designed to have lesser lanes. Sensors can be used to capture the congestion level at a point at different times of the day. During peak hours, users can be suggested to divert to roads that are less congested, hence saving time of travel, pollution, fuel intake.

3 Methodology and Implementation Results The principal plan is to deploy ultrasonic and wireless sensor modules organized on roadside units. The traffic condition will be recognized, processed by deployed computing machine, and then generated summary is transmitted to a Traffic Management Centre (TMC) for collation and computation of multi-site statistics such as link travel times. Proposed concept is illustrated in Fig. 1. Real-time representation of the same

Fig. 1 Concept for traffic surveillance [1]

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Fig. 2 Representation of RSU model

is depicted in Fig. 2. In this approach, the roadside unit captures the signals from onboard sensors as well as Wi-Fi systems proposed in the vehicles. This information will be processed and will be sent to the Traffic Management Centre (TMC). Processing occurs in four stages: A. Optical flow segmentation (very slow traffic) or background image differencing (normal traffic conditions) used to detect and group blobs tied to individual vehicles as they come into the field of view. At this stage, a bounding box can be fitted to the blob to estimate shape parameters for vehicle classification. B. Tracing each moving vehicle for performing improvise and localization and speed in 3D world coordinates, as well as the shape parameters as long as it remains in tracking zone of the unit. C. Cognitive information from the tracked data in order to deduce local traffic density parameters such as vehicle counts per lane, average speeds, incidents and lane change frequencies. These parameters, together with track information (time stamp, vehicle type, color, shape, X-Y position), are transmitted to the TMC at regular time periods. D. Local traffic parameters from each roadside unit are collated and displayed in necessary format, and used to control signals, message displays, android applications and other traffic control devices. Computing machines at the TMC also have the capabilities to process the tracked information from its neighboring RSU and compute long-distance parameters such as link times and origin–destination counts. Real-time system for determining the traffic flow can be implemented using commercial sensor-based traffic surveillance systems, aiming at simplified techniques.

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The more significance is on recovering trajectories and models with high accuracy even for a small number of vehicles. Recognizing vehicles regardless of indefinite sensor data and weather conditions, tracing each vehicle in spite of overlapping with one another poses major challenges in designing and development of sensor-based surveillance methods. The significant reciprocation in the design of such a system, as expected of most real-time computer vision, is the trade-off between accuracy and speed. More computations are expected for higher robust algorithms; nevertheless, they will continue to provide good performance even in conditions such as shadows, dense traffic and day-to-night transitions when the naive algorithms tend to fail. The software part of this approach includes the design of a customized Android application, developed on Android Studio platform. The application receives the input signals from the hardware systems deployed on the roadside and gives the specific output information through Google Maps. To register to become member of this proposed system, one has to click on REGISTER button, this will start the service, and as per our programming in StartCommand() method, a registration window will appear on the bottom of the simulator as shown in Fig. 3. In the case of traffic decongestion, the hardware unit will be sending the message to the Android application via Bluetooth which is labeled as “Route A” and the application will suggest the regular route to the user which is colored blue. In the case of traffic congestion, the hardware unit will be sending the message to the Android application via Bluetooth which is labeled as “Route B” and the application will suggest the alternate route to the user which is colored blue. The Fig. 3 Registration window

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Fig. 4 Suggesting alternate routes in case of traffic congestion

color of the regular route which was suggested in the previous case will turn to red indicating that the route is congested. The outlook of the application when the regular route is congested is shown in Fig. 4. Road traffic congestions impact an important economical and productivity loss in the countries’ growth, as well as getting larger environmental impact. High deployment costs and limited coverage are the major limitations we found in typical sensorbased solutions to detect traffic density, such as surveillance cameras and road surface inductive loops. The proposed system is expected to solve these problems faced in conventional system with minimal modification to the existing systems.

4 Conclusions Road traffic congestions cause an important economical and productivity loss, as well as an expanded environmental impact. Ordinary sensor-based solutions to identify traffic density, such as supervision cameras and road surface inductive loops, have the restraint of high deployment costs and limited coverage. We propose a novel approach to address this by making use of the efficient sensors to get the accurate information about traffic congestion and road condition; it provides on-demand realtime alternate shortest route navigation facility as well. Developing an app that works on Android, which is the most used operating system in smartphones, can be useful for many users. If traffic information is given to users at right time without delay, users can choose the alternate route without entering the congested road and reach destination on time, hence saving time and

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fuel and reducing inconvenience to fellow men. This method uses V2V, and V2I gives many advantages over conventional infrastructure-based solutions in detecting traffic congestions.

References 1. Karpi´nski M, Senart A, Cahill V (2006) Sensor networks for smart roads. In: Proceedings of the fourth annual IEEE international conference on pervasive computing and communications workshops 2. Djahel S, Salehie M et al (2013) Adaptive traffic management for secure and efficient emergency services in smart cities. IEEE, pp 340–343 3. Wang C, Tsai HM (2013) Detecting urban traffic congestion with single ve-hicle. International conference on connected vehicles and expo, pp 233–240 4. Stojmenovic I (2014) Fog computing: a cloud to the ground support for smart things and machine-to-machine networks. Australasian telecommunication networks and applications conference. IEEE, pp 118–122 5. Miz V, Hahanov V (2014) Smart traffic light in terms of the cognitive road traffic management system (CTMS) based on the Internet of things. IEEE, pp 120–126 6. Djahel S, Doolan R et al (2015) A communications-oriented perspective on traffic management systems for smart cities: challenges and innovative approaches. IEEE Commun Surv Tutor 17(1) 7. Al-Sakran HO (2015) Intelligent traffic information system based on integration of internet of things and agent technology. Int J Adv Comput Sci Appl 6(2) 8. Misbahuddin S, Zubairi JA et al (2015) IoT based dynamic road traffic man-agement for smart cities. IEEE, pp 142–146 9. White J, Thompson C, Turner H, Dougherty B, Schmidt DC (2011) WreckWatch: automatic traffic accident detection and notification with smartphones. Mob Netw Appl 16(3):285–303 10. Mazhar Rathore M et al (2016) Urban planning and building smart cities based on the internet of things using big data analytics. Comput Netw 101:63–80

Design and Development of Low-Cost Electronic Stethoscope Trainer Kit Sukshith Shetty and Sukeerth Kumar

Abstract Auscultation is the medical term for using a stethoscope to listen to the internal sounds of the body. Auscultation is performed on lungs, heart and abdomen of a patient during his/her medical tests. Auscultation has been a very important in examining the circulatory and respiratory systems as well as the gastrointestinal system (bowel sounds). Auscultation provides vital diagnostic clues and methodology for the early diagnosis of any cardiac abnormalities and respiratory disorders. Most heart diseases are associated with and reflected by the sounds that the heart produces. Traditional auscultation requires substantial clinical experience and good listening skills. The motive of this paper is to develop an electronic stethoscope trainer kit by using basic electronic components which can amplify the heartbeats of an individual with reduced background ambient noise, thereby producing a crystalclear heartbeat sound for hearing across the earphones. With the help of this device, multiple members can hear the auscultated heartbeats of an individual and analyze them. Results of this project indicate that very minimal amount of noise was present at the earphone end and the enhancement of the heartbeat sound was heard with great intensity. The project’s conclusion indicates that due to the non-complexity of the system, a non-medical profession can use this low-cost electronic stethoscope without any difficulty. Keywords Auscultate · Sallen-key · Chest piece · Zobel filter · AFO · DSO · Butterworth · Microphone

S. Shetty (B) · S. Kumar Department of Electronics and Communication, Nitte Mahalinga Adyanthaya Memorial Institute of Technology, Udupi, India e-mail: [email protected] S. Kumar e-mail: [email protected] © Springer Nature Singapore Pte Ltd. 2020 S. Kalya et al. (eds.), Advances in Communication, Signal Processing, VLSI, and Embedded Systems, Lecture Notes in Electrical Engineering 614, https://doi.org/10.1007/978-981-15-0626-0_17

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1 Introduction Stethoscope is a simple acoustic tool in the medical field that is used to listen to the internal sounds of a human body. It was invented by a French doctor named ReneTheophile-Hyacinthe Laennec in the year 1816 in Necker-Enfants Malades Hospital, Paris. His first stethoscope was a wooden tube similar to the ear horns. This tool was invented by Rene when he was treating a female patient and felt it awkward to use the traditional way of auscultation. For several years the traditional wooden tube stethoscope had undergone many changes through its way by other practitioners and inventors where they have replaced the rigid tube with flexible one. The next version of stethoscope was invented by Irish doctor Arthur Leared in which he attached the binaural ear tubes so that it would be comfortable for the user to listen to auscultated heartbeats [1]. The binaural stethoscope consists of earplugs, binaural pieces, flexible tubing, a stem and a chest piece. The chest piece of a stethoscope basically consists of a bell and diaphragm. The diaphragm is used to auscultate high-frequency heartbeats and the bell is used to hear low-frequency sounds like gallops, rumbles and murmurs. The diaphragm is a flat, metal disc that in turn contains a flat, plastic disc. The diaphragm is the larger component of the chest piece. The bell is a hollow, bell-shaped piece of metal with a tiny hole on top. The diaphragm or the bell of the stethoscope when placed on a individuals chest vibrates when sound waves travel through it from the body surface. The waves bounce and reflects off the inside walls of the rubber or plastic tube. This is called multiple reflection. These sounds in succession travel up the hollow metal earpieces and to the listener’s ears. Classic stethoscope used is not the most culminated device as they have few issues related to their use, one of them being not able to amplify the sounds of the auscultated heartbeats. This provides no amplification of internal body sounds for the listener. Another problem is that only one person at a time can hear through the ear pieces of the acoustic stethoscope. This could be problem for many members to analyze the individual’s heartbeat all at once. Sometimes, even the earpieces could be uncomfortable while listening [1–3]. Electronic stethoscopes overcome these problems by conversion of acoustic sound waves into electrical signals which can then be enhanced and processed for optimal listening. Electronic stethoscope produces powerful and crystal-clear amplification of heart sounds, respiratory sounds and faint murmurs and provides the listener to hear these sounds across the earphones or loud speakers, which is more comfortable and preferable compared to the earpieces. There is a provision for adjusting the volume of the sound heard across speaker/earphone. In spite of these improvements, the electronic stethoscope still has not been embraced by the medical community. The very reason for this is that the sounds heard by the listener through the earpieces are mixed with electronic noise, causing the sounds to be different than the one heard through the acoustic stethoscope because electronic stethoscopes are very sensitive to ambient noise and noise generated internally in the circuit will overpower the sounds of the heart and lungs. Also, electronic stethoscopes are quite expensive as compared

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to acoustic stethoscope. The major goal of this paper is to fix many of the problems in currently marketed electronic stethoscopes and to make it more economical [4, 5]. The rest of the paper is organized as follows: Sect. 2 highlights the system overview with the working and essential information related to the design. Section 3 presents the results and discussion of the project output followed by the future work and conclusions in Sects. 4 and 5, respectively.

2 Methodology 2.1 System Overview and Working The entire device makes use of two 9 V battery source. One 9 V source is used as a positive supply and another is used as a negative supply for powering the opamps IC’s. The negative terminal of the first source and the positive terminal of the second source is shorted and made common (ground) for the entire circuit. The design basically consists of four main stages. The IC used in first three stages is TL072. TL072 is a low noise JFET op-amp. The IC used in the fourth stage of this device is LM386 power audio amplifier.

2.2 Difference Amplifier Stage Two electret condenser microphones are given at the input of the difference amplifier. To power the microphone a minimum of 2 V and max current of 0.5 mA is required. The microphones are powered through the same 9 V battery through a 5 V regulator (LM7805). Two 10 k pullup resistors are connected to both the microphone’s V cc pins to limit the current flow to 0.5 mA or less. Depending on the datasheet of the microphone, any value of current more than 0.5 mA can saturate the microphone and microphone basically stops responding to any input signal [6]. The first microphone is inserted into the stethoscope chest piece through the tubing of the stethoscope and the second microphone is kept open to the surrounding noise. As the chest piece is quite sensitive, it absorbs most of the background ambient sounds. The output from both microphones is passed through two different coupling capacitors of 10 µF to remove any DC component present in the output signal. The two outputs from the capacitors are fed into the non-inverting and inverting terminal of the op-amp (TL072) through the two resistors of 2.2 k forming a difference amplifier with initial gain of one. A resistor of 2.2 k is placed across the output pin and inverting terminal of the op-amp and another 2.2 k resistor is grounded from the non-inverting input terminal to minimize the input-bias current. The amplifier is used in negative feedback configuration. The difference amplifier stage eliminates any common noise present. The main aim behind this difference amplifier stage is

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to remove any background ambient noise. The output from the difference amplifier is fed to the pre-amplifier stage.

2.3 Pre-amplifier Stage The pre-amplifier amplifies the output signal from the difference amplifier stage. This stage is used because the output signal from the condenser microphone is very low in terms of millivolts (5–15 mV range). The power amplifier used in this device requires a minimum of 100 mV (0.1 V) at its input to significantly amplify the signal so that the required power is met to reach the earphones such that the listener can hear to the heartbeats very loud and clear. The output from the difference amplifier is given to the inverting input terminal of the op-amp TL072. The amplifier is used in negative feedback configuration. The required gain of 45 is set by placing a resistor of 100 k (feedback resistor) across the inverting pin and output pin of the op-amp and 2.2 k resistor from inverting input terminal to the ground. A 2.2 k resistor is used across the non-inverting input terminal of the op-amp and ground to minimize input-bias current. The amplified output signal from the pre-amplifier stage is passed on to the next stage of second-order low-pass filters [6, 7].

2.4 Second-Order Low-Pass Filter Stage The low-pass filter stage is required to attenuate any signal frequency above the desired cut-off frequency. This is because heartbeat’s sound frequency falls within the range of 20–250 Hz and any frequency above this range should not be allowed to pass through the circuit. The filter used in this device is an active low-pass secondorder Butterworth filter. It is formed by using two stages of RC filter coupled with an op-amp (TL072). A simple passive RC low-pass filter is formed by connecting a single resistor with a single capacitor. An active filter is formed by coupling the passive filter with an op-amp to avoid any loading problems with the source or the load. Second-order filter is formed by using two RC filter sections in cascade given to the input of the op-amp’s non-inverting input terminal. A feedback capacitor from the op-amp’s output terminal is formed with the first stage of RC filter. This feedback is given to ensure that the filter to provide stability. The resistor and the capacitor are the frequency selective components of a filter. To provide a cut-off frequency of 150 Hz, a resistor value of 1 k and capacitor of 1 µF is used [8]. Cut-off frequency (f ) of second-order Butterworth filter, taking R1 = R2 = R and C1 = C2 = C: f =

1 2π RC

(1)

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where f is the frequency in Hertz. To make an active filter work as Butterworth filter, Butterworth equations need to be followed and implemented. For a second-order filter, the required gain for forming the Butterworth filter is about 1.586. To provide this gain in the filter circuit, a negative feedback gain configuration of resistors is used. A resistor value of 33 k is given from the output terminal of the op-amp to its inverting input terminal and a resistor of 56 k is used across inverting input terminal to ground. This combination of resistors gives a gain of about 1.586 to the filter circuit. The output signal from the filter circuit is given to the power amplifier stage through a volume control potentiometer. The potentiometer used in this device is a PRESET Pot of 10 k. The potentiometer, in general, has three terminals, two fixed terminals and one variable terminal. The output signal from the filter is connected to one of the fixed terminals of the potentiometer and another fixed end of the potentiometer is grounded. The variable terminal is connected to the input of the power amplifier stage. This setup of the potentiometer basically behaves as a volume control knob which can be used to adjust the amount of signal entering the power amplifier IC.

2.5 Audio Power Amplifier Stage The output signal from the volume control knob is given to the input of the noninverting input pin of the audio amplifier IC (LM386) through a coupling capacitor of 0.01 µF to remove any DC component present in the signal. LM386 is a low voltage audio amplifier IC whose maximum output power of is about 1 W which is enough to drive headphones or earphones of 1 W rating. The internal architecture of LM386 is as shown in Fig. 1. The inverting input pin of LM386 is connected to the ground terminal. A bypass capacitor can be connected to the bypass pin of LM386 if required. Bypass capacitor is used to remove any AC interference noise if present. The power supply used for this IC is the same 9 V battery. A capacitor of 470 pF is placed across the non-inverting input terminal and ground to remove any radio frequency interferences and a capacitor of 0.1 µF is placed across the V cc pin and ground pin of LM386 to decouple any noise entering the IC. The internal minimum gain for the power amplifier IC is set to 20. The gain can be varied by placing a combination of capacitor and resistor in series across the gain pins of the IC. The maximum gain that can be achieved by LM386 is about 200 by placing only a capacitor of 10 µF across the gain pins [9]. The internal minimum gain for the power amplifier IC is set to 20. The gain can be varied by placing a combination of capacitor and resistor in series across the gain pins of the IC. The maximum gain that can be achieved by LM386 is about 200 by placing only a capacitor of 10 µF across the gain pins. The output amplified signal from the IC LM386 is passed through a parallel combination of Zobel filter. In this device, the Zobel filter is formed by connecting a capacitor of 0.047 µF and resistor of 10  in series and connecting the capacitor end to the output of the power amplifier IC and shorting the resistor end to ground. It is a parallel circuit of series resistor

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Fig. 1 Interior schematic of LM386 IC

and capacitor with the load. A large value capacitor of 1000 µF is used in series with the output of LM386 to smoothen the flow of the signal and to make sure that no DC component is present in the output signal which can affect the load. At the output side, a 3.5 mm female audio jack socket is used. The audio jack has 5 pins out of which only 3 of extreme ends are used. The extreme right end pin is the tip, the left extreme end pin is the ring and center pin is the sleeve (ground). The output amplified signal from the LM386 is shorted to ring and tip pins of the audio jack. The sleeve pin is grounded. The headphones or the earphones are connected to this audio jack to listen to the heartbeats when the device is switched ON and the stethoscope is placed on the chest. Any headphones/earphones of rating 1 W, which is sensitive to low response range can be used. Calculation of gain for LM386 using external resistances:  Ref =

1 +

 + R4

(2)

Gain = (2 ∗ R8 /Ref ) + 1

(3)

1 R5

1 Rext

Decoupling capacitors are very significant in circuits which are prone to ambient interference and internally generated noise. To remove the noise, decoupling capacitors of both ceramic and electrolytic type are used in this device. Ceramic capacitors being of low value are used to shunt noises of high frequencies and electrolytic capacitors being of high value are used to shunt noises of low frequencies. Decoupling capacitors are most operational when used near V cc (positive and negative) pins of the IC. In this device, ceramic capacitors of 0.1 µF and electrolytic capacitors of

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10 µF are used across V cc pins of the IC and ground. Capacitors of 470 and 0.1 µF are used across both 9 V battery supply and common ground terminal to stabilize the power supply.

2.6 Requirement for Zobel Filter The main purpose to use Zobel filter is in linearization of the driver unit. Zobel networks are used to make the impedance of a loudspeaker present to its amplifier output appear as a steady resistance. It is always placed in parallel with a loudspeaker/earphone driver in order to neutralize the effects of the driver’s voice coil inductance. The impedance of a loudspeaker is partly resistive. Because a speaker’s voice coil is itself an inductor, the impedance of the driver increases with frequency. Zobel can be used to restore the impedance of the driver to the nominal value in the high-frequency range. This is beneficial to the amplifier performance [9].

3 Discussion and Results The overall block diagram of the work is as shown in Fig. 2. The designed electronic stethoscope was tested on the authors of this paper and crystal-clear heartbeats were heard through the earphones with well amplification. Minimal noise and distortion were witnessed as expected. More amplification can be achieved by placing a 10 µF capacitor across the gain pins of the power amplifier IC (LM386). Instead of using maximum gain, a gain of 50 by LM386 did a great job. To implement a gain of 50 in LM386, a resistor of 1.2 k and 10 µF was used in series and connected across the gain pins. The output heartbeat sound heard through the earphones from this was recorded the best in comparison to others. The two-microphone system differential amplifier played a very crucial role in eliminating the ambient noise. Without the second microphone the circuit could detect the heartbeat, but the ambient noise overpowered the heartbeat sound, and this resulted in a very erratic sound across the earphones. Testing of each stage of the circuit was done with the help of an audio Fig. 2 Block diagram of electronic stethoscope

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frequency oscillator (AFO) and digital storage oscilloscope (DSO). A 0.01 V p-p sinusoidal signal of 50 Hz was given to the pre-amplifier stage input. The output voltage from the pre-amplifier was observed using the DSO. The output was 0.45 V p-p as expected. The filter stage was checked using the same method and the output from the filter stage was observed to be 0.7 V which was an expected value. To check the filter response, the frequency from the AFO was increased from 50 to 300 Hz in increasing steps of 10 Hz. The value of the output V p-p for each frequency was noted down and a frequency response graph was plotted and a 3 db cut-off was made in the graph. The frequency achieved was 140 Hz and which was very close to expected cut-off frequency. The output at the power amplifier was noticed and was observed that the power amplifier was expected to amplify the input signal by a gain of 20 but the gain provided by the power amplifier was nearly about 15–18. It was also observed that at the end of power amplifier output, there was quiet a small amount of DC component introduced which was expected to be negligible. The circuit was tested without the decoupling capacitors and was observed that internally generated noise and radio frequencies caused a disturbances at the earphone end and the listener was not able to hear the auscultated sounds clearly. It was observed that using LM386 audio amplifier IC, it is not possible to possible to get a clear heartbeat sound across the speakers whose minimum power ratings are 1 W and above as the maximum output power supplied by LM386 IC varies from 0.5 to 1 W. This power would be insufficient to drive the speakers and give a good bass for heartbeat sound as they are of low-frequency range. The final setup of the project is shown in Fig. 3.

Fig. 3 Final project prototype

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4 Future Work Future work is being done to refine our circuit by implementing wireless technology for transmission of the microphone signal using low-cost method to diagnose, analyze and to record the heartbeat signals so as to detect any kind of cardiac and respiratory problems a patient is suffering from by using techniques of signal processing with the help of a microcontroller and displaying the heartbeat signals on mobile phones through mobile-specific applications using Bluetooth connectivity.

5 Conclusions From the above study of the device, it was concluded that the designed low-cost (Rs. 1000, approx.) stethoscope trainer kit was functioning satisfactorily as expected. Due to absence of complex features, the designed device can also be handled by any nonmedical professionals and can also be used in home by individuals. An individual must see that while placing the stethoscope chest piece recommended auscultation areas will give the best results. The device can be improved by further implementation in PCB layout which would minimize the effect of noise. A higher-order filter could be used which will provide higher roll-off rate and more gain, but this would increase the device size and cost which contradicts the main aim of the device development. A voltage follower could be used at the output end so that the power transfer is maximum (current gain) as the output impedance of audio power amplifier is more compared to the load impedance (speaker/earphone). In order to hear the clear heartbeat sound through the speakers, a higher output power amplifier needs to be implemented. An instrumentation amplifier could be used in place of the difference amplifier to reduce more amount of noise. The designed circuit was not tested on any patients. Hereby, the main aim of the research was to obtain the amplified version of internal body sounds with less ambient noise and distortion which was achieved successfully. Acknowledgements We like to express our special thanks and gratitude to Dr. K. S. Shivapraksha, Associate Professor, and Mr. Anil Kumar Bhat, Assistant Professor, Nitte Mahalinga Adyanthaya Memorial Institute of Technology, Nitte, Karnataka for providing us all the help, support, ideas and the platform to design our system. We also appreciate all the support given by our lab assistants to make this project work successfully.

References 1. Fagbohun OO (2015) A versatile low-cost electronic stethoscope design 2. Jinothkumar S (2010) Digital stethoscope: a new approach to know and hear heart beat and heart frequency rate. J Adv Res Ideas Innov Technol 3(6)

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3. Jamar K, Scherer M, Weis T, Anderson M (2011) Electronic stethoscope, University of Wisconsin—Madison Department of Biomedical Engineering 4. Leng S, Tan RS, Chai KTC, Wang C, Ghista D, Zhon L Electronic stethoscope, 10 July 2015 5. Parmar Hardik R (2013) Design and development of a wireless electronic stethoscope using DSP 6. Gayakwad RA (2004) Op-amps and linear integrated circuits, PHI, 4th edn 7. Carter B, Mancini R (2017) Opamps for everyone, 5th edn 8. Radhakrishna Rao K (2010) Analog circuits and systems: active filters, NPTEL 9. Marshall Leach W Jr (2001) Introduction to electroacoustics and audio amplifier design, 2nd edn. Kendall/Hunt

Modified Hungarian User Pairing Method for NOMA-Based 5G Networks Tadepalli Sri Bala Ragni, Pigilam Swetha and V. P. Harigovindan

Abstract Non-Orthogonal Multiple Access (NOMA) technology is playing a key role in the improvement of network capacity for fifth generation networks. We consider a network model with one cell consisting of one base station serving 10 users as a set of five user pairs with power-domain NOMA. In this work, we have considered a 5G network with hybrid multiple access scheme, i.e. Orthogonal Multiple Access (OMA) and NOMA coexist. We have considered power-domain NOMA, and finding optimal pair of users is an inevitable part of power-domain NOMA. Hungarian method is already proposed for user pairing in power-domain NOMA. Even though Hungarian method provides optimal pair of users, the computational complexity is more for this method. So, we propose modified Hungarian method for finding optimal pair of users in NOMA. From the results, it is evident that the modified Hungarian method can achieve same performance as that of Hungarian method with reduced number of computations, making it a good candidate for user pairing in NOMA-based 5G networks. Keywords 5G · NOMA · Hybrid multiple access · Network capacity · User pairing · Pairing algorithms

1 Introduction Due to increasing demand for cellular and data services, there is a huge demand for improving the network capacity. The mobile traffic is estimated to be mostly due to T. S. B. Ragni (B) · P. Swetha · V. P. Harigovindan Department of Electronics and Communication Engineering, National Institute of Technology Puducherry, Karaikal 609609, India e-mail: [email protected] P. Swetha e-mail: [email protected] V. P. Harigovindan e-mail: [email protected] © Springer Nature Singapore Pte Ltd. 2020 S. Kalya et al. (eds.), Advances in Communication, Signal Processing, VLSI, and Embedded Systems, Lecture Notes in Electrical Engineering 614, https://doi.org/10.1007/978-981-15-0626-0_18

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video-related applications. The evolution path of the mobile communication standards is as follows: 1G standard (FDMA), 2G (TDMA), 3G (CDMA), 4G (OFDMA) and 5G (NOMA, millimetre wave communication, massive MIMO, etc.). The first four generation cellular standards use Orthogonal Multiple Access (OMA) technique where each user is served by one orthogonal resource block. Also, none of these techniques were found to meet the requirements of high spectral efficiency and massive connectivity and increased demand for services. This leads many researchers to take initiatives towards 5G technology which is summarised in [1]. Non-Orthogonal Multiple Access (NOMA) is a technology which has an important ability of good spectral efficiency [2]. In [3], authors studied about the allocation of resources and scheduling problem for downlink NOMA. NOMA has emerged as a solution to meet the above demands and has become an important candidate for fifth generation (5G) wireless networks due to its ability to provide high spectral efficiency, high data rate, high system capacity, massive device connectivity [4], compatibility and flexibility within the same resource block. In [5], authors provide an overview of the latest research and innovations as well as their applications. In NOMA, the same resource block can be shared by multiple users at a time. Power-domain NOMA is implemented by considering the allocation of different power coefficients to the users depending on their channel conditions in [6–10]. In [8, 10–12], authors provided techniques of Superposition Coding (SC) and Successive Interference Cancellation (SIC) to be used at transmitter and receiver, respectively, for transmission of data. With the utilisation of NOMA as a technology for improving spectral efficiency; capacity can be improved without increasing the available resources. Power-domain NOMA can be effectively implemented by finding the optimal pairs of users. Four user pairing algorithms namely the Hungarian, the Gale-Shapley, random pairing and the exhaustive pairing are considered and compared with one another in terms of network sum rate and sum-rate gain in [13]. Even though Hungarian method is an efficient optimisation technique, it is observed that the computational complexity and the number of computations required are more. Authors in [14] proposed a Modified Hungarian method which can achieve the same performance as that of Hungarian method with much reduced computational complexity. In this paper, we present a network in which hybrid multiple access is considered. That is, OMA and NOMA coexist in that cell. By using Hungarian and Modified Hungarian methods, we pair the users in order to improve the network capacity. We investigate the complexity difference involved in using the two user pairing algorithms by comparing the two. This is done by generating a cost matrix which consists of the costs of all the possible user pairs. In this paper, we have shown that the Hungarian method of user pairing is more complex than that of the modified Hungarian method. We have also compared the network sum-rate gain of OMA and NOMA. It is observed that the network sum-rate gain of about 13% over OMA is obtained using NOMA with user pairing.

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1.1 Concept of NOMA Unlike the conventional OMA techniques, multiple users can be served by the same resource block (time/frequency) in NOMA. Hence, it is known as Non-Orthogonal Multiple Access. Three types of NOMA namely power-domain NOMA, code domain NOMA and space domain NOMA exist. We use power-domain NOMA in this paper, which utilises power-domain for user multiplexing by allocating different powers to the users with different power allocation coefficients. To implement NOMA in a network, two techniques are used—Superposition Coding (SC) at the transmitter and Successive Interference Cancellation (SIC) at the receiver. In Superposition Coding (SC), in downlink NOMA, multiple users send data simultaneously, at different power levels, to a single base station. Power allocation is done to the users based on their channel conditions—farthest users with poor channel conditions are allocated high power coefficients, and the nearest users with better channel conditions are allocated with low power coefficients. Base station transmits these signals from different users as a single combined signal. The key idea of SIC is that the signals of users are decoded successively. Initially, the weakest user’s signal is decoded. It is then subtracted from the combined signal before the signal of next weak user is identified for decoding. It is to be noted that signal of each user is decoded by considering the other user’s signal as noise in signal reception.

1.2 NOMA—OMA Coexistence Implementing NOMA in 5G networks does not imply that it replaces OMA techniques those are used currently. Pertaining to the load on a user and his channel conditions, the system can decide whether to use OMA or NOMA. This leads to the coexistence of OMA and NOMA in a 5G system known as hybrid multiple access system.

2 NOMA Implementation 2.1 Data Rates NOMA provides higher data rate compared to that of OMA theoretically. Considering the fact that the nearest user (user 1) has better channel conditions than that of the farthest user (user 2), the power allocation coefficients are allocated accordingly in NOMA. The data rates of the nearest user and the farthest user are given by R1 and R2 , respectively, as shown below.

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For NOMA,  R1 = log2

P1 |h 1 |2 1+ N0,1

 R2 = log2 1 +



P2 |h 2 |2 P1 |h 2 |2 + N0,2

(1)  (2)

where R1 , R2 are the data rates of the nearest and the farthest users, respectively, N 0,i is the power spectral density of noise, P1 and P2 are the powers allocated to user 1 and user 2, respectively and |h1 |2 and |h2 |2 are the channel gains of user 1 and user 2, respectively. From the above equations, it is seen that the rates of the two users R1 and R2 vary with respect to the power allocation ratio P1 /P2 . For OMA,   P1 |h 1 |2 R1 = α log2 1 + α N0,1   P2 |h 2 |2 R2 = (1 − α) log2 1 + (1 − α)N0,2

(3) (4)

where α = bandwidth of user 1 and 1 − α = bandwidth of user 2.

2.2 Power Allocation In NOMA, the power allocation ratio directly affects the system performance. In power-domain multiplexing of NOMA, the power allocated to a user shows impact not only on the data rate of that user but also on the data rate of its paired user. The power allocation scheme to the users in power-domain NOMA is still an open research problem. In power-domain NOMA, there are two methods of power allocation in general— fixed power allocation and dynamic power allocation. Here, we use dynamic power allocation in which the power allocated to user 1 (user with higher channel gain) depends on the Signal to Noise Interference Ratio (SINR) of user 2. It changes dynamically based on the SINR of the second user as shown in (5) and (6). √ P1 =

1 + γ2 − 1 γ2

P2 = 1 − P1

(5) (6)

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2.3 Pairing of Users While pairing, the users are put into two groups, i.e. group A and group B in the scheduler. The users with good availability of resources will be selected by the scheduler. These users are kept in group A. Those users who require resources and are not already selected by the scheduler (in group A) will be kept in group B. The selection of group A users is called prescheduling. The users in these groups are randomly selected. The resources are allocated to the users according to the Eq. (7). An algorithm that is scheduled fairly is used for assigning resources. The priority of assignment of resources is decided based on the value X i (t) in (7). This means that the users with high X i (t) are given the highest priority to be assigned with resources. X i (t) =

ri (t) Si (t − 1)

(7)

where t is the subframe number, r i (t) is the target data rate of user i, and it varies with the application in which the user is involved, and S i (t − 1) is the experienced data rate of user i on an average and is calculated as  Si (t − 1) =

 t −1 ri (t) Si (t − 1) + t t

(8)

In this paper, we focus on the improvement in the network capacity by pairing the users within a system using the Hungarian method and the modified Hungarian method. For pairing users using the methods mentioned above, we need to generate a cost matrix using group A and group B users and then calculate the cost of each possible pair. Let us consider m users in a network among which users numbered with 1 to n belong to group A, and the users from n + 1 to m belong to group B. The cost function C i,j can be calculated as Ci, j =

1 1 + Rs SINR

(9)

with 1 ≤ i ≤ n and (n + 1) ≤ j ≤ m where Rs is the sum rate calculated using (10), and SINR is the difference of SINR of user i and user j calculated using (11). R s = Ri + R j

(10)

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SINR = SINRi −SINR j

(11)

where Ri and Rj are the data rates of user i and user j, respectively. The increase in SINR increases the difference of channel gains, thereby giving higher rate gain taking the cost function value to zero approximately. The lesser is the cost value, more is the priority to those users to get paired up. For pairing two users, two restrictions are to be considered which are as follows: (i) Rs ≥ Ri , with Rs determined as per (3). This assures that the pairing of users will give higher network capacity gain. (ii) I MCS,i < I MCS,j , to assure that the user with higher channel gain is the one accessing the resources allocated to the user with low channel gain. The values I MCS,i and I MCS,j correspond to the modulation and coding scheme (MCS) index of user i and user j, respectively. The users which do not satisfy (i) and (ii) are not suitable for pairing and give the cost which will be greater than the maximum C i,j in the cost matrix so that such pairs cannot be paired. After generating the cost matrix, some algorithms are used for selecting the best pairs which require minimum cost for pairing, thus enhancing the network capacity. The number of pairs in the cost matrix should be same as the number of users in a group with less users unless two or more users in one group pair up with the same person in the other group.

2.4 Hungarian Method Hungarian method is used to pair the users based on the cost required for each possible pair in the cost matrix. Always the cost matrix that has to be generated should be a square matrix for Hungarian method to get optimal solution. If the number of users in group A is not same as the number of users in group B, dummy rows or columns are added additionally in order to get a square matrix. The steps those are involved in the Hungarian algorithm are shown in Fig. 1. Here, n is the order of cost matrix. In Fig. 1, N is the sum of number of horizontal and vertical lines. This algorithm expressed as: n ismathematically m C x Minimise i=1 i, j i j j=1  1, if the user i is already paired with user j where xi, j = 0, if the user i is not paired with user j with the restrictions  (a) x i, j = 1; j = 1, 2,…, n, to guarantee that the user i has only one pair. (b) x i, j = 1; i = 1, 2,…, n, to guarantee that the user j has only one pair.

Modified Hungarian User Pairing Method For NOMA-Based 5G Networks Fig. 1 Hungarian method

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2.5 Modified Hungarian Method In Modified Hungarian method, after drawing horizontal and vertical lines in the cost matrix to cover zeros (N) and after attaining the condition N − n = 1, partial assignment (pairing) has to be done. If the element, which is at the intersection of a row and column in which no assignment was made, is not the minimum of all the uncovered elements, then the previous partial trail pairing will not give the optimal assignment. In this case, Hungarian method is followed (Figs. 1 and 2).

2.6 Network Sum Rate The overall sum rate of a network is calculated by summing up the data rates of all users present in the network. It is given by Sum rate =

n 

Ri

(12)

i=1

where n is the number of users in a network.

3 System Model and Implementation Let us consider a system model with 10 users in a cell under a single base station as shown in Fig. 3. Let us assume that all the users need resources in the subframe. They are grouped into group A and group B as shown in Table 1. In order to calculate the data rates of the users to calculate the cost of the pair for generating a cost matrix, the values of channel gains and SINRss of the users are assumed as in Table 2. In this paper, a hybrid multiple access scheme, in which both NOMA and OMA coexist, is implemented. Depending on the load and the users channel conditions, the system in Fig. 3 might use either OMA or NOMA. Let the entire bandwidth be 1 GHz for our analysis, and it is further divided into five equal bands which are is nothing but OMA scheme. Each band will be allocated to a pair of users which transmit data using NOMA technique in that available bandwidth. Because of power-domain NOMA being used here, we can accommodate a pair of users for transmitting data without dividing bandwidth available. Hence, sum-rate gain increases in the case of hybrid multiple access which will be shown. The data rates are calculated using (1) and (2), and cost is calculated using (9), (10) and (11) considering the values given in Table 2. Similarly, cost is calculated for each shown and every possible pair (one from group A and the other from group

Modified Hungarian User Pairing Method For NOMA-Based 5G Networks Fig. 2 Modified Hungarian method

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Fig. 3 System model for user pairing

Table 1 Grouping of users in the cell

Table 2 Channel gains and SINRss of 10 users

S. No

Group A

Group B

1

User 1

User 6

2

User 2

User 7

3

User 3

User 8

4

User 4

User 9

5

User 5

User 10  h 2  i N0,i

 User

Channel gain

SINRi

1

4

30

2

50

5

3

5

25

4

55

4

5

70

1

6

3

35

7

1

50

8

70

1

9

60

2

10

25

15

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B), and the 5 × 5 cost matrix is generated which is below for the assumed values in Tables 2 and 3. Now Hungarian algorithm and Modified Hungarian algorithms are applied on this cost matrix to get the optimal pairing solution. In Figs. 4 and 5, implementation of Hungarian and Modified Hungarian methods is shown. In the case of implementation of Hungarian method, modified cost matrix, i.e. (d) in Fig. 4, has to be generated. So, the number of arithmetic operations involved in generating this modified cost matrix increases the computational complexity in Hungarian method. But in the case of Modified Hungarian method, there is no need Table 3 5 × 5 cost matrix for user pairing Group A Group B

User 1

(a)

User 10

User 7

User 8

User 9

User 6

0.022

0.0265

0.0128

0.013

0.084

User 2

0.0206

0.0105

0.0421

0.0554

0.0126

User 3

0.0311

0.0202

0.0144

0.0147

0.0417

User 4

0.0187

0.0106

0.0542

0.0792

0.0123

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Fig. 4 Implementation of Hungarian method. a–f are the steps of Hungarian method

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Fig. 5 Implementation of modified Hungarian method. a is the step obtained by performing operations of (a) and (b) of Fig. 4 on Table 3. b is the step obtained by doing assignment directly on (a) of Fig. 5 as per the algorithm

of generating that modified cost matrix, i.e. (d) of Fig. 4, before assignment as in Hungarian method. Here, the partial pairing is done directly on (c) of Fig. 4. So, the number of arithmetic computations involved in doing (d) of Fig. 4 reduces in the case of Modified Hungarian method. Hence, its computational complexity reduces compared to that of Hungarian method. The remaining steps are the same for both the algorithms. From Table 4, it is observed that the computational complexity involved in using Modified Hungarian method is less compared to that of the Hungarian method. The number of lines drawn, the number of modified cost matrices to be obtained and the number of arithmetic operations to be performed are less for Modified Hungarian Method than that of Hungarian Method. Table 4 Comparison between Hungarian and modified Hungarian methods

Hungarian method

Modified Hungarian method

No. of lines drawn

9

4

No. of arithmetic computations

51

40

Fig. 6 Network sum rate comparison of modelled network

Network Sum rate(Gbps)

Modified Hungarian User Pairing Method For NOMA-Based 5G Networks

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3.7373

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3.2977

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Data rate of each user in the cell is calculated in the case of OMA implementation alone using values assumed in Table 2 without considering NOMA. Then, network sum rate is calculated using (12). After the optimal pairing of users is done using Hungarian and Modified Hungarian methods, considering the hybrid multiple access scheme, in which both NOMA and OMA coexist, the network sum rate is calculated accordingly, and the comparison is shown in Fig. 6 for OMA, Hungarian and Modified Hungarian methods cases. The percentage increase in the sum rate of NOMA over OMA is calculated as  Sum-rate gain =

RNOMA − ROMA ROMA

 × 100

The percentage increase in the sum rate is found to be 13.337%.

4 Conclusions In this paper, we presented the Modified Hungarian method of user pairing for powerdomain based hybrid multiple access scheme (OMA and NOMA coexist). Our model consists of a cell with a base station serving 10 users simultaneously by applying hybrid multiple access scheme. We have emphasised on comparing the performance of the two pairing methods, namely the Hungarian and the Modified Hungarian when the NOMA scheme is applied. The complexity involved in two user pairing methods is compared with respect to the number of computations performed. We have observed that the Modified Hungarian method provides same network capacity with lesser computational complexity in user pairing compared to the Hungarian method. We also observed that the proposed scheme provides a significant increase in the network sum-rate gain by 13.337% than conventional OMA. Therefore, the proposed scheme provides a better network capacity with lesser computational complexity for 5Gbased NOMA networks.

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References 1. Pirinen P A brief overview of 5G research activities. Centre for Wireless Communications, P.O. Box 4500, FI-90014 University of Oulu, Finland, Email: [email protected] 2. Dai L, Wang B, Yuan Y, Han S, Chih-Lin I, Wang Z (2015) Non-orthogonal multiple access for 5G: solutions, challenges, opportunities, and future research trends. IEEE Commun Mag 53(9):74–81 3. Di B, Bayat S, Song L, Li Y Radio resource allocation for downlink non-orthogonal multiple access (NOMA) networks using matching theory 4. Dai L, Wang B, Yuan Y, Han S, Chih-Lin I, Wang Z (2015) Non-orthogonal multiple access for 5G: solutions, challenges, opportunities, and future research trends. IEEE 5. Ding Z, Lei X, Karagiannidis GK, Schober R, Yuan J, Bhargava V (2017) A survey on nonorthogonal multiple access for 5G networks: research challenges and future trends 6. Riazul Islam SM, Zeng M, Dobre OA (2017) NOMA in 5G systems: exciting possibilities for enhancing spectral efficiency 7. Aldababsa M, Toka M, Gökçeli S, Kurt GK, Kucur OL (2017) A tutorial on nonorthogonal multiple access for 5G and beyond. Hindawi 8. Riazul Islam SM, Avazov N, Dobre OA, Kwak KS (2016) Power-domain non-orthogonal multiple access (NOMA) in 5G systems: potentials and challenges. IEEE Commun Surv Tutor 19(2):721–742 (Dec, 2016) 9. Liu Y, Qin Z, Elkashlan M, Ding Z, Nallanathan A, Hanzo L (2017) Non-orthogonal multiple access for 5G and beyond. IEEE 10. Riazul Islam SM, Avazov N, Dobre OA, Kwak KS (2016) Power-domain non-orthogonal multiple access (NOMA) in 5G systems: potentials and challenges. IEEE Commun Surv Tutor PP(99):1–1 (Oct, 2016) 11. Higuchi K, Kishiyama Y (2012) Non-orthogonal access with successive interference cancellation for future radio access. In: Proceedings of APWCS. Kyoto, Japan 12. Ding Z, Liu Y, Choi J, Sun Q, Elkashlan M, Chih-Lin I, Poor HV (2017) Application of non-orthogonal multiple access in LTE and 5G networks. IEEE Commun Mag 55(2):185–191 13. Marcano AS, Christiansen HL (2018) Impact of NOMA on network capacity dimensioning for 5G hetnets. IEEE 14. Dutta J, Pal SC (2015) A note on Hungarian method for solving assignment problem. http:// www.tandfonline.com/loi/tios20

Adaptive Bi-threshold Algorithm for ECG Compression Based on Signal Slope Y. Mahesha and B. L. Lavanya

Abstract Electrocardiogram (ECG) is used to record electrical activity associated with the functioning of the heart. These signals are highly data intensive and have higher resolution; thus, ECG signals require large space for storage in database and more transmission bandwidth. The ECG signals contain information signal with some redundancies; by removing these redundancies, better ECG signal compression can be achieved. The ECG compression algorithm should have high compression ratio (CR), low percent root-mean-square difference (PRD), low reconstruction error, and less computational complexity. DCT/FFT methods use frequency transformation and parameter extraction techniques. In dynamic compression scheme, IF sampler and lossless encoder are used. Both methods require preprocessing of the ECG signal. In the proposed method, the preprocessing of ECG signal is not required; signal compression is based on two threshold values, and the noise is eliminated. Using these techniques, better CR, PRD, and less storage space are achieved. Keywords ECG signal · DCT/FFT method · Lossless encoder · Dynamic compression scheme · Signal compression · Compression ratio · Root-mean-square difference · Noise stress test database

1 Introduction The electrocardiogram (ECG) is the graphical representation of the heart’s electrical activity. A typical ECG signal has P, Q, R, S, and T waves. Cardiologists use these signal features to analyze the health of the heart (various disorders like atrial flutter, fibrillation, bundle branch blocks, etc.). In order to store these features, it requires large storage space. For reducing the storage space, ECG compression techniques are Y. Mahesha Electronics and Communication Department, St. Joseph Engineering College, Mangaluru, India e-mail: [email protected] B. L. Lavanya (B) Electronics and Communication Department, NMAM Institute of Technology, Karkala, India e-mail: [email protected] © Springer Nature Singapore Pte Ltd. 2020 S. Kalya et al. (eds.), Advances in Communication, Signal Processing, VLSI, and Embedded Systems, Lecture Notes in Electrical Engineering 614, https://doi.org/10.1007/978-981-15-0626-0_19

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used, which reduce the bits used to represent the cardiac disorder with high-quality ECG signal and less storage space. ECG compression techniques are classified as direct data compression techniques, parameter extraction techniques, and transformation methods. Transformation method contains transformed data from the original signal and the inverse process for the reconstruction of the original signal. Discrete cosine transform (DCT) or fast Fourier transform (FFT) [1] belong to this category. Dynamic compression scheme [2] is another method for compressing the ECG signals in wireless sensors. Parameter extraction method is a compression achieved by extracting some parameters. This parameter can be used for the signal representation and reconstruction. Local extrema extraction [3] and R-peak detection algorithm [4] belong to this category. The discrete wavelet transform (DWT) [5] is another technique for the time–frequency analysis. Direct data compression techniques (AZTEC [6]) generally reconstruct the more important information containing samples and discard the rest. Other existing methods include compression algorithm using matching templates [7], run-length encoding (RLE) [8], and various applications, including health monitoring system [9] and ANN-based compression [10]. The proposed method uses a threshold- and slope-based ECG compression technique and thereby achieves high compression ratio, and the accurate signal can be reconstructed without any loss of information content. Further preprocessing is not required and noise is eliminated are the advantages of this technique. ECG compression algorithm should measure Compression Ratio (CR) and Percent Root-meansquare Difference (PRD) which measures high quality of the reconstructed ECG signals.

2 Dynamic Compression Scheme QRS complex signal and baseline have same representative bits, but more information is present in QRS signal. The direct transmission of only ECG signal is redundant; by compressing this signal, higher efficiency can be achieved. DC scheme allocates bits according to information present in ECG. Figure 1 shows the block representation of DC scheme.

2.1 IF Sampling An IF  sampling contains an integrator and comparators as shown in Fig. 2. Timebased − encoding is used for measuring small- and high-amplitude signals. The positive and negative threshold (±θ ) values are found by convolving f (n) which is the input signal and u(n) which is average function signal. The integral of the signal during a fire time interval (tk + τ , tk + 1), τ is refractory period. Initial value of θ is calculated by the QRS waveform of ECG signal.

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Dynamic Compression ECG Signal

IF Sampler

Lossless Encoder

Transmitter (Wireless)

Receiver (Wireless)

Decoder

Recovery

User

Decompression

Fig. 1 Block representation of DC scheme

The reconstructed signal should contain the information with the significant diagnostic features of ECG signals. High CR and low PRD indicate a reconstruction of compressed ECG signals which have high quality. It helps cardiologist to detect and analyze and cardiac condition accurately, by extracting important diagnostic parameters from the reconstructed ECG signal. The reconstructed ECG signal is represented by Eq. 1. β is the desired oversampling time period, and φ(n) is the reconstruction signal kernel function. fˆ(βk) =



s(k)φ(−βk)

(1)

k∈z

The IF sampler output has two parts—time stamps and sign phases. Sign phase (binary) need not to be encoded, whereas time stamps need to be encoded using lossless entropy encoder (Huffman coder).

3 Proposed Method In original ECG signals, there are artifacts that disturb the signals, and when signals are compressed, the artifacts also get processed normally; therefore, more memory space is required to store it. In order to avoid this problem, a threshold value is fixed, which is the minimum of overall signal. Then, a threshold-finding algorithm is introduced to fix the threshold value according to the signal slope. Threshold values are changed as per the variation in the signal slope. Flowchart for ECG compression is shown in Fig. 2. • Step 1: Initialize the slope1, slope2, threshold1, and threshold2. Let x(n) be the incoming signal. • Step 2: Calculate slope1 = x(n) − x(n − 1). • Step 3: Calculate tempslope = x(n + 1) − x(n).

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Initialize slope1, slope2, threshold1, threshold2.

slope1= x(n)-x(n-1) Update threshold1 threshold2.

tempslope=x(n+1)-x(n)

X= (tempslope-slope1)

Discard tempslope

Yes

If X threshold2

compressed_data={compressed_data, slope1, n} clear slope1

No Slope2= Slope1 Skip one sample tempslope=x(n+1)-x(n) Y= tempslope-Slope1

compressed_data={compressed_data, slope1, n-1} slope1=slope2.

No

If X < threshold2

Yes Fig. 2 Flowchart of ECG compression

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• Step 4: Find the difference between tempslope and slope1, if is less than threshold1 discard tempslope and go to step 3, else change compressed_data, {compressed_data, slope1, n} and clear slope1 and go to step 2. If the difference between tempslope and slope1 is between threshold1 and threshold2, then store the difference in slope2 and skip next sample. • Step 5: Compute tempslope = x(n + 1) − x(n). Find the difference between tempslope and if slope is less than threshold1, go to Step 3 or else {compressed_data, slope1, n − 1} and slope1 = slope2. • Step 6: Update the threshold values using threshold-finding algorithm and go to step 3.

3.1 Threshold-Finding Algorithm • Step 1: Reconstruct the ECG signal from the compressed data. • Step 2: Find the original signals PRD and reconstructed signal PRD. This PRD is required for compression, and it is according to the application. • Step 3: If the PRD difference lies between an acceptable value, then threshold is not changed. • Step 4: If the PRD difference is very much greater, then conversion rate (mu) = 0.7. • Step 5: If the PRD difference is slightly greater, then conversion rate (mu) = 0.4. • Step 6: For fast varying and plateau region, th1 increases and th2 decreases.   th1 = th1 − mu PRDnew − PRDreq   th2 = th2 + mu PRDnew − PRDreq • Step 7: For slow slope regions, if slope is positive, th1 is increased and th2 kept constant.   th1 = th1 − mu PRDnew − PRDreq For slow slope regions, if slope is negative, th1 is decreased and th2 kept constant.   th1 = th1 + mu PRDnew − PRDreq

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4 Results and Discussion Various ECG signals from the PhysioBank ATM can be used for analyzing this algorithm. Original and reconstructed signal of compression analysis of 100 m MITBIH and 207 m MIT-BIH ECG signal is shown in Figs. 3 and 4. Table 1 shows the different length of MIT-BIH ECG signals. Performance comparisons of 223 m ECG signal for different methods are shown in Table 2.

Fig. 3 100 m MIT-BIH ECG original and reconstructed signal

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Fig. 4 207 m MIT-BIH ECG original and reconstructed signal

The performance found by calculating the CR and PRD is given by Eqs. 2 and 3, where f (i) is the original signal and f (i) is the reconstructed signal. 



f (i) − f (i) ∗ 100% CR = f (i)    n ( f (i) − f (i))2 i=1 n PRD = 2 i=1 f (i)

(2)



(3)

The signals for the testing the algorithm were taken from the PhysioBank ATM; several databases are available in the PhysioBank ATM MIT-BIH arrhythmia database. It was the first database which contains set of standard test material for evaluation of arrhythmia detectors. ECGs have 4000 long-term Holter recordings

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Table 1 Performance comparisons of ECG signals Description

Original signal

Reconstructed signal

117 m CR(%) = 83.08 PRD = 0

202 m CR(%) = 78.37 PRD = 0.019

119 m CR(%) = 85.9 PRD = 0.043

214 m CR(%) = 82.97 PRD = 0

105 m CR(%) = 82.78 PRD = 0.10

118e12 m CR(%) = 77.71 PRD = 0.56

223 m

(continued)

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Table 1 (continued) Description

Original signal

Reconstructed signal

CR(%) = 87.54 PRD = 0 102 m CR(%) = 83.10 PRD = 0.018

Table 2 COMPARISON of 223 m signal for different methods ECG signal

DCT compression

FFT compression

Proposed method

CR

PRD

CR

PRD

CR

PRD

223 m

89.6%

0.58

91.32%

1.08

87.54%

0

which have been obtained by the Beth Israel Hospital Arrhythmias Laboratory from 1975 to 1979, and about 60% of these recordings were obtained from inpatients. The ten records from this database numbered from 100 to 110 were chosen which comprise a variety of important parameters for arrhythmia detectors. The 100 m signal is taken into consideration for the detailed study of R-peak. The R-R interval is used to access the ventricular rate where the heart rate is more in 100 m signal. The 207 m signal represents functional arrhythmias. It occurs when electrical activation of the heart originates near or within the AV node instead of from the SA node, and P wave is not present. 102, 105, 117, and 119 m MIT-BIH are commonly used for clinical tests. 202 m contains complex ventricular and 214 m contains supraventricular arrhythmias. 223 m represents the tachycardia rhythm, and 118e12 m signal of MIT-BIH Noise Stress Test Database (NSTD) has typical noise in ECG. Figures 5 and 6 show the graphs of PRD and CR (in percentage) for different ECG signals, DC scheme, and proposed scheme. In Table 2, it is found that the proposed method has very high CR and very low PRD compared to DCT and FFT compression methods. The proposed method provides maximum CR and PRD performance for signal containing high-frequency noise and sharp peaks. This method gives a worst result for signal containing slow variation with high amplitude and low or high PRD performance for signal having large amount of high-amplitude noise. For signals with large variation and signals with sharp variations, this method gives a better result while comparing with the base paper’s method. Adaptive threshold method introduced gives a considerable amount of performance change in compression ratio while comparing with fixed threshold method in signal having large amount of noise.

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Fig. 5 Plot of PRD for DC and proposed scheme

Fig. 6 Plot of CR for DC and proposed scheme

5 Conclusion The proposed algorithm enhances the quality of the ECG signal by providing necessary improvements on CR and PRD. Adaptive threshold method gives a considerable amount of performance change in CR while comparing with fixed threshold method in signal having large amount of noise. The proposed method for 223 m MIT-BIH ECG signal was compared with DCT and FFT methods. It is found that the proposed method has high CR 87.54% and low PRD 0. Overall, the proposed method produces an average of 16.25% improvement in CR and 98.11% improvement in PRD for different MIT-BIH signals.

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References 1. Mahajan R, Bansal D (2014) Hybrid ECG signal compression system: a step towards efficient tele-cardiology. In: IEEE 2014 international conference on reliability, optimization and information technology (ICROIT) 2. Luo K, Li J, Wu J (2014) A dynamic compression scheme for energy-efficient real-time wireless electrocardiogram biosensors. IEEE Trans Instrum Meas 63(9) 3. Negoita M, Goras L (2008) On a compression algorithm for ECG signals. IEEE Trans Biomed Eng 4. Mukhopadhyay SK, Mitra M, Mitra S (2011) An ECG data compression method via R-peak detection and ASCII character encoding. In: International conference on computer, communication and electrical technology—ICCCET 5. Qureshi KA, Patel VP (2013) Compression of ECG signal using discrete wavelet transform. In: Proceedings of SARC-IRAJ international conference. ISBN: 978-93-82702-21-4 6. Qu X-C, Zhang Y (2014) A compression algorithm for ECG data using variable length classified template sets. In: International symposium on computer, consumer and control 7. Wadhwani S, Wadhwani AK, Tripathi E (1982) ECG data compression using enhanced modified AZTEC technique. IEEE Transaction on BME, 35(3):43–8 8. Akhter S, Haque MA ECG compression using run length encoding. In: 18th European signal processing conference (EUSIPCO-2010) Aalborg, Denmark, 23–27 Aug 2010 9. Siao S-R, Hsu C-C, Po-Hung Lin M, A Novel Approach for ECG Data Compression in Healthcare Monitoring System. In: 2014 IEEE international symposium on bioelectronics and bioinformatics (IEEE ISBB 2014) 10. Pathak A, Wadhwani AK (2012) Data compression of ECG signals using error back propagation (EBP) algorithm. Int J Eng Adv Technol (IJEAT) 1(4). ISSN: 2249-8958

Design of Set D Flip-Flop and Scannable Set D Flip-Flop with Optimized Area M. Pooja, Guruprasad S. Shetty, Vedantham Shabara Datta and M. Suchitra

Abstract In modern integrated circuits, power and area are being key factors to be considered while designing. So we have chosen customized designing of D flip-flop with inverter buffers and tristate inverter buffers which reduces power consumption when compared to other types of flip-flops like SR flip-flop and JK flip-flop. In this paper, a D flip-flop is designed using nine tracks operating with 0.8 V and the poly pitch maintained is 0.24 nm. The library is implemented using 45 nm in Cadence Virtuoso v6.1.6. This article consists of a D flip-flop with set pin in positive edge triggering. As the testing of circuit with D flip-flop is usually difficult, the addition of scannable circuit to this is also done. According to results obtained from simulation, these designs reduce the power consumption and area when compared to in-built library in Cadence Virtuoso v6.1.6. Keywords VLSI-very–large-scale integration · TG-transmission gate · TB-tristate inverter buffer · CLK-clock · CLKB-clock bar · ASIC-application-specific integrated circuit · CMOS-complementary metal-oxide-semiconductor

M. Pooja · G. S. Shetty (B) · V. S. Datta · M. Suchitra Electronics and Communication, Vidyavardhaka College of Engineering, Mysore, India e-mail: [email protected] M. Pooja e-mail: [email protected] V. S. Datta e-mail: [email protected] M. Suchitra e-mail: [email protected] © Springer Nature Singapore Pte Ltd. 2020 S. Kalya et al. (eds.), Advances in Communication, Signal Processing, VLSI, and Embedded Systems, Lecture Notes in Electrical Engineering 614, https://doi.org/10.1007/978-981-15-0626-0_20

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1 Introduction As we observe, the integrated circuit technology has undergone some revolutionary changes since some decades. From Moore’s law, it suggests that as the time increases, the number of transistors on a chip will also be increasing in exponential way. This has become a burden of cost for the manufactures for which very-largescale integration (VLSI) techniques came into existence. CMOS design is type of VLSI technology that has reduced power dissipation when ease of use compared to bipolar and NMOS technology. The researchers have done some works and came out with various approaches to increase the performances of the electronic devices. Flip-flops are the most fundamental building blocks of many digital VLSI circuits. There are many types of flip-flops such as SR flip-flop, JK flip-flop, D flip-flop, T flip-flop, and so on. D flip flop seems more advantageous as it does not come up with problems that occur in other types such as, uncertainty in output when both inputs are same in SR flip flop and in JK flip flop when both J, K and clock is one, then its swipes the previous output. In addition, D flip-flops do not alter the data and they are versatile too. The scannable D flip-flop is a D flip-flop with the multiplexer added at the input with one input of the multiplexer acting as functional input D and other input serving as scan-in (scannable input). CMOS designs such as circuits and layouts can be simulated and verified using Cadence Virtuoso v6.1.6. Cadence Virtuoso is a tool used to design to help users to create manufacturing robust designs.

2 Literature Survey Before forming the final schematic design of set D flip-flop and scannable set D flip-flop, many designs have been simulated and verified. And few keys points from referred papers have been taken. In paper [1], D flip-flop consists of transmission gate in both master loop and slave loop. Transmission is used to give the clock input signal. The working of set D flip-flop and scan D flip-flop has been explained in this section. Layouts of D flip-flops had been explained in paper [2]. The usage of metal-2 will help in reducing the area. With proper stick diagram of the schematic, we can reduce the layout. In paper [3], scan flip-flop operation has been discussed. Scan flip-flop is very useful during the time of design for testability. From the simulation results, we can further reduce the area and power by maintaining a poly pitch of 0.27 µm and by constructing the layout in nine tracks. The usage of tristate devices in place of transmission gate in the loops reduces the power consumption which has its high impedance during null operation or no transfer of data.

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Fig. 1 Set D flip-flop

3 Design The working of set D flip-flop and scan D flip-flop as been explained in this section.

3.1 Set D Flip-Flop Set D flip-flop consists of two loops as shown in Fig. 1. Master loop consists of standard CMOS inverter and a tristate buffer inserted in the feedback loop. This form of implementation requires two clock signals CLK and CLKB, and the resulting circuit is equivalent to positive edge-triggered inverting D flip-flop. Slave loop consists of two-input NAND gate and tristate buffer. Two-input NAND gate is used to provide set input to the D flip-flop. Master loop gets it D input from transmission gate TG1 and TG2 and connects the output of master loop to the input of slave loop. The usage of transmission gate allows it to act as edge-triggered D flip-flop. When the clock signal is high, TG2 and tristate buffer are master loop are in the OFF state, while TG1 and tristate buffer in slave loop are in the ON state. Therefore, the slave loop is isolated from the master loop. The slave loop feedback is closed, and hence, it allows to retain the previous state. On the other hand, the feedback loop of the master latch is open and the output of the master loop is same as of the D input. The usage of master loop is the most efficient way of storing data [1].

3.2 Scannable Set D Flip-Flop Figure 2 shows scannable set D flip-flop. A scan flip-flop is ordinary flip-flop modified for the sake of using it during design for testability. Scan flip-flop contains a MUX to select either a normal operation with data input or scan operation with scan input. It has a control input to select either data or scan input. They are very much conceptually

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Fig. 2 Scannable set D flip-flop

related to fault simulation purposes, in order to check the current state of the flip-flop ensuring the rightness of the state.

4 Proposed Layouts This paper aims in reducing the overall area such that the design becomes better applicable for the lower power application. Figure 3 shows the full custom layout of set D flip-flop.

Fig. 3 Full customized set D flip-flop layout

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Fig. 4 Full customized layout design of scannable D flip-flop

To continue with this, the layout is created in full custom manner using 9 tracks over 12 tracks as in Cadence Virtuoso library which will help in reducing overall area. Figure 4 shows the full custom layout of scannable set D flip-flop [2].

5 Simulation and Results The designs are implemented using Cadence Virtuoso tool. CMOS logic is used to design the circuit. The schematic and waveform of the designed D flip-flop are shown in Figs. 4 and 5. Figures 6 and 7 show the schematic and waveform of scannable D flip-flop. The functionality of the proposed design is verified, and a comprehensive study of area reduction has been done.

6 Conclusion This article has focused on designing set D flip-flop and scannable set D flip-flop using Cadence Virtuoso v6.1.6 with reduced area and hence the power. These designs are also effective in ASIC design. The scannable D flip-flop is extensively used for device testing. Simulation results from Table 1 conclude that this design can operate at 0.8 V as input voltage and with reduced power consumption and reduced area.

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Fig. 5 Set D flip-flop schematic

Fig. 6 Waveform of set D flip-flop

M. Pooja et al.

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Fig. 7 Scannable set D flip-flop schematic

Table 1 Comparison between proposed layout and Cadence library

Parameters

Proposed layout

Cadence library

Area

4.32 µm2

6.019 µm2

Cell height

1.24 µm

1.9 µm

Tracks

9

12

Operating voltage

0.8 V

1.1 V

Acknowledgements The authors are greatly thankful to the management of Vidyavardhaka College of Engineering for support and encouragement.

References 1. Saw SK, Maiti M, Meher P, Chakraborty SK (2016) Design and implementation of TG based D flip flop for clock and data recovery application 2. Chakravarthi PK, Mehra R (2015) Layout design of d flip flop for power and area reduction. Int J Sci Res Eng Technol (IJSRET) (ISSN: 2278–0882 EATHD-2015 Conference Proceeding) 3. Xiang D, Li KW, Fujiwara H (2005) Design for cost effective scan testing by reconfiguring scan flip-flops. In: 14th Asian test symposium. IEEE

User Satisfaction-Based Resource Allocation in LTE-A Jagadeesha R. Bhat and S. Anantha Kamath

Abstract The resource allocation issue in LTE-A is a challenge as it is a combinatorial optimization problem, involving several constraints. The resource blocks (RBs) can be scheduled to a user at every 1 ms, following the adaptive modulation coding (AMC) techniques. In this paper, we address the resource allocation problem for a unicast scenario (i) to maximize the number of satisfied users and (ii) to maximize the overall throughput by packet-level scheduling when the resources are limited. Both problems are NP-hard, and as a result, we proposed two heuristic algorithms that could meet the said objectives in polynomial time by adaptively selecting the RBs. The performance evaluation of the proposed algorithms shows that these algorithms outperform the conventional greedy method in terms of user satisfaction, resource consumption, and system throughput. Keywords Resource allocation · Adaptive modulation coding · Packet-level scheduling

1 Introduction Recently, with the introduction of 4G standards, future progression of wireless data service seems promising. There is a huge demand for high-speed data, video, gaming services that require wide bandwidth and power that pose the primary challenge. In addition, delay, QoS, and need of an all-IP network will further demand the intensive design of next-generation networks. The Long Time Evolution-Advanced (LTE-A), an outcome of 4G telecommunication system is a promising technology. It offers tremendously high data rate of 1 Gbps in downlink, and up to 500 Mbps in uplink, to the mobile users using Orthogonal Frequency Division Multiple Access [1, 2]. J. R. Bhat · S. A. Kamath (B) Department of Electronics & Communication Engineering, St. Joseph Engineering College, Mangalore 575028, India e-mail: [email protected] J. R. Bhat e-mail: [email protected] © Springer Nature Singapore Pte Ltd. 2020 S. Kalya et al. (eds.), Advances in Communication, Signal Processing, VLSI, and Embedded Systems, Lecture Notes in Electrical Engineering 614, https://doi.org/10.1007/978-981-15-0626-0_21

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Here, the information bits are transmitted in the form of RBs by eNodeB (eNB) to the user equipment (UEs) by considering their channel quality (CQI). A resource block (RB) is the smallest schedulable radio resource which varies in time-frequency domain and is scheduled at every transmission time interval (TTI) of 1 ms as a pair. Moreover, only a specific number of RBs are supported by a particular bandwidth; however, by carrier aggregation, a number of RBs can be supported by LTE-A [1, 3]. These RBs are allocated by employing suitable modulation and coding schemes termed as adaptive modulation and coding (AMC), based on the user’s channel quality [4, 5]. It is a highly challenging task to allocate optimum resources with appropriate modulation and coding schemes (MCSs) to a user to satisfy its requirement, due to several constraints associated with RB allocation as we detailed in sect. 3. Many of the previous works on LTE-A downlink scheduling have focused either on a single antenna or MIMO-based environments. In [6–9], the authors targeted to maximize the overall throughput by packet-level scheduling, at every scheduling interval. In [10], overall throughput is maximized by overestimating the constraints of LTE-A with respect to MCS selection. In [11–13], carrier aggregation methods are explored to schedule LTE-A users. All these works have a similar objective of maximizing the overall throughput by considering uniform user data request rates. In this paper, we address the resource allocation problem for the LTE-A unicast users in downlink who have specific data requests and varying channel qualities on each RB. Motivated by the challenges and the constraints, the main objectives are to maximize the number of satisfied users by the minimum number of RBs and to maximize the system throughput assuming available RBs are limited. We know that both of these problems are NP-hard [8] [10] [14] [15, 16], and thus, only sub-optimal solutions can be found. In this proposed algorithm, we employ an adaptive greedy heuristic algorithm which first prioritizes the users, then allocates the RBs based on the future data request, local maxima, and by foreseeing the loss that would cause to next priority user. Our work is different from other works as we consider the individual user requests and aim to maximize the satisfied users. The main contributions of our proposed algorithms are polynomial time with complexity of O(T2 N + N2 ) where T is the total RBs. In addition, the simulation results show that the proposed algorithm outperforms the conventional greedy method in terms of average satisfied users, average RB consumption, and overall throughput and near to optimal. The rest of the paper is organized as follows. In sect. 2, we present the related work. In sect. 3, we formulate our downlink optimization problem, and in sect. 4, we present our algorithm and its time complexity analysis. The simulation results are presented in sect. 5, and we conclude our work in sect. 6.

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2 Related Works In this section, we present few most relevant research works on the downlink resource allocation issue of LTE-A networks. In the first classification, we concentrate on the research work that schedules the RBs by a most common CQI, and few others use carrier aggregation. In [8], users are assigned priority by determining the number of RBs needed to fulfill their data requests. In this case, the scheduler selects the users, assigns the RBs with the best CQI by the greedy approach, and employs a common MCS to all the selected RBs. However, this method is not efficient when CQI on each RB varies. The carrier aggregation-based downlink scheduling method, as proposed in [11], tackles the resource allocation problem by splitting into two parts. In the first stage, eNB schedules the component carrier to the user based on user’s data load at the scheduler queue, and in the second stage assigns the RBs by the greedy method. However, while transmitting the RBs, it uses the most efficient MCS that enhances the data rate. In an attempt to maximize the aggregated data rate in LTE-A, the authors in [10] have proposed an approximation algorithm, in which multiple component carriers (CCs) and RBs are allocated to the user by a common highest possible MCS. A highlight of this scheme is that during the iterations of the algorithm, some of the RBs can be reassigned to other users to improve the throughput. In LTE-A, it is obvious from the fact that the users can feedback the CQI for each resource block. As a result, the scheduler can employ different MCSs on each RB at different scheduling intervals to use AMC more efficiently. In [9], the authors have proposed a heuristic approach to obtain a near optimal solution. In this approach, a meta-heuristic genetic algorithm and simulated annealing are proposed that address the combinatorial problem to maximize the throughput. The component carrier-based resource allocation is addressed in [12]. Here, the authors proposed two methods namely independent and joint component carrier scheduling schemes. The overall objective is to attain fairness and maximize the throughput gain. In another work [13], CCs are scheduled by comparing the feature of users of LTE-A and Release 8 to schedule the CCs and to balance the load. The point to be observed here is that the method has good performance at low load. Here, we discuss the second classification of the research works that have considered the packet-level scheduling by using the most appropriate CQI. In [17, 18], the authors used packet-level scheduling in the downlink of a relay-based OFDM network, where the base station either directly or via relay nodes serves the users. It schedules the users at the packet level. This allows different packets transmitted to a user to have different priorities and MCSs at various scheduling intervals. The scheduling problem has formulated into a d-MCKP and is solved by using a heuristic water-filling algorithm, to offer performance guarantee in polynomial time. Frequency domain packet scheduling was described in [19, 20], where RBs are allocated to the user at every TTI. In those works, the authors presented an approximation algorithm that considers the MIMO scenario to schedule the blocks by various MIMO modes. We can clearly understand as mentioned in LTE [21], and the constraints on MCS with regard to the different transmission blocks of the MIMO are

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different when compared to the single antenna units. In case of MIMO, all the RBs belong to a transmission block need to use the same MCS; however, in a single antenna system, each RB can be transmitted with different MCSs at disparate TTI. While comparing to the above works, in our method, we schedule the users by assigning the most appropriate CQI on each RB at every transmission time along with carrier aggregation features. Our method is different from previously mentioned methods, as we assume each RB could have various CQI. Thus, we employ AMC scheme on each RB of any CC to assign a RB.

3 System Model A. Design Constraints In this section, we explain our network model to illustrate the scenario of resource allocation. To begin with, we detail the constraints associated with our problem of resource allocation which is similar to the constraints as mentioned in LTE-A standard [4, 21]. First, at any scheduling interval (TTI), the RBs have to be assigned in pairs to a single UE (unicast). Second, while assigning the RBs to a user from any selected CC, a single MCS needs to be used on all the scheduled pair of RBs for the particular user at that scheduling interval. However, at different TTI, we may use different MCSs. Some of the existing pieces of literature have overestimated this constraint [10]. Nevertheless, in multiple antennas (MIMO) scenarios, it is feasible to employ multiple MCSs in the same scheduling period on different transmission blocks assigned to a user from the eNB [17, 22]. In this paper, we consider that users and eNB have a single antenna. As a result, we abide by using single MCS on all the RBs at any particular scheduling period on a CC. Nonetheless, it does not confine to use different MCS at varying TTI. B. Network Model As shown in Fig. 1, our network scenario consists of a single cell eNB as a scheduler and N users. Each user has a specific data request and has a CQI for every RB. As a result, the scheduler maintains a global view of the CQI requests from every user toward an RB and schedules them with the appropriate MCS while considering the resource availability [2]. Let T be the total number of RBs available at the scheduler, and dRn (bits/s) be the data requirement of user n, for 1 ≤ n ≤ N . There are C number of CCs of equal bandwidth, from which the UEs can access the downlink data (nevertheless, different CCs can be aggregated to enhance the bandwidth). Let rc represents the  total number of RBs for a CC c, for 1 ≤ c ≤ C and Cc=1 rc = T . Let Rci denotes the i-th RB of a CC c, for 1 ≤ i ≤ rc . Any user n can feedback the CQI to the scheduler for each of the resource block i as cqiin , cqiin  cqi_set, where cqi_set be the set of channel quality of the users. Upon receiving a CQI from a user, the scheduler assigns (maps) suitable MCS for a RB at a TTI. We assume a backlogged traffic model in

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Fig. 1 An eNB and mobile users with individual data request

our design, and as a result, it is possible at the eNB to assign the RBs to any user at every TTI. The mapping scheme from CQI to appropriate MCS is implementation specific; in our algorithm, we represent a one-to-one mapping. For example, if a user requests a RB at CQI 1, then eNB can assign a RB with MCS value 1. However, it is applicable to any mapping schemes. In general, for successful reception of data (i.e., a RB) by an user, the eNB must use the MCS (for transmission) whose value is at least the value of CQI. Let dimcs be the bit rate (bit/s) transmitted by the scheduler for a RB i when it assigns a particular MCS, where mcs  mcs_set, and mcs_set be the set of modulation schemes the scheduler could assign to a RB. Table 1 shows the CQI table of three users A, B, and C for 9 RBs over 3 CCs. In Table 1, each user has three CCs, and each CC has 3 RBs. The CC 1 of user A has CQI 2, 1, 3 for RB 1, 2, 3, respectively. C. Problem formulation In our algorithms, we use the term user satisfaction to refer to users whose data request gets fulfilled completely. We consider a unicast scenario, where each UE has a data request dR, and this request has to be satisfied by the scheduler by assigning Table 1 Individual user’s channel quality table CC 1

CC 2

CC 3

CC 1

CC 2

CC 3

CC 1

CC 2

CC 3

2(R1)

2(R4)

3(R7)

3(R1)

2(R4)

1(R7)

1(R1)

1(R4)

1(R7)

1(R2)

1(R5)

2(R8)

2(R2)

3(R5)

1(R8)

3(R2)

1(R5)

1(R8)

3(R3)

2(R6)

1(R9)

3(R3)

1(R6)

1(R9)

1(R3)

3(R6)

2(R9)

User A

User B

User C

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RBs with the suitable modulation scheme. Let dimcs be the data bits corresponding to be the RB i modulated with mcs and the RB i for the selected MCS level. Let imcs n assigned to the user n. We assume that the available number of RBs is limited, as a result need to spend the resources cautiously. For this reason, each user is prioritized based on the number of RBs they expect to consume. By this way, the scheduler can attain the objective of increasing the number of satisfied users. Problem1 Maximize the number of satisfied users when the available resources are limited. The objective function of our problem 1 will be as follows. max

N 

Sn ;

(1)

n=1

Let Sn = 1 if the requested data rate of user n can be satisfied by our resource allocation and Sn = 0, otherwise. Subject to the following constraints (2)–(4): Under the assumption of a limited number of available RBs, we assume that dRn ≤ DR, where DR is the total data bits that can be allocated to all UEs using all the total available RBs. Therefore, Sn = 1 if,

rn 

n n dmcs, i ≥ dR

(2)

i=1 n The user will satisfy when its data request will be fulfilled. In (2), where dmcs, i is the data bits obtained by user n, when a RB i has assigned with MCS value mcs. The term r n implies the total number of RBs assigned to a user n. N   n=1

mcs∈mcs_set

xi,n c, mcs ≤ 1

(3)

where xi,n c, mcs is a binary indicator variable, indicates that RB i from CC c assigned with modulation scheme mcs to user n. The constraint (3) indicates each RB can be allocated to at most one user by only one MCS value at a particular TTI. Total number of RBs allocated from any CC to all the users will be ≤ T. N  C 

rcn ≤ T,

(4)

n=1 c=1

where rcn is the assigned number of RBs to a user n from CC c. Total data bits transmitted to a user will be determined by the product of the number of bits corresponding to the employed MCS on a RB and rcn . Problem 2 Maximize the throughput when available RBs are limited.

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In this problem, we assume that the available RBs are limited, and each user does not have separate data request. Thus, we measure the average channel quality of each user from the available RBs and prioritize them. Therefore, the objective of throughput maximization is as follows. max

 N r n 

 n dmcs, i

(5)

n=1 i=1 n where dmcs, i is the data bits obtained by user n, when a RB i has assigned with MCS value mcs. The term r n implies the total number of RBs assigned to a user n. Subjected to the constraint in (2)–(4) of problem 1.

4 Algorithms Before presenting our algorithms, we have the following definition. Definition1 The maximum gain and minimum loss are a scheduling policy, in which the current user will be assigned a RB of highest possible channel quality while decreasing the data loss that would occur to other users by this assignment. As an example, in Table 2, if user A has assigned R7 of CC 3, it gets a MCS of 3, while other two users lose that RB with a minimum loss of MCS 1 each. Instead, if R3 of CC 1 is assigned, though A gets maximum MCS 3, however B and C comparatively lose higher valued RB than R7 of CC 3. So, we prefer assignment of R7 to user A than R3. A. Algorithm 1: Maximizing the number of satisfied users when the RBs are limited. In our context, a user that meets its data rate requirement completely is called as a satisfied user. To serve a user, we need to decide the user’s serving order. The scheduler will decide the priority of the user to serve the RBs and the type of MCS to employ in such a way that each user consumes a minimum number of RBs. Thus, intuitively, we have the target of maximizing the number of satisfied users that consume less RBs. We have mentioned the outline of this idea in (6). Thus, this is purely an optimization problem of NP-hard complexity [10]. Initially, we n represents prioritize the users based on a weightage as computed by (6). Here, WRB the weightage computed for user n to assign the RBs. The intuition is to serve the Table 2 CQI of each RB for each user in CC1, CC2 and CC3

A/B/C CC 1

A/B/C CC 2

A/B/C CC 3

2/3/1 (R1)

2/2/1 (R4)

3/1/1 (R7)

1/2/3 (R2)

1/3/1 (R5)

2/1/1 (R8)

3/3/1 (R3)

2/1/3 (R6)

1/2/2 (R9)

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user that requires lesser number of RBs so that it can be satisfied easily. The term in the denominator of (6) determines the average channel quality over all the T RBs for user n. n WRB = dRn /

T 1  mcsi T i=1

(6)

The user with the lowest weightage attains the highest priority. This also provides an estimate of the number of RBs required to satisfy the user n. To begin with the RB allocation, we assign the RBs to the users by the rule as shown in algorithm 1, where the key strategy is the maximum gain and minimum loss policy. As shown in line 5, when the requested data rate of the user is higher than data bits that represent the highest MCS value, select the RB, which offers the highest bits while causing the least loss to other priority users. Later, when the number of data bits required becomes less than the maximum MCS bits, the user selects the RB of any nearest choice by following low loss high gain rule as in line 8. In this way, we assign the RBs such that each user consumes a minimum number of RBs to satisfy their data request. In order to serve the other user, the priority will be re-computed among the remaining RBs, and the same procedure will be followed as in line 14. We explain our algorithm with the help of an example. Throughout our paper, we assume that the CQI (MCS) 1, 2, and 3 refer to data bits 16, 24, and 32, respectively. There are three users A, B, and C with data request 40, 80, and 95 bits, respectively. Their experienced CQI on each RB of the CC is shown in Table 2. There are T = 9 RBs labeled as R1 to R9 over three CCs. As per the initial priority weight, the serving order will be users A, B, and C; then, we execute algorithm 1. Initial weight values of users A, B, and C will be 21.17, 40, and 61.09, respectively. To be specific, the dRA = 40 ≥ maximum available MCS bit (i.e., mcs = 3) so, the scheduler search for the RB that offers maximum gain to A with minimum loss to user B and C. So, first assign RB 7 to user A, then remaining dRA = 40−32 = 8 and for this condition, any RB can be assigned. However, RB 8 with MCS level 2 has the highest gain (i.e., mcs = 2) and cause lowest loss to other users; so assign RB 8 to satisfy A. Later, while serving the users B and C, the priority weight will be determined again by considering the remaining RBs. As per this example, user B has the higher priority than the user C. Therefore, the scheduler assigns RBs 1, 3, and 5 to the user B to fulfil its data request. Finally, the remaining user C will be served by RBs 2, 6, 9, and 4 to satisfy it completely. However, in a greedy rule, it is possible that multiple RBs will suit a condition, then assign a RB randomly. Thus, in this example by a greedy rule, user A will be assigned RBs 3 and 7 similarly for B RBs 1, 5, and 2. However, the remaining RBs 6, 9, 4, and 8 cannot satisfy user C.

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B. Algorithm 2: Maximize the throughput when available RBs are limited. In this problem, our objective is to maximize the user throughput by satisfying a user’s request. We assume that the individual users do not have a separate data request, or in other words, all the users have the uniform data request. Nevertheless, they have experienced CQI on each of the RBs. Thus, we estimate the user weight based on n as in (7), which is the average channel quality over T RBs for a user n. User WRB with the highest weight attains first priority. In (7), the term mcsin denotes the MCS value of user n on each of its RB i. In this algorithm, the computation of user priority is dynamic; i.e., while serving each priority user, we assign one RB in a round and re-compute the priority to decide the next user to serve in the same manner. n WRB =

T 1  mcsin T i=1

(7)

From Table 2, assume CQI 1, 2, and 3 represents 16, 24, and 32 bits, respectively. We determine the average CQI for each user A, B, and C as 1.88, 2.0, and 1.55, respectively. Thus, B will be the first priority user and selects R5 based on maximum gain minimum loss RB selection rule. Later, we re-compute the priorities for the remaining RBs and assign RBs similarly. In case multiple users of same priority, we break the tie randomly. We represent such a user by “#” notation in Table 3. The complete RB assignment in every TTI is shown in Table 3. By this scheme, at each Table 3 RB allocation to user A, B and C at each TTI TTI

1

2

3

4

5

6

7

8

9

User

B

A

B

A#

C

A#

C

B

C#

RB

R5

R7

R1

R3

R2

R8

R6

R4

R9

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TTI, the user with the best overall channel condition gets the opportunity to receive the data. We measure the overall throughput as the sum of all the data bits received by all the users, which are 264. By the greedy scheme, the RB selection does not consider the loss to the other users. As a result, the next priority user may lose its best RB due to the current users RB selection. In case of greedy, though a user may get multiple choices to select a RB based on greedy policy, we present one solution here. User B(R3), A(R7), B(R1), A(R6), C(R2), A(R4), C(R9), B(R5), C(R8), thus overall throughput becomes 248 bits.

The RB selection rule of Algorithm 2 is similar to algorithm 1. However, here chose the user with maximum weight as in line 2. Once we assign a RB to a user, we re-compute the weight for all users by deleting that RB as shown in lines 13, 14, and 15. C. Computational complexity From algorithm 1, let us assume T be the total number of available RBs. To find a RB that offers the highest gain and minimum loss requires O(T ). The estimate of the number of RBs required to satisfy the user depends on dR of the user and CQI. Let R    be the number of RBs required by a user R ≤ dR/d min_MCS  where d min_ MCS refers to the number of bits associated with the lowest channel quality of the user. However, in a worst-case scenario, R = T. So, the time required by an user will be O(T 2 ). As a result, N users need total time complexity of O(T 2 N). In addition, we have O(N) to choose  the minimum weight user, and this to be done for all N times which needs O N 2 . Thus, O(T 2 N + N 2 ) becomes time complexity of our algorithm 1. From algorithm 2, in order to choose a RB based on high gain and low loss policy, a user needs a computation time of O(T ). To carry out this process by all the N users

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in the system, we need O(TN). As a result, the time needed to select all T RBs will be O(T 2 N). In addition, to choose maximum weight,   user needs a time of O(N). And this to be done for all N users which needs O N 2 . Thus, O(T 2 N + N 2 ) will be the total time complexity by N users.

5 Simulation Results In this section, we discuss our experimental results to evaluate the performance of the two proposed algorithms. We wrote our simulator to execute the algorithms using Java programming and plotted the results in MATLAB. We used one-to-one mapping to map the received CQI to user MCS. In our simulations, we considered 15 MCS levels, the CC and the number of RBs in each CC are varied as the number of users, and their data requests vary at different trials. Each MCS level is represented by a difference of eight bits and increase in proportion with the MCS level. And each RB is of 1 ms duration (TTI) as per LTE specifications [4]. We compared our RB assignment algorithm, with the greedy and optimal selection. In case of the greedy method, the users select the RBs based on the highest value of MCS without considering the loss that would occur to the other users. At the same time, we used a brute force search to determine the optimum solution for the proposed problem. Due to the huge time complexity of the optimal solution, we could only run the simulation for small user set (eight users). Initially, we fixed the number of available RBs for each user set and varied user channel quality randomly for about 1200 sets of input values, with each user having a specific data request (bits). As shown in Fig. 2, as the number of users is varied from 2–50, we measured the average number of satisfied users using Algorithm 1. It is evident from the result that the proposed algorithm performs better than the greedy, due to its adaptive nature in selecting the RBs by considering the future data request and data loss that would occur to other users by its selection. Whereas, greedy selects the best available RBs by a local (static) search, consequently making the other users lose their most important RBs. As mentioned before, the optimum solution is computed only for eight users set. The performance is shown with the line marked as “opt” to represent the optima solution obtained by the brute force search. Figure 3 shows the average number of RBs required to satisfy the users in the above case by algorithm 1. Similar to the previous result, we can observe that the algorithm 1 performs better than greedy in terms of RBs conservation. As the proposed algorithm is adaptive in its selection, it incurs less loss to other users compared to greedy. Due to this, every user consumes less number of RBs on an average which increases the performance. In Fig. 4, we determine the average number of RBs required to satisfy all the users by algorithm 1 and compare with the greedy approach. This is different from Fig. 3 that will target only satisfiable users under the limited RBs constraint. In general, an efficient algorithm should consume a lesser number of RBs. In this case, we set the number of RBs for each user set such that all the users in the set satisfy. Later, we

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Fig. 2 Average satisfied users for varying number of users

Fig. 3 Average RB consumption for varying number of users

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Fig. 4 Average RBs for complete user satisfaction

note their RB requirements as plotted in Fig. 4. We perform this for user sets 5–50. It is clear from the result that the algorithm 1 requires lesser RBs than the greedy selection for every user set variation from 5 to 50. For instance, when the available RBs are 100, the proposed algorithm could satisfy all 40 users. However, the greedy method could only satisfy up to 30 users. This is mainly because the greedy can make only local choices. Thus, ignores the users that have relatively higher potential to get satisfied. We could simulate the optimal algorithm only for eight users, and the performance is nearer to the proposed algorithm for this user set. In Fig. 5, we determine the overall user throughput as mentioned in algorithm 2.

Fig. 5 Average throughput for varying number of users

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By our RB selection rule, each user could select the best RB at every TTI causing minimum loss to subsequent priority users. However, in the case of greedy, though it can select the best RB, the loss to other users has not considered. As a result, next priority user might lose its best RBs during current user’s selection; and lowers the throughput. We can see that for different user inputs, the throughput of the proposed algorithm is higher than greedy by around 50%.

6 Conclusion The resource allocation scheme for unicast users in LTE-A using packet-level scheduling has discussed here by assigning the RBs at every TTI at the best possible MCS. We proposed two algorithms with different objectives such as to maximize the number of satisfied users and to maximize the throughput when RBs are limited. Our algorithm used a RB selection rule that considers the gain to the current user and loss to the other users due to the assignment of a RB. The experimental results show that the proposed algorithms perform better than the greedy method and near to the optimal in terms of average satisfied users, average RB consumption, and throughput with reasonable time complexity. In future, we plan to extend our work to multicast users with multiple antenna systems.

References 1. Akyildiz IF, Gutierrez-Estevez DM, Reyes EC (2010) The evolution to 4G cellular systems: LTE-Advanced. Physical Communication, Elsevier 3:217–244 2. GPP TS 36.521-1 (2013) Evolved universal terrestrial radio access (E-UTRA); user equipment (UE) conformance specification; radio transmission and reception; part 1: conformance testing2013 3. Capozzi F, Piro G, Grieco LA, Boggia G, Camarda P (2013) Downlink packet scheduling in LTE cellular networks: key design issues and a survey. IEEE Commun Surv Tutorials 15(2):678– 700, Second Quarter 4. Dahlman E, Parkvall S, Sköld J (2011) 4G LTE/LTE-Advanced for mobile broadband, Academic Press 5. Chiumento A, Desset C, Pollin S, Perre LV, Lauwereins R (2014) The value of feedback for LTE resource allocation. In: IEEE wireless communication and networking conference (IEEE WCNC’14), Istanbul, Turkey, pp 2073–2078 6. Lee SB, Pefkianakis I, Meyerson A, Xu S, Lu SW (2009) Proportional fair frequency-domain packet scheduling for 3GPP LTE Uplink. In: IEEE International conference on computer communications (INFOCOM’09), pp 2611–2615 April 7. Zhao L, Qin Y, Ma M, Zhong X, Li L (2012) QoS guaranteed resource block allocation algorithm in LTE downlink. In: 7th international ICST conference on communications and networking in China (CHINACOM), pp 425–429 8. Guan N, Zhou Y, Tian L, Sun G, Shi JL (2011) Qos Guaranteed resource block allocation algorithm for LTE system. In: IEEE 7th international conference of wireless and mobile computing networking and communications (WiMob), pp 307–312

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9. Aydin ME, Kwan R, Wu J (2013) Multiuser scheduling on the LTE downlink with meta-heuristic approaches. Physical Communication, Elsevier 9:257–265 10. Liao HS, Chen PY, Chen WT (2014) An efficient downlink radio resource allocation with carrier aggregation in LTE-advanced networks. IEEE Trans Mob Comput 13(10):2229–2239 11. Cheng X, Gupta G, Mohapatra P (2013) Joint carrier aggregation and packet scheduling in LTE-advanced networks. In: 10th Annual IEEE communications society conference on sensor, Mesh and Ad Hoc communications and networks (SECON’13), pp 469–477 12. Liu L, Li M, Zhou J, Chen XL, Sagae Y Iwamura M (2011) Component carrier management for carrier aggregation in LTE-advanced system. Vehicular Technology Conference (VTC Spring’11) 13. Wang Y, Pedersen KI, Sørensen TB, Mogensen PE (2010) Carrier load balancing and packet scheduling for multi-carrier systems. IEEE Trans Wireless Commun 9(5):1780–1789 14. Sheu JP, Kao CC, Yang SR, Chang LF (2013) A resource allocation scheme for scalable video multicast in WiMAX relay networks. IEEE Trans Mob Comput 12(1):90–104 15. Li A, Sun Y, Xu X, Yang X (2015) QoS-aware user satisfaction oriented joint resource block and power allocation in OFDMA systems with cloud based information sharing. In: 2015 IEEE 16th international conference on communication technology (ICCT), pp 219–224 16. Abrahao CD, Vieira TFH, Ferreira GMV (2015) Resource allocation algorithm for LTE networks using βMWM modeling and adaptive effective bandwidth estimation. In: 2015 international workshop on telecommunications (IWT), pp 1–8 17. Cohen R, Grebla G (2015) Multidimensional OFDMA scheduling in a wireless network with relay nodes. IEEE/ACM Transactions on Networking, pp 1765–1776 Dec 18. Cohen R, Grebla G (2014) Multi-dimensional OFDMA scheduling in a wireless network with relay nodes. In: IEEE conference on computer communications (INFOCOM’14), pp 2427– 2435 19. Xu Y, Yang H, Ren F, Lin C, Shen X (2013) Frequency domain packet scheduling with MIMO for 3GPP LTE downlink. IEEE Trans Wireless Commun 12(4):1752–1761 20. Niafar S, Huang Z, Tsang DHK (2014) An optimal standard-compliant MIMO scheduler for LTE downlink. IEEE Trans Wireless Commun 13(5):2412–2421 21. LTE Feasibility study for Further Advancements for E-UTRA (LTE-Advanced) (3GPP TR 36.912 version 10.0.0 Release 10), 2011 22. Lee SB, Choudhury S, Khoshnevis A, Xu S, Lu S (2009) Downlink MIMO with frequencydomain packet scheduling for 3GPP LTE. In: IEEE conference on computer communications (INFOCOM’09), pp 1269–1277

Secure Routing Protocol for MANET: A Survey K. J. Abhilash and K. S. Shivaprakasha

Abstract In recent years, the interest in wireless networks has seemingly increasing because of the extensive growth in wireless communication devices. Mobile ad hoc network (MANET) is proved to be one of the emerging wireless network variants because of its unique characteristics such as decentralized nature and dynamic feature. MANET is a collection of wireless devices that are rapidly deployed on go without any fixed infrastructure forming a multi-hop network with the absence of centralized administration. Down the years, MANETs have posed many challenges to researchers in the fields like routing, scheduling, mobility, energy efficiency, security, and so on. Security is a greater challenge for MANET, due to its dynamic behavior and continuously changing topology. In this paper, an attempt is made to provide an insight into the features of wireless ad hoc network system from the perspective of secure routing protocol. The paper not only presents the various attacks experienced in MANETs but also details various security solutions for routing protocols. Keywords MANET · Routing protocols · Security · Attacks

1 Introduction MANET is a collection of nodes that are deployed in a large geographical area. It is an infrastructureless network, and hence, the nodes have to cooperate among themselves for the data communication. The major challenges in MANETs include signal security, the reliability of portable devices and dynamic nature of nodes [1]. The wireless mobile nodes in MANET are capable of building temporary wireless network spontaneously in the absence of infrastructure like AP and router, and they act as a router as shown in Fig. 1. In this network, each node is capable of acting K. J. Abhilash (B) Department E & CE, Bahubali College of Engineering, Shravanabelagola, India e-mail: [email protected] K. S. Shivaprakasha Department E & CE, NMAM Institute of Technology, Nitte, India e-mail: [email protected] © Springer Nature Singapore Pte Ltd. 2020 S. Kalya et al. (eds.), Advances in Communication, Signal Processing, VLSI, and Embedded Systems, Lecture Notes in Electrical Engineering 614, https://doi.org/10.1007/978-981-15-0626-0_22

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Fig. 1 MANET example

as a “host” as well as a “router” to forward the traffic to other specified nodes in the network. The routers are allowed to move randomly and arrange themselves subjectively. Therefore, the network topology is subjected to change. In order to facilitate communication within the network, a routing protocol is used to discover routes between nodes. Routing in MANETs can be either proactive or reactive. The main motive of MANET is to support robust and efficient operation in wireless networks by implementing routing functionalities at each mobile node [2]. The reliability, effectiveness, security, and limit of remote connections are generally difficult to achieve in wireless networks in comparison with wired connections. A number of routing protocols have been proposed, and a few of them have been broadly used and implemented in various sorts of ad hoc networks like MANETs, WMNs, WSNs, VANETS, and so on. Additionally, there are essential optimization methods which help in improving network performance [3]. The main characteristics of MANETs could be listed as below, 1. Infrastructureless and self-organizing: MANET does not rely upon any centralized entity. Each node works in a distributed mode and organizes itself to dynamic nature of network and to its own mobility. 2. Multi-hop ad hoc forwarding: When a node tries to send information to another node which is out of its transmission range, the packet should be sent through the help of intermediate nodes. 3. Dynamic topology: As mobile ad hoc networks allow nodes to move freely, wireless devices like laptops, PDAs, cell phones dynamically form the framework topology, wherein communication might be unidirectional or bidirectional, which is usually multi-hop, subjected to frequent changes in the network topology. 4. Diversity and node abilities: Every node in the network can be diverse and unique in its capabilities.

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5. Bandwidth-constrained and variable capacity links: The network is operating solely on cooperative basis; the communication is facilitated over wireless communication links which is bandwidth constrained and capacity of link depends on transmission range capabilities on node since nodes are dynamic in nature. 6. Shared physical wireless medium: The nodes in the network are making use of shared wireless medium, a node with its radio interface abilities gains access to the open shared wireless channel. 7. Distributed mode operation: As MANET practices decentralized control, nodes present in a MANET should coordinate among themselves and should operate accordingly to facilitate specific tasks like directing and security. 8. Protocol diversity: Nodes can utilize diverse protocol standards, for instance, IrDA, Bluetooth, ZigBee, 802.11, GSM, or TCP/IP. 9. Self-healing: MANETs support connection failures, because mobility and transmission protocols are intended to deal with these circumstances. The rest of the paper is organized as follows: Sect. 2 gives an insight into the security aspects in MANETs, Sect. 3 details the various security attacks in MANET, Sect. 4 presents a comparative analysis of secure MANET routing protocols, and finally, Sect. 5 concludes the paper.

2 Security in Manets A MANET is a distributed decentralized network environment, wherein each node needs to rely on individual security solutions, and therefore, it is difficult to implement centralized security control. This nature of MANET makes it vulnerable to various forms of attack. Attacks take different forms as active and passive attacks from internal and external attacker posing various security challenges. There is a requirement to secure the MANET from threats and vulnerability. The random nature of these networks necessitates the enforcement of security features. As nodes in MANETs collaborate with their neighbors to propagate data, allowing malicious nodes to establish collaboration with normal nodes to disturb network operation and reduce its efficiency is likely to happen [4]. Vulnerabilities like threats from compromised nodes inside the network, limited physical security, distributed coordination, open and shared physical wireless channel, constrained resource and highly dynamic network topology, scalability and absence of centralized control and its infrastructureless dynamic environment make MANET more prone to malicious attacks [5]. The malignant nodes attack other network nodes and thereby exploit dynamic nature of the network to avoid being detected by other nodes in MANETs. Some nodes in network might try to save their energy and start to exhibit malicious activities such as dropping the packet while forwarding, etc. Such security problems in the network make routing also inefficient. Hence to improve the routing efficiency along with security, several techniques have been used so far [6].

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A specific goal is to ensure MANET’s security. Security issues in MANETs will remain a potential research field. Potential security mechanism has to ensure following service prerequisites to set up secure association between other nodes: 1. Authentication: Authentication is the confirmation that sender and receiver or modifier in correspondence is ideal individual and impersonators if any should be identified. 2. Authorization: The legitimate user has to be accredited by a declaration specialist. 3. Availability: Availability expresses that the node should be ready to give all the fused administrations regardless of the security state. The security standard is tested amid the denial-of-service (DoS) assaults making the system administrations inaccessible. 4. Integrity: Integrity affirms the identity of the message when they are sent on the channel. 5. Anonymity: Anonymity/vagueness exhibits all information which can be utilized to perceive current or proprietor client nodes. Data about such nodes must be held by and should not to be scattered by the system device/programming or the node itself. 6. Non-repudiation: This ensures that transmitter and recipient of a message cannot deny; they have really passed on or gotten this sort of idea. 7. Confidentiality: The process of ensuring that the secret information is kept riddle from all substances.

3 Security Attacks in Manet The intruder can initiate the attack either within or from outside the network, based on which the attacks may be categorized as insider or outsider attacks. Same time the attacker may choose to just observe or analyze the information being shared forming a passive attack or choose to modify the information forming an active attack [7]. A. Types of Attacks The security attacks in MANETs can be broadly listed into two categories: Passive attack: In this type of attack, the intruder just plays out some sort of monitoring the information exchange without infusing any fake information. Passive attacks are traffic analysis, eavesdropping, etc. Active attack: In this sort of attack, the attacker plays out a successful impeachment on either the network resources or the information transmitted. Active attacks are black hole, gray hole, wormhole, Byzantine, flooding, and others. B. Attacks on Different Layers The various possible attacks across different layers of the network are as shown in Table 1.

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Table 1 Different types of attacks at different network layers Layers

Attacks

Application layer

Repudiation, data corruption

Transport layer

Session hijacking, sync flooding

Network layer

Wormhole, black hole, gray hole, Byzantine, flooding [8], resource consumption [9], location disclosure, Sybil attack, jellyfish, fabrication, modification attack

Data link layer

Traffic analysis, monitoring, disruption MAC(802.11), WEP weakness, selfish node

Physical layer

Jamming, interception, eavesdropping

Multi-layer attacks

Dos attacks, impersonation, replay, man-in-the-middle

4 Secure Manet Routing Protocols Routing is one of the prime concerns in MANETs because of decentralized framework. Many routing strategies are proposed to perform efficient routing. Position based, proactive, reactive, topology based, and hybrid are the familiar routing strategies of MANET. Based on the route discovery process, the routing in MANETs is classified as either proactive or reactive protocols. On the other hand, based on the type of the data forwarding from source to destination, it is classified as direct, multi-hop, and cluster-based routing. Distributed control in MANETS poses major challenges in routing. Thus in securing the routing protocol, majority of protocols use the cryptography. Only trusted nodes are allowed to participate in the routing process. Authentication techniques were implemented to discover trusted nodes. These trusted nodes work adhering defined rules of protocol. Authentication can be implemented using symmetric, public key, or digital signature techniques [10]. Secure routing protocol provides the reliable and accurate path in the presence of untrusted network or malicious attackers. This section provides an insight into various secure routing protocols proposed in the literature [11]. A comparative analysis of the same is also presented. 1.

2.

Anonymous Location-Aided Routing in MANET (ALARM) is an anonymous secure location-based routing protocol. ALARM constructs network topology by finding node’s current location by flooding the Location Announcement Message (LAM) throughout the MANET to construct topology. The proposed technique is based on advanced cryptographic group signatures, a public-key signature which offers both security and privacy. ALARM facilitates network services such as authentication, integrity, anonymity, and un-traceability. Authenticated anonymous secure routing (AASR) protocol immunes the network from the various security attacks. In AASR, route request packets are authenticated using group signature at each node. Discovered routes were

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recorded using key encryption mechanism, and route request and route reply were verified by encryption using secret information. Robust secure routing protocol (RSRP) based on the asymmetric cryptography, RSA with Chinese remainder theorem (CRT) in which decryption process is performed quickly in modular exponentiation. Probable routes were discovered using Shamir’s secret sharing principle of RSA. The mechanism only discovers stable and trustworthy routes. This protocol also reduces the key generation complexity by using RSA along with CRT instead of conventional RSA. Hence, the routing becomes less expensive and secure. Hash-based Anonymous Secure Routing (HASR) is based on the design of collision-resistant one-way hash function and pseudo-name generation mechanism together similar to AODV. As HASR does not apply cryptography on data or key, its computation requirement and network bandwidth requirement for performing routing functions are less. HASR implements anonymity and secure communication. HASR offers immunity against replay attack, spoofing attack, route maintenance attack, and DoS attack. Secure AODV (SAODV) uses conventional public-key cryptography for securing the AODV routing protocol. In SAODV, routing information is authenticated using hash chains and digital signature techniques. Digitally signed route request (RREQ), route reply (RREP), and route error (RERR) messages were used in route discovery and maintenance phases. This digital signature is validated at every node cryptographically. Digital signatures are appended with routing messages exchanged. SAODV provides authentication and integrity of security services. Key distribution is complicated for establishing a new node in the network. Adaptive SAODV (A-SAODV) is modified protocol based on SAODV. ASAODV is designed using an asymmetric key cryptography protocol which optimizes the performance. Parallelism is implemented using thread functionality for cryptographic operation in A-SAODV to reduce processing time. Thread concept is implemented in two levels: one for cryptography operation and second for other functions like processing and management of routing message, routing table, and generation of the message. These threads digitally verify messages in a FIFO queue. Double signature is optional feature in A-SAODV. In SAODV, nodes were expected to be overloaded as there was a need for double cryptography signatures. Fuzzy petri net (FPNT)-OLSR an integration of trust-based routing mechanism and data forwarding process to achieve secure routing. It operates on the foundation of trust-based routing mechanism for selecting a path based on maximum trust value among all possible paths. The trustworthiness of the nodes is evaluated on the basis of fuzzy rules. The algorithm considers load, packet forwarding rate, average forwarding delay, protocol deviation flags as trust parameters while evaluating the trust of nodes using fuzzy petri net. IBE-RAOLSR is based on radio-aware OLSR (RAOLSR) and identity-based encryption (IBE) to secure the OLSR protocol. The design of IBE-RA-OLSR scheme counters the vulnerabilities of RA-OLSR and at the same time does

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not introduce additional overhead. IBE signature secures hello and topology control (TC) messages of OLSR by removing the authenticity verification of public keys. In reputation-based clustering (RBC) scheme, residual energy and connectivity index of nodes are the metrics used for the selection of MPR and cluster head, respectively. An election algorithm is presented for selecting a cluster head. Trust value of path is evaluated based on trust of the nodes’ reputation in the presence of selfish nodes. Trust-based source routing protocol (TSR) is a source initiated on-demand trust routing protocol. It has been shown that TSR performs better than DSR and TDSR. The trust prediction model computes the trust value which might be direct trust or indirect trust. Direct trust is on the basis of received information from neighbors which is easy to gather. Indirect trust is the information received from other nodes such as recommended trust of the third party. It is assumed that at initial phase of protocol, every node in the network is authenticated and direct trust is used for the algorithm. During the process, trust is continuously monitored. If the trust of a neighbor node goes below a threshold, then it is listed as black node. The dynamic trust prediction model based on nodes’ historical and future behaviors using extended fuzzy logic rules prediction is used. Cluster-based secure routing protocol (CBSRP) offers secure routing and key management in MANET by using digital signature and one-way hashing function. It is a hierarchical secure routing protocol that forms small clusters of four to five nodes, each having a temporary cluster head and member nodes. Oneway hashing function is used for nodes within a cluster and digital signatures are used for cluster-to-cluster authentication. Cluster-based trust-aware routing protocol (CBTRP) is an on-demand source trust-based cluster routing protocol for securing routing process. In this protocol, the whole network is organized into one-hop disjoint clusters and cluster head is elected on the basis of its trustworthiness. The data forwarding from member nodes of clusters happens only through the trusted cluster heads. Secure zone routing protocol (SZRP) uses digital signature and encryption techniques that provide security for the zone routing protocol (ZRP). SZRP uses both the symmetric and asymmetric key encryption techniques. It offers the integrity, confidentiality, and end-to-end authentication. SZRP effectively operates in the presence of internal and external attack conditions. The trust of nodes calculated on basis of nodes performance such as misbehave and drop data packet. Fuzzy Logic Secure AODV (FL-SAODV) exploits fuzzy logic for securing AODV routing protocol. FL-SAODV works on the assumption of each neighbor node having a secret key. Security association is established with neighbor nodes first, followed by authentication of packet using message digest. This strategy depends upon the knowledge of secret key and node’s behavior like bandwidth consumption and number of neighbor nodes. Security level of a node is computed on the basis of fuzzy reasoning system using the analysis and knowledge.

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14. Q-learning-based trust ABR (QTABR) is a secure algorithm based on associativity-based routing (ABR) which solely depends on associativity as a measure of connectivity among neighbor nodes. For participating in routing, a node must satisfy node’s observed associativity. Q-learning technique is proposed to score the trust of neighbor nodes in trust evaluation table (TET). QTABR exhibits reduced route selection time and increased end-to-end packet delivery in comparison of ABR protocol. 15. Secure destination-sequenced distance vector (SDSDV) protocol is a secure variant of DSDV which uses two one-way hash chains. A routing table entry of DSDV contains hop count and fresh sequence number. These two fields play an important role in the operation of DSDV. Malicious node can disturb protocol operation by either modifying hop count or sequence number. By implementing two one-way hash chain mechanisms, hop count and destination sequence number are protected from malicious nodes. Two additional fields, alteration (AL) and accumulation (AC), were added to improve the security. 16. Trust ad hoc on-demand multipath distance vector (T-AOMDV) is a trustaware multipath routing protocol. This scheme performs soft encryption using bitwise XOR for securing message of the sender node. After that, the sender node utilizes trust model to discover the secure path. Path trust is computed on the basis of trust values assigned to nodes by trust model. Data sensitive level of source node is classified into secret class and confidential class. Routing is implemented on selection of a particular path for transmission based on its class and path trust. 17. Trust-enhanced routing table (TRT): In this algorithm, a module is included to measure a reliable metric for the routes. Secure route is mapped by security associations (SAs) with the authenticated (trusted) nodes. In this approach, Rank Base Data Routing (RBDR) scheme is used for the detection and prevention of packet drop attack in AOMDV routing protocol. Rank-based data routing record is used to identify malicious node, and algorithm avoids the malicious path to prevent packet drop attack. 18. Topology-hiding protocol (TOHIP) operates in the multipath based on topology-hiding concept. TOHIP does not maintain link connectivity in route, thus countering the network topology-based attacks. TOHIP can discover the secure multiple disjoint paths by excluding the malicious nodes in routes. TOHIP has proved to be efficient to find routes and increase packet delivery ratio even in the presence of malicious nodes. Table 2 outlines the proposed secure routing protocols. Cryptography, game theory, reputation, trust, fuzzy reasoning, etc., are the various mechanisms for securing routing protocol. Among these, some approaches are able to find reliable single or multi-paths, some are able to find only trusted path, and some are able to find a secure path in the presence of outsider and insider attacks by sharing security keys.

Routing protocol

–

–

–

–

AODV

AODV

Security algorithm proposed

ALARM [12]

AASR [13]

RSRP [14]

HASR [15]

SAODV [16]

A-SAODV [17]

Table 2 Secure routing protocols proposed

Hop count

Hop count

Hop count

Battery power, mobility, and trust value

Hop based

Route metric Source routing √

√

√

√

√

√

Table-driven routing

Topology information

Double signature mechanism and reply by only non-overloaded intermediate nodes

Public-key cryptography, hash chain, digital signature

Collision-resistant one-way hash function and pseudo-name generation/exchange mechanism

RSA-CRT cryptography

Key encrypted onion routing group signature

Group signature

Security technique used

(continued)

Authentication integrity and reduced the overhead of SAODV

Authentication and integrity

Replay attack, spoofing attack, route maintenance attack, and DoS

Passive attacks, impersonation attacks, DoS attacks

Active attacks without revealing nodes identity

Active, passive and external, internal attacks

Countered attacks

Secure Routing Protocol for MANET: A Survey 271

Routing protocol

OLSR

OLSR

OLSR

–

Security algorithm proposed

FPNT-OLSR [18]

IBE-RA-OLSR [19]

RBC-OLSR [20]

TSR [21]

Table 2 (continued)

Hop count, trust value, and path trust

Nodes’ reputation and hop count

Hop count

Hop count

Route metric

√

√

√

Source routing √

Table-driven routing

Topology information

Dynamic trust prediction model based on nodes’ historical behavior and future behavior via extended fuzzy logic rules’ prediction

Nodes’ reputation, residual energy level, and connectivity index of the nodes

Identity-based encryption (IBE)

Fuzzy petri-net trust based

Security technique used

(continued)

Attack resistance, malicious nodes’ identification, and their exclusion

Selfish nodes’ identification

Reduced overhead compared to RAOLSR

Outperforms OLSR in terms of packet delivery ratio, average latency, and overhead even in the presence of malicious node

Countered attacks

272 K. J. Abhilash and K. S. Shivaprakasha

Routing protocol

DSR

–

ZRP

ZRP

ZRP

OLSR

Security algorithm proposed

CBSRP [22]

CBTRP [23]

SZRP [24]

[25]

[26]

[27]

Table 2 (continued)

Hop count

Hop count

Hop count

Hop count

Trust

Hop count

Route metric

√

√

√

√

√

Source routing √

Table-driven routing

Topology information

Trust based

ZRP with trust based and HMACSHA256

Node trust based

Digital signature, symmetric, and asymmetric encryption

Distinguish trusted nodes from malicious, one-hop disjoint clusters of network are formed

Digital signature, one-way hash function

Security technique used

(continued)

Isolate the misbehaving nodes

Avoid misbehaving nodes, authentication and integrity

Avoid misbehaving nodes

Integrity, confidentiality, and end-to-end authentication in the presence of internal and external attacks

Intermediary malicious nodes

Malicious nodes’ identification

Countered attacks

Secure Routing Protocol for MANET: A Survey 273

Routing protocol

AODV

ABR

DSDV

AOMDV

AOMDV

AOMDV

–

Security algorithm proposed

FL-AODV [28]

QTABR [29]

SDSDV [30]

T-AOMDV [31]

[32]

RBDR [33]

TOHIP [34]

Table 2 (continued)

Hop count

Reliability metric, time stamp, session key, and hop count

Hop count

Hop count

Weighted average of the trust value of the nodes and hop count

Hop count

Route metric Source routing

√

√

√

√

√

√

Table-driven routing √

Topology information

Topology hiding

Rank-based data record

Policy-based SAs

Trust model, soft encryption using XOR

Two one-way hash chains

Q-learning-based trust

Fuzzy logic, message digest (MD)

Security technique used

Black hole attack, rushing attack, wormhole attack, sybil attack

Packet drop attack

Securing routing messages

Malicious nodes’ identification

Protection from malicious nodes

Misbehaving nodes’ identification

Trust calculation and authentication

Countered attacks

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5 Conclusion The characteristics and features of MANET make it vulnerable to various attacks from inside or outside the network in active or passive form. In this paper, an attempt is made to discuss various secure routing protocols proposed for MANETs and a comparative analysis of the same has been carried out. No single approach is ideal to secure MANET against various attack types. As attacks are possible at different phases of communication such as routing, data transmission, and forwarding, there is a need for security mechanism to counter malignant activities in all these phases. To secure the data transmission, cryptographic techniques could be implemented as a first level of defense. The intrusion detection systems (IDS [35]) can monitor the network as a second line of defense, which are specific to an application [36]. Cryptographic methods and IDS in MANETs can offer protection to both control and data message transmission. On the other hand, secure routing algorithms can protect the routing specific information and enable dynamic reliable route discovery [37]. Security mechanisms such as fuzzy logic, game theory, trust metrics could be implemented along with cryptography at first line of defense during route discovery phase and data transmission phase. Nevertheless, the network performance in terms of QoS parameters may suffer because of security mechanisms. Thus, there is a need for a QoS-aware secure routing, as major applications today in real-time scenarios are based on MANET. Thus, MANETs’ success on greater scales depends on its security features toward new applications.

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11. Papadimitratos P, Haas ZJ (2016) Secure message transmission in mobile ad hoc networks. Int J Found Comput Sci Technol 6(1), January 12. El Defrawy K, Tsudik G (2011) ALARM: anonymous location-aided routing in suspicious MANETs. IEEE Trans Mob Comput 10(9):1345–1358 13. Wei L, Yu M (2011) AASR: authenticated anonymous secure routing for MANETs in adversarial environments. IEEE Trans Veh Technol 63(9):4585–4593 14. Sinha D, Bhattacharya U, Chaki R (2014) RSRP: a robust secure routing protocol in MANET. Found Comput Decis Sci 39(2):129–154 15. Lo NW, Chiang MC, Hsu CY (2015) Hash-based anonymous secure routing protocol in mobile ad hoc networks. In: IEEE 10th Asia joint conference on information security (Asia JCIS), pp 5–62 16. Lupia A, De Rango F (2015) Performance evaluation of secure AODV with trust management under an energy aware perspective. In: IEEE international symposium on performance evaluation of computer and telecommunication systems (SPECTS 2014), Monterey, pp 599–06 17. Zapata MG, Asokan N (2002) Securing ad hoc routing protocols. In: proceedings of the 1st ACM workshop on wireless security, NY, pp 1–10 18. Cerri D, Ghioni A (2008) Securing AODV: the A-SAODV secure routing prototype. IEEE Commun Mag 46(2):120–125 19. Tan S, Li X, Dong Q (2015) Trust based routing mechanism for securing OSLR-based MANET. Ad Hoc Netw 30:84–98 20. Ben-Othman J, Benitez YIS (2012) A new method to secure RA-OLSR using IBE. In: IEEE global communications conference (GLOBECOM), Anaheim, CA, pp 354–58 21. Robert JM, Otrok H, Chriqi A (2012) RBC-OLSR: reputation-based clustering OLSR protocol for wireless ad hoc networks. Comput Commun 35(4):487–499 22. Xia H, Jia Z, Li X, Ju L, Sha EHM (2013) Trust prediction and trust-based source routing in mobile ad hoc networks. Ad Hoc Netw 11(7):2096–2114 23. Morshed MM, Islam MR (2013) CBSRP: cluster based secure routing protocol. In: IEEE 3rd international advance computing conference (IACC), Ghaziabad, pp 571–76 24. Safa H, Artail H, Tabet D (2010) A cluster-based trust-aware routing protocol for mobile ad hoc networks. Wireless Netw 16(4):969–984 25. Pan NK, Mishra S (2014) Secure hybrid routing for MANET resilient to internal and external attacks. In: ICT and critical infrastructure: proceedings of the 48th annual convention of computer society of India, vol 1. Springer International Publishing, pp 449–58 26. ElRefaie Y, Nassef L, Saroit IA (2012) Enhancing security of zone-based routing protocol using trust. In: IEEE 8th international conference on informatics and systems (INFOS), Cairo, pp 32–39 27. Rahman MT, Mahi N, Julkar M (2014) Proposal for SZRP protocol with the establishment of the salted SHA-256 bit HMAC PBKDF2 advance security system in a MANET In: IEEE international conference on electrical engineering and information & communication technology (ICEEICT), Dhaka, pp 1–5 28. Adnane A, Bidan C, de Sousa Júnior R T (2013) Trust-based security for the OLSR routing protocol. Comput Commun 36(10):1159–1171 29. Zhang Z (2011) A novel secure routing protocol for MANETs. InTech, pp 455–66 30. VijayaKumar A, Jeyapal A (2014) Self-adaptive trust based ABR protocol for MANETs using q-learning. Sci World J pp 120–25 31. Wei WJ, Chen HC, Lin YP (2013) A secure DSDV routing protocol for ad hoc mobile networks. In: IEEE 5th international joint conference on INC, IMS and IDC, Seoul, pp 2079–2084 32. Huang JW, Woungang I, Chao HC, Obaidat MS, Chi T Y Dhurandher SK (2011) Multi-path trust-based secure AOMDV routing in ad hoc networks. In: IEEE global telecommunications conference (GLOBECOM 2011), Houston, Tx, USA, pp 1–5 33. Sumaiya V, Patel R, Patel N (2015) Rank base data routing (RBDR) scheme using AOMDV: a proposed scheme for packet drop attack detection and prevention in MANET. In: IEEE international conference on electrical, computer and communication technologies (ICECCT), Coimbatore, pp 1–5

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34. Zhang Y, Yan T, Tian J, Hu Q, Wang G, Li Z (2014) TOHIP: A topology-hiding multipath routing protocol in mobile ad hoc networks. Ad Hoc Netw 21:109–122 35. Khan S, Loo KK, Din ZU (2010) Framework for intrusion detection in IEEE 802.11 wireless mesh networks. Int Arab J Inf Technol 7(4):435–440 36. Rafsanjani MK, Movaghar A, Koroupi F (2008) Investigating intrusion detection systems in MANET and comparing IDSs for detecting misbehaving nodes. World Acad Sci Eng Technol 20:351–355 37. Salmanian M, Li M (2012) Enabling secure and reliable policy-based routing in MANETs. In: IEEE military communications conference, Orlando, FL, pp 1–7 38. Ramanujan R, Ahamad A, Bonney J, Hagelstrom R, Thurber K (2000) Techniques for intrusionresistant ad hoc routing algorithms (TIARA). In: MILCOM 2000. 21st century military communications conference proceedings, Vol. 2. pp 660–664 39. Patel R, Kamboj P (2017) A survey on contemporary MANET security: approaches for securing the MANET. Int J Eng Technol, February

Improved HMM-Based Mixed-Language (Telugu–Hindi) Polyglot Speech Synthesis M. Kiran Reddy and K. Sreenivasa Rao

Abstract Speech synthesis research has recently focused on developing polyglot speech synthesizers for handling mixed-language sentences. Polyglot speech synthesis systems are particularly essential in multilingual countries like India. This paper aims at enhancing the quality of hidden Markov model (HMM)-based polyglot synthesizer for the two popular Indian languages (Telugu–Hindi) by incorporating an advanced excitation modeling approach. Experimental results show that the voice quality of our mixed-language synthesizer is significantly better than the baseline systems. Keywords Speech synthesis · Excitation model · Mixed-language polyglot synthesis · Hidden Markov models

1 Introduction Text-to-speech synthesis (TTS) system takes text as input and produces corresponding speech utterance at the output. Statistical parametric speech synthesis (SPSS) based on hidden Markov models (HMMs) [1] or deep neural networks (DNNs) [2] has grown in popularity in recent years. It performs statistical modeling of the speech parameters (e.g., source and vocal-tract filter parameters) by using HMMs/DNNs. The main advantages of this technique are (1) flexibility in modifying various emotions, speaker identities, and speaking styles and (2) smaller memory footprint and computational resources. The conventional HMM-based speech synthesis system (HTS) usually generates speech for the language on which is trained, viewed as monolingual HTS. In multilingual countries, HTS systems often have to deal with texts consisting of two or M. K. Reddy (B) · K. S. Rao Department of Computer Science and Engineering, Indian Institute of Technology Kharagpur, Kharagpur, India e-mail: [email protected] K. S. Rao e-mail: [email protected] © Springer Nature Singapore Pte Ltd. 2020 S. Kalya et al. (eds.), Advances in Communication, Signal Processing, VLSI, and Embedded Systems, Lecture Notes in Electrical Engineering 614, https://doi.org/10.1007/978-981-15-0626-0_23

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more languages in the form of phrases, words, or parts of words. In India, people frequently include Hindi language words during conversations along with their native language. Hence, current research focus is on developing polyglot TTS systems, for synthesizing mixed-language text appropriately. The task of synthesizing speech corresponding to an input mixed-language or monolingual text in the voice of a single speaker [3] is termed as polyglot speech synthesis. In literature, some efforts have been made to develop mixed-language TTS systems [3–6]. The existing mixed-language synthesizers can produce intelligible speech, but the synthesized utterances sounds degraded. This is because a mixed-language synthesizer is conventionally built using either traditional pulse-based or STRAIGHT-based excitation modeling approaches [1, 7]. In pulse-based approach [1], only pitch (F0 ) is used for modeling and generating the excitation signal. During synthesis, a pulse sequence and white noise are used as voiced and unvoiced excitation signals, respectively. Hence, buzziness can be perceived in the synthesized speech. In STRAIGHT-based method [7], the excitation signal is modeled by using five-dimensional band a-periodicities (BAPs) besides fundamental frequency. During synthesis, mixed excitation generated utilizing periodic impulses and BAPs is used as excitation for voiced speech, and for unvoiced speech, white noise is taken as excitation signal. Though the excitation constructed using STRAIGHT-based method is better than the impulse train, it is still far from the natural excitation signal. Recently, an inverse filter-based excitation model is proposed in [8]. This approach can generate more realistic excitation signals and has shown notable enhancement in the quality of monolingual HTS compared to pulse and STRAIGHT-based excitation models. In this paper, we have incorporated this promising excitation modeling approach [8] into Telugu–Hindi bilingual SPSS, for enhancing synthesized speech quality. Through subjective tests, we validate the effectiveness of our bilingual speech synthesizer. The rest of this paper is organized as follows. The inverse filter-based excitation model is explained in Sect. 2. Section 3 explains the baseline and proposed bilingual SPSS systems. The details of performance evaluation of the bilingual synthesizers are given in Sect. 4. Section 5 concludes the present work.

2 Inverse Filter-Based Excitation Model HTS depends on source-filter representation for speech modeling, in which the speech signal s(n) can be interpreted as the convolution of two components: s(n) = e(n) ∗ h(n), where h(n) and e(n) denote the vocal-tract spectrum and source signal, respectively. The excitation source carries speaker and phone-specific information, and it is essential for preserving the intelligibility and quality. The inverse filter-based excitation model [8] tries to capture the necessary characteristics of the excitation signal using features derived from the residual signal. Following are the steps in excitation modeling and generation:

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(1) Apply Mel-generalized log spectrum approximation (MGLSA) inverse filtering to derive the residual signal. (2) Divide the residual signal into frames with a frame size of 25 ms and shift of 5 ms. (3) Extract two excitation source parameters: 10th order linear prediction coefficients (LPCs) and energy from each frame. (4) Train the excitation parameters under HMM framework. During synthesis, the excitation signals for voiced and unvoiced frames are constructed separately by utilizing the target parameters generated from HMMs [8]. For voiced frame, the excitation signal is synthesized in two steps: (1) The natural residual segment (estimated from steady state portion of a vowel during training) is pitch synchronously overlap added to reconstruct the source signal. (2) The generated source signal is further modified to incorporate the target excitation parameters given by HMMs [8]. For unvoiced frames, the excitation corresponds to the white noise altered according to the parameters generated from HMMs. Figure 1 illustrates the voiced excitation signals generated with various excitation modeling approaches. Figure 1a shows the natural residual signal, and the residual signals constructed using pulse-based, STRAIGHT-based, and inverse filter-based excitation modeling methods are shown in Fig. 1b, c and d, respectively. From the figure, it can be seen that the inverse filter-based model constructs excitation signal much closer to the natural one (shown in Fig. 1a), which aids in the synthesis of better quality speech.

Fig. 1 a Natural excitation signal, b excitation constructed using pulse-based model, c excitation constructed using STRAIGHT-based model, and d excitation reconstructed by inverse filter-based excitation model

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3 Telugu–Hindi HMM-Based Polyglot Speech Synthesizers 3.1 Speech Database In this paper, the polyglot speech corpus record by a native Telugu Female speaker who can fluently speak Hindi and Telugu [6] is used for building the polyglot TTS systems. Recording is done in a studio environment by setting sampling rate at 16 kHz. The corpus consists of sentences from news bulletins, short stories, and sports. The total duration of the training data is about 2 h. (1 h for each language). Since, the considered languages (Hindi and Telugu) are phonetically closer, the phonetic transcriptions are derived using a common phone set as in [9].

3.2 Baseline System—I The speech synthesizers are implemented using the openly available HTS toolkit [10]. Figure 2 depicts the block diagram of baseline system. The HTS comprises of two main steps, namely training and synthesis.

Fig. 2 Conventional HMM-based speech synthesis system

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In training step, pitch (F0 ) and vocal-tract (spectral) parameters are computed from the speech utterances in the database. 35th order Mel-Generalized cepstral coefficients(MGCCs) represent the spectral parameters. F0 is extracted using the continuous wavelet transform (CWT)-based robust pitch extraction algorithm [11]. The speech parameters along with their dynamic features are obtained for every 5 ms. Continuous probability density HMM (CD-HMM) is used for modeling spectral features. Whereas, multi-space probability distribution HMM (MSD-HMM) is used to model F0 features, which consists of a mixture of discrete symbols and continuous values. For all the experiments, we used five-state left-right HMMs. Let q and O =  T T T T O1 , O2 , O3 . . . OTT denote the set of features and state sequence, respectively. The model parameters λ are estimated using maximum likelihood (ML) criterion as follows, λˆ = argmax P(O|q, λ) λ

(1)

During synthesis, corresponding to given text, sequences of context-dependent phoneme labels are constructed. The utterance HMMs are generated by concatenating context-dependent HMMs. The maximum likelihood parameter generation algorithm (MLPG) is used to generate the speech parameter sequence from the utterance HMM as follows:   ˆ = argmax P O|q, λˆ O (2) o

From the target pitch values, the excitation signal is generated using the traditional pulse-based excitation scheme [1] which generates a pulse train (controlled by F0 ) and white noise as voiced and unvoiced excitation, respectively. The constructed excitation signal and MGCCs are given as input to MGLSA synthesis filter to synthesize speech.

3.3 Baseline System—II Figure 3 shows the block diagram of baseline system-II which uses the STRAIGHTbased excitation model [7]. STRAIGHT is a vocoding technique which makes use of pitch-adaptive spectral smoothing performed in the time–frequency domain for speech representation, manipulation, and reconstruction. In STRAIGHT-based HTS, five BAPs along with F0 are used for modeling the excitation signal. The training and parameter generation are performed as in the baseline system. The generated BAPs and F0 are used for constructing the voiced excitation and white noise is used as unvoiced excitation [7]. The output speech is produced by passing the generated source signal as input to MGLSA filter.

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Fig. 3 HTS including inverse filter-based excitation model

3.4 Proposed System The proposed system uses the inverse filter-based excitation model [8]. Figure 4 shows the block diagram of proposed HTS. In addition to F0 and spectral parameters, two excitation parameters: energy and source spectrum are also extracted from training speech utterances. CD-HMM is used for modeling the excitation parameters. The training and parameter generation are performed as in the baseline system. The generated excitation parameters and natural residual segments are utilized for constructing the excitation of every frame, as discussed in Sect. 2. Finally, speech is synthesized by inputting the reconstructed excitation signal and MGCCs into MGLSA synthesis filter.

4 Experiments In this section, two subjective listening tests, namely preference test and mean opinion score (MOS) test [8] are used to assess the quality of the proposed and baseline bilingual polyglot TTS systems. Twelve evaluators aged between 24–31, having

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Fig. 4 HTS including STRAIGHT-based excitation model

enough expertise in rating the synthesized speech samples, participated in the subjective tests. Thirty sentences (comprising of 10 Hindi, 10 Telugu and 10 bilingual sentences) synthesized from all TTS systems have been used for evaluation. In preference tests, given a pair of synthesized samples, the evaluators have to prefer the one with better quality or prefer both as equal. In the case of MOS test, the evaluators were asked to rate the synthesized samples in terms of quality on a 5-point scale: 5-Very Good, 4-Good, 3-Fair, 2-Poor, and 1-Bad. For avoiding bias, the synthesized samples are played to the evaluators in random order. Tables 1 and 2 depict the MOS and preference scores, respectively. From Table 1, it can be seen that the average MOS scores obtained for baseline system-I and baseline system-II are lower than the MOS score for proposed system. The preference scores provided in Table 2 show that the evaluators preferred the proposed system for about 69% of cases. However, they preferred the baseline system-I in only about 15% of cases. The preference scores also indicate that the evaluators significantly preferred the proposed system over Table 1 Results of MOS Test

System

Baseline system-I

Baseline system-II

Proposed system

MOS

3.12

3.35

3.73

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Proposed system versus. baseline system-I

Proposed system versus. baseline system-II

Proposed system preferred (%)

68.5

47.3

Equivalent (%)

17.2

25.9

Proposed system preferred (%)

14.3

26.8

baseline system-II. The results of listening tests indicate that the quality of proposed bilingual polyglot synthesizer is superior compared to the baseline systems. The improvement in the quality of synthesized speech is due to generation of improved excitation signals in the proposed HTS.

5 Conclusion The speech synthesized with conventional mixed-language polyglot synthesizer sounds buzzy due to the usage of oversimplified excitation model. In this paper, the inverse filter-based excitation model is incorporated into the baseline polyglot HTS for two Indian languages: Telugu–Hindi, to improve the quality of synthetic speech. The results of MOS and preference tests show that the quality of our mixed-language polyglot synthesizer is significantly better compared to the baseline system. In future, we plan to use the advanced excitation model for deep neural network (DNN)-based polyglot synthesis and analyze the improvement in quality of synthesis.

References 1. Zen H, Tokuda K, Black AW (2009) Statistical parametric speech synthesis. Speech Commun 51(11):1039–1064 2. Zen H, Senior A, Schuster M (2013) Statistical parametric speech synthesis using deep neural networks. In: Proc. ICASSP, Vancouver, Canada, pp 7962–7966 3. Solomi V, Christina S, Rachel G, Ramani B, Vijayalakshmi P, Nagarajan T (2013) Analysis on acoustic similarities between Tamil and English phonemes using product of likelihood-Gaussians for an HMM-based mixed-language synthesizer. In: Proc. IEEE OCOCOSDA/CASLRE, Gurgaon, India, pp 1–5 4. Qian Y, Cao H, Soong FK (2008) HMM-based mixed-language (Mandarin-English) speech synthesis. In: Proc. INTERSPEECH, Brisbane, Australia, pp 4460–4464 5. Justin T et al. (2012) A bilingual HMM-based speech synthesis system for closely related languages. In: Proc. TSD, Czech Republic, pp 543–550 6. Reddy MK, Rao KS (2018) DNN-based bilingual (Telugu–Hindi) polyglot speech synthesis. In: Proc. ICACCI, Bangalore, India, pp 1808–1811 7. Zen H, Toda T, Nakamura M, Tokuda K (2007) Details of the Nitech HMM-based speech synthesis system for the Blizzard challenge 2005. IEICE Trans Inf Syst 90(1):325–333

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8. Reddy MK, Rao KS (2018) Inverse filter based excitation model for HMM-based speech synthesis system. IET Signal Proc 12(4):544–548 9. Ramani B et al. (2013) A common attribute based unified HTS framework for speech synthesis in Indian languages. In: Proc. SSW, Barcelona, Spain, pp 291–296 10. “HMM-based speech synthesis system (HTS).” [online]. Available:http://hts.sp.nitech.ac.jp/ 11. Reddy MK, Rao KS (2017) Robust pitch extraction method for the HMM-based speech synthesis system. In: IEEE signal processing letters, vol. 24. no. 8, pp 1133–1137

Energy Harvesting Using Raindrops Through Solar Panels: A Review Shreya Shetty, Vibha Kishore, Sinaida Reeya Pinto and K. B. Bommegowda

Abstract Energy is important for almost all activities and therefore plays a vital role in all aspects of day to day life. Life is hard to imagine without energy. Currently, most energy is produced from non-renewable sources like oil, coal, natural gas, petroleum, uranium, etc. These exhaustible energy sources contaminate our air and water, damage the earth’s climate, and destroy balanced eco-system and put human health in danger. This energy which is generated from non-renewable energy sources is harmful, is costly and gets finished fast. This problem can be overcome by using the renewable energy sources which can safeguard our health, wealth and climate. That is, by the use of clean, renewable energy such as the sun, hydro and wind energy. These renewable energy sources are abundantly available in nature, free of cost, reusable and inexhaustible. Among these, water is one of the abundant sources from which energy can be exploited for different purposes. Till now, there are different techniques which generate electricity from flowing water. Even the falling rainwater has the potential which can be used for various applications. This idea can be collaborated with already existing solar panels for better harnessing of the energy. Since these sources do not use these exhaustible fuels, the costs and price alterations are not a problem. Keywords Renewable energy · Energy harvesting · Raindrop energy · Graphene

S. Shetty (B) · V. Kishore · S. R. Pinto · K. B. Bommegowda Department of Electronics and Communication, Nitte Mahalinga Adyanthaya Memorial Institute of Technology, Udupi, India e-mail: [email protected] V. Kishore e-mail: [email protected] S. R. Pinto e-mail: [email protected] K. B. Bommegowda e-mail: [email protected] © Springer Nature Singapore Pte Ltd. 2020 S. Kalya et al. (eds.), Advances in Communication, Signal Processing, VLSI, and Embedded Systems, Lecture Notes in Electrical Engineering 614, https://doi.org/10.1007/978-981-15-0626-0_24

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1 Introduction The renewable energy generated from natural sources such as solar, wind, wave and rain is exclusively known as green energy. Nowadays, green energy is mainly used in four different areas such as water heating, fuels for automobiles, daily energy requirements and power production. Nearly, one-fifth of the power produced from electricity across the world can be supplied by renewable energy sources. Countries such as Paraguay, Iceland and Norway produce most of their energy from renewable energy sources [1]. Maximum of electricity in India is produced from hydroelectric power. Hydroelectric power is generated when waterfalls over the turbines from a height. In India, in 2012 nearly 21.53% of the electricity was produced using hydroelectric power. This hydroelectric power is particularly generated by the dam projects in large scale which blocks the water flowing with high pressure and by passing this water over the turbines. Likewise, solar power is also highly popular. It is clean, efficient and renewable source of energy production. When sun shines on the photovoltaic (PV) cells, energy is generated. However, when there is partial or shaded sun, the energy generated will be less. This problem can be solved by designing the maximum power point tracker (MPPT) system. MPPT is an electronic system used in solar electric charge controllers. Irrespective of the changes in environmental conditions the MPPT systems can generate electricity from solar PV cells. These solar panels, with MPPT system, can now be improved to generate power even from rain. Since 2012, the cost of production of these solar panels has decreased dramatically. The International Energy Agency forecasts that within 2040, the green energy sources will contribute nearly 40% of the total generated power in the world [2]. The hybrid solar panel is designed to generate electrical power from both the sun and the water. This hybrid device uses eco-friendly concepts and utilizes naturally available resources to produce electricity. The drawback of trivial solar panels is its disability to produce electricity under rainy conditions. This drawback can be overcome to a small extent by collaborating it with some materials that are capable of producing electricity from rain such as triboelectric nano generator (TENG), graphene, etc.

2 Design Solution Used for Harvesting Energy from Raindrops India gets good amount of rainfall using which large measure of hydroelectric power can be generated. India generates hydroelectric potential of approximately 37,367.4 mW per year and ranks 5th in global scenario [3]. Electricity can be generated by utilizing the energy in falling water. Nearly, 5% of the primary power requirements are produced by hydroelectric power which is an inexhaustible source of energy. Modern hydroelectric stations are used to produce more than 80% of inherent power from water to generate electricity. But the fossil fuel power stations

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differ from energy generation from these green sources because of their large energy losses [4–6]. One of the mechanisms of converting energy of rainfall into electricity is by running the collected rainwater through a turbine. Trapping the kinetic energy directly from the falling rain is the one more method of generating power. Kinetic energy from the object is equal to half of the mass times the velocity squared. The velocity of rain is limited by air resistance and has a maximum velocity around 8 m/s [7]. After the required calculation, the quantity of kinetic energy acquired from the rainfall on a 185 m2 roof is approximately about 59.2 kJ/cm (0.016 kWh/cm) of rain. But this power is only about 1.6 kWh of energy per year in the places that get about a meter of rainfall per year [8].

2.1 Piezoelectric Transducer Piezoelectricity, also known as piezoelectric effect, is an ability to convert mechanical energy into electrical energy, which generates alternating current and voltage with the help of certain ceramics and quartz which are non-conducting substances. These materials when subjected to vibration due to AC voltage, pressure or any other mechanical oscillations. The capability of these piezoelectric objects in order to convert from mechanical to electrical energy depends upon its crystalline structure with absence of center of symmetry in the crystal [9]. Piezoelectricity concept is used to convert vibration energy of falling rainwater into electricity. When the raindrop falls on the piezoelectric material with a certain pressure, these piezoelectric substances will start vibrating. And the charge Q is generated by this vibrating piezoelectric material. The generated charge is collected in between the two electrode plates. A voltage U is created across these plates according to the equation given below U = Q/Cpiezo

(1)

where the capacitance C piezo = 2r 2o A/t, 2o is the electrical permittivity in free space, 2r is the relative permittivity of the medium present in between the two plates, A is the total area of the electrode and t is the patrician between the electrode plates. By this, the generated power energy can be found using P = E/timpact

(2)

here the stored energy E = C piezo U 2 /2 with t impact being the time taken by the raindrops to effect on the piezoelectric material. To know the concept of energy being generated from rainwater, understanding about certain parameters is essential. The properties that impact the energy generation are its size, falling velocity, type of its impact, change of shape and kinetic energy of raindrop [10–12] (Fig. 1).

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Fig. 1 Driving rain

When the rain falls through fog, there will be changes in the air resistance and shape in the raindrop. Thus, the kinetic energy depends on this change in size along with its velocity of falling water drop. The French scientists have shown that a single drop of rainwater with varying diameter of about 1 and 5 mm can produce nearly 12 mJ/s [13]. Italian study has demonstrated that the conversion system based on the piezoelectric transducer generates energy of about 0.43 J [14]. Harvesting energy from the rainwater using this piezoelectricity technique is still not completely utilized in practical uses because of its complexity in working. [15].

2.2 Triboelectric Nanogenerator (TENG) In this new device generated, two polymer layers having the property of transparency are placed on top surface of the solar photovoltaic (PV) cells. A static electricity charge is generated due to friction produced. This friction is produced because of falling raindrops on the surface and rolling off [16]. Previous attempts to boost the ability of the solar cells under rainy conditions involved the addition of a pseudocapacitor (a component of a supercapacitor) or a triboelectric nanogenerator (TENG), a useful device which converts mechanical energy into electricity, is added to an existing solar cell. One of the polymer films in TENG works like an electrode for the TENG as well as for the solar cell. In order

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to get more power from solar panels, more light has to be focused on the solar cell, which is done by grooving the top layer of the cell, so that it provides larger surface area [17]. This method is implemented by imprinting two polymers with grooves by simply placing them onto DVDs. Adding this texture resulted in a boost to the triboelectric performance of one of the polymers, i.e., improving the efficiency of the conversion of external mechanical energy of the falling raindrops into electrical energy [18]. Meanwhile, the other polymer placed between the TENG and the solar cell acts as a mutual electrode for the devices and conducts energy from the TENG to the cell. Since the two polymers are transparent, energy is harvested from PV cells in addition to falling rain. Such a hybrid solar cell would be capable of generating energy even during a dark and rainy weather. While helpful, these approaches have proved complex to assemble and result in a bulky final product [17, 18].

2.3 Graphene Graphene is a two-dimensional form of carbon, which is obtained by oxidation, exfoliation and subsequent reduction of graphite. In graphene, there is a honeycomb-like arrangement of carbon atoms. Graphene has certain special electrical characteristics which makes them suitable for its usage to generate electrical power from raindrops: it has free delocalized electrons which can freely travel over the entire surface and conducts electricity. Graphene has the ability to combine its positively charged ions with electrons in its aqueous mixture with the concept of as Lewis acid-base interaction. This property is used in graphene-based processes to remove lead ions and organic dyes from solutions [19]. Graphene when combined with slightly saltwater, it has the capacity to generate electric potential. By using graphene, hybrid solar cells are developed, by coating thin film of graphene on the dye-sensitized solar cells. This technique uses electrodes of graphene to generate energy from the impact of falling raindrops. Since raindrops contain soluble salts of certain elements they are not pure form of water. They involve sodium, calcium, and ammonium ions which are positively charged. And these salts decompose into respective positive and negative ions. When these raindrops fall on graphene electrodes the water droplets dissociate into their respective ions. At this point of contact, the water becomes enriched in positive ions and graphene becomes enriched with delocalized electrons. These results in a duel-layer made up of electrons and positively ions, which are called pseudocapacitor. The potential difference linked with this concept is enough to produce a current and voltage. Some inimitable features of graphene making it appropriate with regard to its electricity, stability and heat conduction are: • The graphene crystalline structure with two-dimensional property consists of carbon-carbon bonds. In two-dimensional plane, chemically bonded graphene atom comprises of three more carbon atoms, with honeycomb-like structure. And

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graphene, in its three-dimensional plane consists of one free electron which is available for electronic conduction. The free electrons which are present above and below the graphene layer are of high mobility which is called pi (π ) electrons. Thus, the thermal fluctuation from instability is prevented by overlapping of these pi orbital’s which helps in improving the quality of carbon-carbon bond [20]. The Dirac point in graphene, which governs the chemical reactivity of graphene and play a vital role in propelling it. The electrons and holes have zero effective mass and this is the result of 6 individual corners of the Brillouin zone, the energy required for the excitation in the spectrum is linear at the lower energies. At this Dirac point of graphene, because of its zero density, the electronic conductivity of graphene is comparatively less by which the Fermi level can be varied by doping with electrons or holes to create relatively finer substance [21]. One of the exceptional properties of graphene is its intrinsic strength. The graphene is the strongest material ever discovered due to its 0.142 N m-long carbon bonds strength. It has an ultimate tensile stiffness of 150 GPa and tensile strength of 130 GPa (or 1,300,000 bars), compared to 400 MPa for A36 structural steel, or 375.7 MPa for Kevlar [22]. Absorbing and elastic property of graphene is another remarkable and essential quality. Even after applying strain, the initial size of the graphene is retained. The electrons of graphene behave like massless charge carriers and have higher mobility. As a result, the electron can draw 2.30% of white light. Light of high intensity reduces the absorption once the optical intensity reaches the certain saturation energy per unit area. This electric property is the main aspect with respect to the mode-locking of fiber lasers, i.e., producing pulses of light of extremely short duration. The force–displacement behavior of mono-layer graphene can be interpreted within an outline of nonlinear elastic stress–strain reaction which produces second- and third-order elastic stiffnesses of about 340 N/m [23]. Graphene is much delicate with 0.77 milligrams (mg) per square meter. In comparison, 1 m2 of paper is nearly thousand times bulky than 1 m2 of graphene. By this we can say, one sheet of graphene has the thickness of about one atom, which has enough size to cover the entire football field and weighs approximately less than one gram [24]. This graphene is a single atomic layer which owns very thin atomic thickness of about 0.345 N m. Due to this, graphene behaves very much like photons because of lack of mass. Thus, charge carriers can travel without scattering for sub-micrometer distances which are known as ballistic transport [25, 26]. Graphene is a type of semi-metal where there is no overlapping of energy gap between the valence band and conduction band. The energy band gap E can be adjusted continuously from 0 to approximately till 0.3 eV when SiO2 is preferred as a dielectric material. In such conditions, both the hole, as well as electrons will be available as charge conveyors having very high electrical conductivity even under ambient conditions [27].

Graphene is a single layer structure of hexagonally arranged carbon atoms. One may call it the single layer of graphite. However, graphene’s are basic structure of not

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only graphite but other allotropes of carbon like diamond, charcoal, fullerenes, etc., different substances are used in chemical composition of graphene. The source for construction of graphene is served by the graphene oxide (GO). This GO is chemically derived and is an automatically thin sheet of graphite. The efficiency of about 5.2% in this energy transmission can be obtained by modifying the distribution and density of reduced graphene oxide wafer on Si [28]. This can be covalently furnished by the functional group which contains oxygen either at the edges or at basal plane by which it possesses the mixture of sp2 and sp3 hybridized carbon atoms. Particularly, opportunities for tailoring its optoelectronic properties can be obtained by altering the shape, manipulating the size and the relative fraction of hybridized sp2 domains of graphene oxide with the help of reduction chemistry [29]. Sodium borohydride (NaBH4 ) is used as a reducing agent to acquire the electrical conductivity of reduced graphene oxide (RGO), from graphene oxide (GO) which is being experimentally analyzed with time (12 h) and at room temperature with 0.5 mg/mL by researchers. The epoxy or hydroxyl group’s reduction affects greatly on the restoration of the graphite structures conductive nature in RGO [30]. Scientists have added graphene which acts as a counter electrode catalyst with high efficiency to the solar cell which is dye-sensitized and a type of low cost, thin-layered cell, being reported 60% transparency and less than 9.2 efficiency. This results in hybrid solar cell having solar to electric conversion having the efficiency of about 6.53%. This flexible solar cell produces nearly hundreds of microvolt from rainwater which is split up into positive ions and negative ions [31]. Thus, this technology can be used to create all-weather solar panels to produce current, in which the electricity is generated from the rain which influences on the top layer of the solar cell. This graphene electrons being negatively charged can attract the ions with positive charges like ammonium, calcium and sodium toward itself. As a result, the positive and negative ion of rainwater gets separated on the graphene and then acts as a capacitor which stores the charge. Thus, where graphene and raindrops combine together, graphene gets delocalized electrons that are free to travel around. Meanwhile, the water at the contact becomes enriched in positive ions which are present in the raindrops. This separated positive and negative charges forms a duellayer which consists of made of negatively and positively charged ions. This concept is known as pseudocapacitor. This difference in potential works similar to a battery which generates current and voltage. The power produced from this graphene-coated solar cell can be utilized for different applications by producing electricity [24].

3 Applications in Using Graphene Systems In China, Britain and Mexico the commercial graphene MPPT systems are available. These solar panels are triggered by sunlight on bright days and even by water drops during the rainy season. Of the few systems available, solar mobile independent lowcost energy system known as SMILE is implemented by using transparent graphene

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on solar panels to be implanted on the building walls in order to build building management system (BMS). The SMILE technology is the first effort made to combine graphene that binds electrons of solar panels with the positively charged ions which are available in the rainwater. This separates bonding of the natural water and makes it combine with graphene. As a result, the dual layer is produced between the natural water and graphene which in turn helps in generating electricity [24]. But the dye-sensitized cells of solar panel applied with graphene are not the types which can completely be the successful replacement of the technology which uses exhaustible energy source, and also these graphene-coated cells have applications mostly in lacking-light conditions but not in the places with high sunlight [32]. Over the last few years, their efficiency has enhanced dramatically above 20%, where most of the countries and also the private citizens are changing their preferences from conventional energy sources to renewable sources which harness the power from sunlight. Because of the reason that solar panels are an easy choice to gather energy in places of lavish sunshine they are seen as an alternative to fossil fuels. But some places with significant presumption have not been as quick to adopt this method of energy generation, as panels typically generate 10–25% less energy on cloudy days than on sunny days. While these results are nowhere near the current output of present solar cells which have an efficiency of about 20% and can produce between 6 and 24 V of power. But the idea to grasp rain as well as sunshine certainly could make solar panels a more approachable option for generating renewable energy in all-weather by using graphene.

4 Conclusion This literature review paper provides an insight to the various techniques used to generate energy using falling rainwater. The aim of producing electricity from rain is to fulfill the needs of different electronic components. The research shows three different techniques used so far for increasing the efficiency of power generated from rain. And from the unique properties of graphene, the conclusion can be drawn that graphene-coated solar cells are best to harvest energy from the rainwater among the other methods studied. By using this, the solar cell can be built to replace conventional solar cells which will provide analogous efficiencies. Currently, research is going on in many other regions about using graphene in solar cells to enhance the efficiency and reduce the costs of the solar cells so that they can be probable source of energy in the future and can substitute the fossil fuels in different applications.

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24. Scientific India (2018, Aug 6) Retrieved Feb 2019, from Use of graphene in generating electricity from rain drops through solar panels: http://scind.org/1251/Science/use-of-graphene-ingenerating-electricity-from-rain-drops-through-solar-panels-.html 25. Baringhaus J et al (2013) Exceptional ballistic transport in epitaxial graphene nanoribbons. Nature. http://dx.doi.org/10.1038/nature12952 26. Properties of graphene (2009) Cambridge, USA 27. Srinivasan YO (2011) Graphene: is it the future for semiconductors? p 52 28. Lee W-C, Tsai M-L, Chen YL, Tu WC (2017, Apr 11) Fabrication and analysis of chemicallyderived graphene/pyramidal Si heterojunction solar cells 29. Loh KP, Bao Q, Eda G, Chhowalla M (2010, Dec) Graphene oxide as a chemically tunable platform for optical applications. Nat Chem 30. Yang Z-Z, Yang ZZ, Zheng QB, Qiu HX, Jing LI, Yang JH (2015) A simple method for the reduction of graphene oxide by sodium borohydride with CaCl2 as a catalyst. New Carbon Mater 86 31. Husain AA, Hasan WZ, Shafie S, Hamidon MN, Pandey SS (2018) A review of transparent solar photovoltaic technologies. Renew Sustain Energy Rev 94:779–791 (Elsevier) 32. Lim K (2016, Apr 15) Rain-powered energy discovered by Chinese scientists to increase solar panel efficiency. Retrieved from The Inquisitr: https://www.inquisitr.com/2996906/rainpowered-energy-discovered-by-chinese-scientists-to-increase-solar-panel-efficiency

Transfer Learning for Classification of Uterine Cervix Images for Cervical Cancer Screening Vidya Kudva, Keerthana Prasad and Shyamala Guruvare

Abstract Automated analysis of digital cervix images acquired during Visual Inspection with Acetic acid (VIA) is found to be of great help to aid the physicians to diagnose cervical cancer. Traditional classification methods require many features to distinguish between normal and abnormal cervix. Selection of distinct visual features which well represent the data and at the same time are capable of performing discriminative learning is complex. This problem can be overcome using deep learning approaches. Transfer learning is one of the deep learning approaches, which facilitates the use of a pre-trained network for a specific problem at hand. This paper presents a transfer learning using AlexNet, which is a pre-trained convolutional neural network, for classification of the cervix images into two classes namely negative and positive. This study used 2198 cervix images with 1090 belonging to negative class and 1108 to positive class. Our experiment using AlexNet for transfer learning achieved an accuracy of 0.934. Keywords Cervical cancer screening · Deep learning · Transfer learning · Machine learning · Medical image classification · Artificial intelligence

1 Introduction Though cervical cancer is amenable for screening and early detection, it is the second most common cause of death among women worldwide [1]. According to studies [1–3], developing countries contribute almost 90% to deaths due to cervical cancer. V. Kudva (B) E&C Department, NMAM Institute of Technology, NITTE, Karkala, India e-mail: [email protected] V. Kudva · K. Prasad MSOIS, MAHE, MANIPAL, Manipal, India e-mail: [email protected] S. Guruvare Department of Obstetrics and Gynecology, Kasturba Medical College, Manipal, India e-mail: [email protected] © Springer Nature Singapore Pte Ltd. 2020 S. Kalya et al. (eds.), Advances in Communication, Signal Processing, VLSI, and Embedded Systems, Lecture Notes in Electrical Engineering 614, https://doi.org/10.1007/978-981-15-0626-0_25

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Pap smear is the most commonly used method for screening of cervical cancer. But it has its own drawbacks in terms of low sensitivity (52%) [4] and the need for efficient networking between smear collection and cytology laboratories [5]. Along with being an expensive test, the results of this test are available approximately after two weeks. Hence, this approach cannot facilitate the screening and treatment in a single visit. VIA is demonstrated as a simple, cost-effective test that allows screen and treat approach [6]. Application of 3–5% acetic acid turns the pre-cancerous regions white, called acetowhite (AW) regions. Typical cervix images prior to and after the application of acetic acid are shown in Fig. 1. Pre-cancerous regions have turned white in Fig. 1b, which is marked as AW. These regions can be destroyed instantly by using cryotherapy [6]. This screen and treat approach can be performed in a single visit to the hospitals, which suppresses further development of cervical cancer. Diverse health workers like physicians, nurses, midwives and local health workers can perform VIA. Considerable training is required to discriminate between actual cancer lesions and lesions that are benign. Accuracy of this test depends on the skill level of the person who performs the test [7]. Blumenthal et al. [8] reported that health workers need to be trained well for successful implementation of VIA. This problem can be considered as a challenge in computer vision. Images of cervix during VIA process can be acquired and analysed using image processing algorithms. Traditional methods of cervix image classification are based on the selection of hand-crafted features and demand a clear awareness of prior domain knowledge. To differentiate between normal and abnormal lesions, the three main features such as colour, vascular patterns and lesion margins are considered [9] for analysis of cervical images. A few researchers [10–12] considered acetowhite feature for the classification of cervical images into normal or abnormal. Another group [13–15] used vascular patterns within the acetowhite lesion as feature. Claude et al. [16] and Raad et al. [17] used lesion margin feature. These studies observed a large variability in the dataset as the images were collected from different sites and heterogeneous devices were used for image acquisition. There was intrinsic variability among cervix images such as the size, colour, etc., among different patients. Images were complex with many features to distinguish between normal and abnormal cervix. Selection of

Fig. 1 Typical cervix images a prior to the application of acetic acid, b after the application of acetic acid

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Fig. 2 Taxonomy of deep learning using CNN for image analysis

distinct visual features, which well represent the data and at the same time capable of performing discriminative learning was difficult. Image analysis using deep learning can overcome these difficulties. Deep learning algorithm analyses the images in the same manner as the human brain. Their layered architecture self-learns the hierarchical features directly from the image data. Convolutional neural network (CNN) is a deep learning algorithm used extensively in analysing images. They are mainly composed of different layers namely convolutional layer, rectified linear unit (ReLU) layer, pooling layer and fully connected layer. A taxonomy of deep learning using CNN for image analysis is shown in Fig. 2. Deep learning is a technique in machine learning which learns to perform classifications directly from the data such as images, speech. Deep learning approaches are classified mainly into two types; full training and transfer learning. Under full training approach, CNNs are designed and trained from scratch. Depending on the number of layers in the architectures, CNNs can be classified as deep layer CNN and shallow layer CNN. Full training of CNNs with deep architecture requires large number of annotated data which are usually not available in the medical domain. Hence, the most popular deep CNNs [18–23] were trained with images of non-medical domain [24, 25]. Deep CNNs are capable of obtaining full representation of the training data. But the requirement of large number of annotated data hinders its applicability in the analysis of images in medical domain. So full training using shallow layered CNNs [26–40] were considered for image analysis in medical domain. But images in the medical domain have high feature variability, which needs the deep CNN architecture for the analysis. To exploit the advantages of deep architecture of CNN on the limited dataset, a concept known as transfer learning was utilised. This approach facilitates the use of the knowledge acquired by pre-trained CNNs which were trained using large number of non-medical data. Transfer learning can be performed in two ways. First is by extracting the features from different layers after retraining them with small data [41–45]. The features extracted are classified using different classifiers. Second way of transfer learning involves fine-tuning various layers of pre-trained CNNs to perform a different task [46–52]. It was demonstrated by these researchers that transfer learning is the best choice for the analysis of medical images, where large number of annotated data are not available. This paper reports a study of performance of transfer learning using AlexNet for classification of cervix images.

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2 Materials and Method 2.1 Data Collection and Ground Truth The cervix images were collected from the Kasturba Medical College of Manipal, India. Ground truth for the study was provided by a Gynaecologic Oncology expert. A total of 231 images were collected of which 31 images were VIA positive. We also collected the cervix images from the National Cancer Institute (NCI) and the National Institutes of Health (NIH) archive. A total of 1413 images of which 890 were VIA negative and 523 were VIA positive. Combining both the datasets we had 1644 images in total with 1090 VIA negative and 554 VIA positive. To increase the size of the data in VIA positive class, we used data augmentation. We rotated the VIA positive images by an angle of 90°. With data augmentation in total we have 1108 images in positive class and overall dataset consists of 2198 images.

2.2 Image Classification Using Transfer Learning Workflow of cervix image classification using AlexNet for transfer learning is shown in Fig. 3. It consists of four steps. First step involves replacing the last fully connected layer fc8 of AlexNet with a new fc8 with number of classes equal to two. Depth of fine-tuning needed for classification is determined in the second step. After fixing the depth of fine-tuning, number of training epochs needed for this network is determined in the third step. Number of batch sizes needed is determined in the fourth step after fixing depth of fine-tuning and number of training epochs. We used AlexNet for transfer learning. AlexNet is a deep pre-trained CNN trained on ImageNet. ImageNet is the dataset with 1.2 million labelled images belonging to 1000 classes. The architecture of the AlexNet is shown in the first block of Fig. 3. Design of ‘fc8’ which is the final layer, is dependent on the number of output classes in the applications considered. In the case of cervix image classification, there are two classes namely VIA positive and VIA negative. Hence, as the first step, layers ‘fc8’, ‘prob’ and ‘output’ of AlexNet need to be replaced with different layers, which are designed for the two-class problem. Number of neurons in the newly replaced ‘fc8’ layer was changed to two and hence ‘prob’ and ‘output’ were changed to two. In the second step, we carried out experiment on fine-tuning the different layers of AlexNet keeping the training epoch at 100 and with a batch size of 50. The initial CNN layers usually learn low-level features of image such as edges, lines and corners. Subsequent layers of CNN learn application-specific high-level features. Hence, it is usual to fine-tune the last few layers for transfer learning. We initiated the fine-tuning at the last layer and included the subsequent layers incrementally until the desired performance was achieved. Incremental fine-tuning was performed for the proposed application using different learning rates are listed in Table 1.

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Fig. 3 Cervix image classification using transfer learning Table 1 Learning rates used for fine-tuning layers of AlexNet Layer

S1

S2

S3

S4

S5

S6

S7

S8

fc8

0.01

0.01

0.01

0.01

0.01

0.01

0.01

0.01

fc7

0

0.001

0.001

0.001

0.001

0.001

0.001

0.001

fc6

0

0

0.001

0.001

0.001

0.001

0.001

0.001

cn5

0

0

0

0.001

0.001

0.001

0.001

0.001

cn4

0

0

0

0

0.001

0.001

0.001

0.001

cn3

0

0

0

0

0

0.001

0.001

0.001

cn2

0

0

0

0

0

0

0.001

0.001

cn1

0

0

0

0

0

0

0

0.001

cn—Convolutional, fc—fully connected

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Table 2 Results of image classification using fine-tuning AlexNet layers Fine-tuned layer

Accuracy

Sensitivity

Specificity

AUC

fc8

0.826

0.810

0.842

0.826

fc8-fc7

0.920

0.912

0.930

0.920

fc8-fc6

0.903

0.888

0.920

0.902

fc8-cn5

0.904

0.906

0.903

0.904

fc8-cn4

0.901

0.893

0.910

0.901

fc8-cn3

0.897

0.891

0.903

0.897

fc8-cn2

0.902

0.893

0.911

0.902

fc8-cn1

0.894

0.882

0.906

0.894

To retrain the network 85% of the data was used and remaining 15% for testing. A batch size of 50 was used. The network which provided the best performance was selected for further optimisation. Referring from Table 2, which represents finetuning the last fully connected layers fc8-fc7 provided the best results. In the third step, we chose the best network obtained from step 2 and studied its performance for different training epochs. This step was performed in order to select the optimal number of epochs for training the data. An epoch refers to the number of times entire training data are used for updating the weights of the network. After finalising the optimal number of layers of AlexNet to be considered, we experimented with different number of epochs to be used for the training in step 3. Performance of network for different epochs was studied and the epoch, which provided the best results was selected as the optimal ‘number of epochs’. In the fourth step, we selected the network obtained in step 2 and optimum number of epochs obtained in step 3 for the study of selection of batch size. We trained the network obtained in step 2 with different batch sizes for 700 epochs. Performance parameters as well as training time were noted. A batch size which was best in terms of accuracy and speed was selected. We retrained AlexNet using the parameters selected in steps 1–4 using 85% of the data for training. In the next step, we extracted features from different layers for the given dataset. These features were used to train a SVM classifier. Features for remaining 15% of the data were also extracted from the same layers and used as testing data. This method of image classification was compared with a traditional machine learning method of image classification [53]. This study reported the use of preprocessing [54] to remove various image acquisition artefacts. Different features such as colour, Haralick, and local binary pattern (LBP) were extracted. Relevant features were selected using Random subset feature selection (RSFS) method. Images were classified using selected features through SVM classifier. We followed this method to classify the images and compared the performance of this method with that obtained from the deep learning procedure described above.

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3 Results Results of fine-tuning different layers of AlexNet are shown in Table 2. Fine-tuning two fully connected layers fc8-fc7 provided better results. Performance of fine-tuning fc8-fc7 layers of AlexNet for different epochs is shown in Fig. 4. A plot of accuracy and sensitivity of AlexNet for different batch sizes are shown in Fig. 5. A plot of accuracy and training time as a function of different batch sizes is shown in Fig. 6. Results of classification using the features extracted from different AlexNet layers and classification by SVM classifier are shown in Fig. 7. Performance of features extracted from fc6, fc7 and fc8 layers is shown in Fig. 6.

Fig. 4 Performance of fine-tuning fc8-fc7 layers of AlexNet for different epochs

Fig. 5 Performance of AlexNet for different batch sizes

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Fig. 6 Accuracy and training time as a function of batch sizes

Fig. 7 Classification results using the features extracted from different AlexNet layers

Different performance parameters for traditional machine learning and transfer learning methods are tabulated in Table 3. Average values of different parameters over ten iterations are reported. Table 3 Comparison of traditional machine learning and transfer learning Method

Accuracy

Sensitivity

Specificity

Traditional machine learning

0.536

0.704

0.366

Transfer learning (features extracted from fc8 layer)

0.934

0.935

0.933

Transfer learning (fine-tune fc8-fc7)

0.933

0.933

0.932

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4 Discussion In this paper, we report the experimentation of use of transfer learning for classification of cervical images. Through the experimentation, we identified optimal values for depth of fine-tuning, training epochs and batch size. All the experiments were performed using NVIDIA GEFORCE GT640 system with 2 GB memory. MATLAB R2017b was used to build image processing algorithm. Tajbakhsh et al. [49] demonstrated that transfer learning is the best choice in medical image classification using deep learning, where large number of labelled data is not available. They stated that the required level of fine-tuning differs from one application to another. Also, selection of optimum parameters such as training epoch, batch size is necessary to get the optimum performance from a pre-trained network [53]. To study the depth of fine-tuning needed for the application of cervical image classification, we initiated the fine-tuning at the last layer and included the subsequent layers incrementally until the desired performance was achieved as shown in Table 2. It can be observed from Table 2 that fine-tuning two fully connected layers fc8fc7 provided the best results. Hence, for further studies of selection of optimum parameters, we used fine-tuning of only the last two layers. Number of training epochs used plays a major role in the performance of the pretrained network. Higher number of epochs for training leads to reduction in the error and thus improves the performance of the network. However, after few epochs the network may over-fit to the training data and loses the performance. This is analysed by monitoring the performance of the network for different training epochs as shown in Fig. 4. Optimum performance was achieved for 700 epochs. Hence, we use training epoch as 700. Selection of appropriate batch size is crucial for good performance of CNN. Selecting a high batch size reduces the training time but provides inaccurate results. On the other hand, selecting a very low batch size may provide accurate results but training time required will be more as shown in Figs. 5 and 6. So there is a need for trade-off between accuracy and speed. From Figs. 5 and 6 a batch size of 50 was selected as it provided the best results. Another method of performing transfer learning is to retrain the pre-trained network using the data of a different application. Subsequently, features were extracted from different layers and used to train classifier such as SVM and perform classification of images. We retrained AlexNet with fine-tuning depth fc8-fc7, 700 epochs and a batch size of 50. 85% of data were used for training. Features were extracted from different layers of AlexNet and used to train SVM classifiers. Features were extracted for 15% of test data from same layers and used as test features. The performance of SVM classifier for the features extracted from different layers of AlexNet is shown in Fig. 7. Since the features at different layers are different, training SVM using different features gives different accuracy. For instance, lower levels such as conv1, conv2, conv3 have low-level features such edges, colour where as high-level features such as shapes, textures in deep layers such as fc6, fc7 and fc8. It can be

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Fig. 8 Performance of features extracted from fully connected layers

observed from Fig. 7 that optimum results were obtained for three fully connected layers. Out of three fully connected layers, the features from the last fully connected layer fc8 provide the optimum results as shown in Fig. 8. A comparison performance of traditional machine learning with transfer learning is shown in Table 3. Performance for 85% training and 15% test data were tabulated. It can be observed from Table 3 that performance of traditional machine learning is poor when compared with the performance of transfer learning.

5 Conclusion An application of transfer learning using AlexNet for cervix image classification was reported in this paper. Parameters such as depth of fine-tuning, training epochs and batch size which provides optimal results were determined experimentally. The experimental results reveal that fine-tuning final layers fc8-fc7 of AlexNet provides optimal results. Also, features extracted from fc8 layers of AlexNet and classified using SVM classifier provides optimal results. We conclude that AlexNet configuration with fine-tuning fc8-fc7 layers, with training epochs of 700 and a batch size of 50 offers the best results for classification of cervix images. Acknowledgements This publication is made possible by a sub agreement from the Consortium for Affordable Medical Technologies (CAMTech) at Massachusetts General Hospital with funds provided by the generous support of the American people through the United States Agency for International Development (USAID Grant number 224581). The contents are the responsibility of Manipal Academy of Higher Education and do not necessarily reflect the views of Massachusetts General Hospital, USAID or the United States Government. We would like to acknowledge the support of Mark Schiffman, M.D, M.P.H., Division of Cancer Epidemiology and Genetics, National

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Cancer Institute, USA for providing us with cervix images. We would like to acknowledge the support of Dr. Suma Nair, Associate Professor, Community Medicine Department, Kasturba Medical College, Manipal for facilitating the acquisition of images during the screening programs conducted. Compliance with Ethical Standards Conflict of Interest The authors declare that they have no conflict of interest. Ethical Approval Approval from Institutional Ethics Committee, Kasturba Medical College and Kasturba Hospital, Manipal was obtained for this study, and an informed consent was obtained from the women participating in the study.

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Skew Analysis on Multisource Clock Tree Synthesis Using H-Tree Structure Vinayak Krishna Bhat, H. H. Surendra and H. R. Archana

Abstract The most critical constraints in System on chip (SoC’s), to determine the performance are area and power. As technology scales down, innovative clock tree design techniques are required to improve the skew. Hence, skew minimization design should be introduced in VLSI physical design at early stages of SoC’s where it has the highest benefits for QoR. In this paper, skew balance methodology using H-Tree is introduced in Multisource CTS design. Keywords Conventional clock tree synthesis · Multisource clock tree · H-Tree · Skew · Latency · Quality of results (QoR)

1 Introduction Any VLSI design is considered in terms of power, area and performance which in turn depend on placement, delay and skew. Timing optimization can be attained if there are no set-up and hold violations in your design. Proper placement and routing of the design ensure high performances of designs [1]. Clock tree synthesis is one of the important stages in very large scale integration (VLSI) physical design and has a significant impact on the QoR. Physical design or backend design is a set of ASIC design processes designed to take RTL through a variety of tools and flows to generate timing, routing, power, area and qualityconverged layout towards tape in. Clock tree synthesis (CTS) is a process which ensures that all the clock gets distributed evenly to all the sequential elements in the design. The CTS is not a good technique to understand the impact of congestion and timing violations. Therefore, the main goal in CTS stage is to minimize the latency V. K. Bhat (B) · H. H. Surendra · H. R. Archana Department of ECE, B.M.S.C.E, Bangalore, India e-mail: [email protected] H. H. Surendra e-mail: [email protected] H. R. Archana e-mail: [email protected] © Springer Nature Singapore Pte Ltd. 2020 S. Kalya et al. (eds.), Advances in Communication, Signal Processing, VLSI, and Embedded Systems, Lecture Notes in Electrical Engineering 614, https://doi.org/10.1007/978-981-15-0626-0_26

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Fig. 1 Example of clock skew waveform

and skew. CTS builds clock tree and enables all the sequential elements to have clock input as start point or reference point. All sequential elements in the design require synchronous clock to trigger the next stage. Clock is a medium to provide the reference edge so that next state can be achieved. Clock skew is the difference in clock signal arrival times between sinks as shown in Fig. 1. Clock skew minimal is very important in high-speed designs to meet timing demands. Latency is the delay that clock signal takes between the two points, i.e. clock source and clock pin. With lower technology nodes, the impact of process and on-chip variation is increasing. This in turn impacts the variability of the chip. There are two usual clock tree distribution architectures used in any design to meet timing requirements. One is conventional clock tree synthesis, which is commonly used due to minimal routing resources usage and less power consumption, as well as ease of simulation and implementation [2]. For high-performance design, clock tree based architecture can be more sensitive to process, voltage and temperature (PVT) variations. Second is the clock tree mesh architecture. It is a uniform metal grid which is marked with parallel lines on the chip which distributes the clock signals [3]. This clock mesh structure provides better tolerance to PVT variations. Chakrabarti [4], has proposed clock tree skew minimization with structured routing. Outcomes indicate that there is 6.5% skew reduction in the selected clock sub trees. The authors have proposed an algorithm for clock tree considering the process variations [1]. Parthibhan et al. have explained how to reduce the local skew on clock paths without affecting the process parameters. Here, researchers have explained about tunable clock buffers, tunable clock inverter design and its comparison [5]. Lin et al. have suggested a design which is very useful in clock skew optimization during pre and post CTS. On the other hand, power efficient and slew-aware 3D-gated clock tree synthesis is proposed using abstract topology generation which results in minimal buffer routing and clock skew [6]. In clock path, to get tight skew, developed a buffer reduction algorithm method for mesh-based clock distribution [7]. Another research works explain some heuristic approaches to improve the performance of MSCTS, for skew optimization. This explains tap drivers and sink assignments in clock tree path [8]. A two-level-powermode-aware clock tree optimization (CTO) methodology among different power modes is proposed by authors in [9]. The chip-level CTO globally reduces skew

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among the modules, whereas module-level CTO reduces clock skew within a single module; experimental results show that power-mode-aware CTO can achieve significant improvements in skew with worst-case condition. Most of the relative works mainly focus on the mesh tree architecture. In this paper, we have determined the QoR of Multipoint CTS flow provided by synopsis tool. Here, we analyse quality of results of traditional clock tree synthesis and Multipoint CTS on a real industrial design. In order to improve the skew in the clock path, we used H-tree structure for balancing the loads. The implementation flow is shown in Sect. 3. Sections 2 and 3 explains the basic knowledge on conventional CTS, clock mesh and Multipoint CTS. Section 4 presents how Multipoint CTS is proposed for tap-point assignment. Section 5 reports the experimental results with different cases. In Sect. 6 the conclusions and future work are discussed.

2 Conventional CTS and Clock Mesh 2.1 Conventional Clock Tree Synthesis Regular or conventional clock tree synthesis uses techniques like path sharing, delay detouring and multicorner optimization to address the process variations. Conventional clock tree structure is shown in Fig. 2. In this structure, most of sinks share Fig. 2 Conventional clock tree structure

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very few paths back to the clock route. In a simple buffer tree, clock source could be a port or output pin of the cell. In this case, levels of flops are imbalanced.

2.2 Clock Mesh The clock mesh is another architecture driven by many drivers spread out across an inter-join grid of metal wires. Outputs of all the drivers are shorted together by a metal grid to make sure that clock meshes oscillate as a single entity instead of multiple. Clock mesh structure is shown in Fig. 3.

3 Multipoint Clock Tree Synthesis Multipoint CTS is a custom clock tree structure having aspects of regular clock tree synthesis and clock mesh. Here, on-chip variation (OCV) tolerance is mainly achieved by improved path sharing contributed by clock mesh structure in the design.

Fig. 3 Clock mesh tree structure

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It also has better performance across the corners than the traditional clock tree structure. The structure is shown in the Fig. 4, which consists of mesh driven by premesh tree. A renewed emphasis on high-frequency clock design has heightened interest in multisource CTS. These multisource CTS consist of a global clock structure and local subtrees. A global clock structure consists of • • • •

The clock route A global clock tree Clock mesh drivers A clock mesh

Local subtrees that can be driven by the predefined set of drivers that are connected to clock mesh as shown in Fig. 4. These subtrees are built using regular clock tree

Fig. 4 Multisource CTS clock mesh tree structure

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Fig. 5 Clock mesh tree structure

synthesis and optimized by merging and splitting clock cells, while preserving subtree levels in the input structure.

3.1 Clock Spine and Clock Mesh in MSCTS Clock mesh is a two-dimensional grid in horizontal and vertical layer, where the straps are connected by vias at the intersection point as shown in Fig. 5. Clock spine is either one- or two-dimensional structure. One-dimensional spines are connected to multiple stripes in the orthogonal direction. Stripes connected to one spine do not connect stripes of different spines. The minimal distance between the stripes of different spines is called the back off.

3.2 Clock Tree Power Power consumption in clock mesh is mainly due to short circuit current in the skew from global clock tree, mesh driver and mesh fabric. Mesh causes a large increase in power consumption, in particular due to shorted buffers. It is observed that skew distribution of premesh tree is important in determining the amount of short circuit power. Figure 6 shows the short circuit current in the multisource clock tree synthesis. Short circuit power can be reduced by using symmetric and global clock tree structure, which ensures skew within tight bounds across the corners at the input of mesh drivers. Mesh fabric can be reduced by varying the number of mesh straps based on the load. Flops distribution and lower loads in sparser mesh fabric lead to fewer mesh drivers.

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Fig. 6 Short circuit current in multisource CTS

4 Multisource CTS Implementation In this, we are explaining how the clock structures are used in multisource CTS without clock mesh. Figure 8 shows multisource CTS where clock structure does not have a clock mesh. The global clock tree structure only consists of H-tree, which directly drives the tap drivers. It provides a way to control the clock latencies by using appropriate number of tap drivers in a block or design. This in turn improves the inter-block timing closure at the top level. A global clock distribution structure distributes the clock from root to each of the sub trees across the floor plan as shown in Fig. 7. A local clock distribution can have subtree that are optimized by merging and splitting clock cells, while preserving subtree level in the input structure. This represents the structural MSCTS. All the sinks are driven through a predefined levels of drivers called tap drivers and optimized by regular clock tree synthesis, which forms regular MSCTS. For both the structures a subtree connects the global clock structure at defined points or sources and hence, the name multisource clock tree synthesis.

4.1 Physical Implementation Flow The physical implementation of the clock structure flow is defined in the Fig. 8. To start clock tree assignment, we need a proper placement design set-up and CTS set-up for the design. H-tree is structurally symmetric and a balanced tree is used for global clock tree system, which drives the tap drivers as shown in Fig. 9. It uses high drive strength repeaters and low RC metal layers. The symmetrical construction ensures low skew across the corners of related sequential elements. The clock routing for particular design used is metal layer 7 to metal layer 12. To implement a multisource clock structure with H-Tree.

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Fig. 7 H-Tree based MSCTS without mesh

Fig. 8 Multisource CTS physical flow using H-tree

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Fig. 9 H-Tree implementation using clock structure

(a) Specify your clock tree constraints and settings. (b) Perform following steps for multi-voltage design: • Enable multi-voltage support by setting the cts., multisource., enable., full., mv., support application option true. • Enable additional feed through cells, which belongs to a voltage area physically but not logically by setting application option true. (c) Specify the required settings by using the multisource tree command and perform the tap assignment. H-tree is built by specifying required commands. (d) Specify options and settings for tap assignments. Perform the tap assignment using commands which performs the following functionalities:

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• Merges equivalent clock cells to remove any artificial boundary between the clusters of sinks. • Assigns endpoints to the closest tap drivers. Split cells along the path in the groups defined. • Copies the UPF and SDC constraints and user-defined attributes onto the newly created cells across the active scenarios. • Synthesize the entire clock tree, from clock route using synopsis command.

4.2 Insertion of Drivers and Sink Assignments In multisource CTS flow, the act of showing the number of drivers and its position which connects sinks in the design is very important. The arrangement of all the sinks can affect the QoR of the clock tree network structure. In this flow, IC compiler (ICC) tool from synopsis is used to determine the number of drivers based on position of sinks and its counts. In this work, we have modified the parameters according to the available resources from ICC and tabulated our results.

5 Experiment Results The H-tree structure implementation is done on a 10 nm process technology. The referred literatures include the results of implementation of regular CTS and clock mesh-based CTS, and conclude that clock mesh has a better QoR than regular CTS. Our paper addresses the tight skew requirements and improvisation of the performance of multisource CTS. Some design characteristics are listed in Table 1. All our design flows use same placement results deduced from ICC as the input. Comparison of QoR between conventional CTS and multisource CTS is tabulated in Table 2. Table 1 The design data

Cell name

ASIC

Process

10 nm

Number of macro cells

259,282

Number of standard cells

373

Total macro area

1,014,427.31 µm2

Clock routing layers

M7–M12

Skew Analysis on Multisource Clock Tree Synthesis … Table 2 The QoR table for CTS and MSCTS

Clock

323

Skew (ns)

Total latency (ns)

Clock 1

108.32

695.06

Clock 2

53.30

575.59

Clock 1

59.20

769.3

Clock 2

17.13

678.16

CTS

Multisource CTS

6 Conclusion and Future Work Here, we present the analysis of skew, latency and QoR of conventional CTS and multisource CTS with a real industrial design. Here, we implemented H-tree by creating drivers to improve the performance of multisource CTS, especially for skew optimization. From the results, we can conclude that multisource CTS gives a better performance for high-speed designs having a larger area. The multisource CTS can be improved by reducing the complexity of design required to implement the technique in the SoC level. Highspeed designs require minimal clock latencies and tight skews to meet timing and power demands. Similar set-up can be used for timing and power analysis. Acknowledgements We would like to thank Intel technology Pvt Ltd. for their support and encouragement.

References 1. Deng C, Cai Y, Zhou Q (2015) Fast synthesis of low power clock trees based on register clustering. In: International symposium on quality electronic design, pp 303–309 2. Xiao L, Xiao Z, Qian Z, Jiang Y, Huang T, Tian H, Young EFY (2010) Local clock skew minimization using blockage-aware mixed tree-mesh clock network. In: International conference on computer-aided design, pp 458–462 3. Patel N (2013) A novel clock distribution technology—multisource clock tree system (MCTS). Int J Adv Res Electr Electron Instrum Eng 2:2234–2239 4. Chakrabarti P (2012) Clock tree skew minimization with structured routing. In: International conference on VLSI design, pp 233–237 5. Parthibhan N, Ravi S, Maillikarjun KH (2012) Clock skew optimization in pre and post CTS. In: International conference on advanced in computing and communications, pp146–149 6. Lin M, Sun H, Kimura S (2016) Power-efficient and slew-aware three dimensional clock tree synthesis. In: IEEE International conference on VLSI-SoC 7. Reuben J, Zackriya M, Kittur HM (2014) Buffer reduction algorithm for mesh-based clock distribution. In: International conference on advanced in computing and communications 8. Chen W-H, Wang C-K, Chen H-M, Chou Y-C, Tsai C-H (2016) A comparative study on multisource clock network synthesis, pp 141–145 9. Lung C-L, Zeng Z-Y, Chou C-H, Chang S-C (2010) Clock skew optimization considering complicated power nodes. In: IEEE automation and test in Europe conference & exhibition, pp 1474–1479

Review on Implementation of Fingerprint Verification System Using Image Inpainting Milind B. Bhilavade, Meenakshi R. Patil, Lalita S. Admuthe and K. S. Shivaprakasha

Abstract Biometric attendance system has become more popular over the conventional system due to its various advantages. Fingerprint verification system is one of the promising methods installed in various organizations for attendance purpose. Usage of image inpainting technique in fingerprint verification improves the performance of fingerprint verification system. This paper highlights on some image inpainting techniques useful in fingerprint verification system. This paper also focuses on motivation to use image inpainting in fingerprint verification system. The fingerprint verification system is proposed where image inpainting algorithm shall be used to improve the performance of fingerprint verification system. Keywords Fingerprint · Minutiae · Ridge · Pores · Image inpainting

1 Introduction Nowaday’s biometric attendance system has been installed in many organizations like private, public and educational institutions. Due to the uniqueness of biometric characteristics biometric systems had become widely popular over the conventional M. B. Bhilavade (B) Electrical Engineering Department, VTU, Belagavi, India e-mail: [email protected] M. R. Patil Electronics and Communication Engineering Department, Jain AGM Institute of Technology, Jamkhandi, India e-mail: [email protected] L. S. Admuthe Electronics Engineering Department, DKTE’S Textile and Engineering Institute, Ichalkaranji, India e-mail: [email protected] K. S. Shivaprakasha Electronics and Communication Engineering Department, NMAMIT, Nitte, Udupi, India e-mail: [email protected] © Springer Nature Singapore Pte Ltd. 2020 S. Kalya et al. (eds.), Advances in Communication, Signal Processing, VLSI, and Embedded Systems, Lecture Notes in Electrical Engineering 614, https://doi.org/10.1007/978-981-15-0626-0_27

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system such as physical signatures. Several technologies have been proposed till date to overcome various difficulties that appear while matching these biometric characteristics. Fingerprint-based biometric attendance system is one of the favorite over the other biometric systems based on iris recognition, face recognition, palm recognition or speech recognition, etc. Due to its consistency and unique nature, fingerprint verification is becoming increasingly popular. Due to its low cost, it is widely used in smaller organizations. Different fingerprint matching technologies [1–5] are proposed by various researchers to overcome difficulties like impartial scanning and latent print of fingerprint. It has been also observed that this matching fails if the various scratches appear on the finger of the candidate who is suppose to register his attendance. These scratches appear during winter season or smaller cuts on the finger. So we propose to use image inpainting technology to remove these scratches. Image inpainting technique is a process which restores damaged or missing areas of an image. The image inpainting techniques proposed are mainly categorized into diffusion-based inpainting and texture-based Inpainting [6]. The remaining sections of the paper are organized as follows: In Sect. 2, various fingerprint techniques are reviewed to understand fundamentals of fingerprint and fingerprint verification system. The Sect. 3, reviews the image inpainting technique. In Sect. 4, discuss on proposing the fingerprint verification system using image inpainting.

2 Fingerprint Verification Systems Fingerprint-based biometric system is widely used because it is the most trusted user authentication system. A typical fingerprint verification system mainly consists of two process fingerprint enrollment and fingerprint verification. In fingerprint enrollment process, user registers his/her fingerprint and database is created. The fingerprint stored in database is used as template. During fingerprint verification process, the new fingerprint of user is compared with the templates of various users stored in the database to prove the authenticity of the user. Francis Galton was the first person to identify the unique and distinct ridge patterns present on the palms of our hands [5]. After that fingerprint has been widely used for authentication of persons, Galton stated that the minutiae particulars exhibit the individual characteristics of a person [2]. Many of the fingerprint verification techniques are based on Galton characteristics or Minutiae (ridge bifurcations and ridge ending). Other categories of fingerprint techniques are based on image pattern recognition. It has been observed by researchers that the techniques based on Galton characteristics shows improved results compare to the other category techniques based on pattern recognition. Fingerprint minutiae are shown in Fig. 1. In [5], the author has stated that no identification method has been devised to utilize the existence of the sweat pores that are observable on the ridges. In his paper, Locard has proposed to use the pores for identification like ridge characteristics, as the

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Fig. 1 Finger print minutiae

Pores

Ridge Bifurcation

Ridge End

pores are also permanent and unique for a person [2]. Paper [2] also presents a study of sweat pore variations and four criteria were defined for pore-based identification. The fingerprint in humans are basically the ridges and furrows exhibited by the fingers. Friction ridge skin (FRS) consists of two layers: inner and outer. The ridges come from the outer layer of the FRS [2]. On the contrary, pores emerge from the outer layer and penetrate into the inner layer. They act as the openings of the sweat glands. In a fingerprint image, a pore can be either open or closed depending on the perspiration activity [2]. Pores and ridges can be observed in Fig. 1. Two different prints of pores can be different as it may be open in one of the prints and closed in the other [2]. Fingerprints can be classified into the following three categories: First type is the rolled print containing the ridge details from nail to nail that is captured by the rolling of the finger. Second type is plain that can be obtained by pressing the finger on a plain body. The last category is the latent fingerprint that exhibits partial impressions of the finger that are retained on the object during its handling [5]. The last category of fingerprints is generally used for forensic applications. For biometric attendance systems plain/slap fingerprints are acquired. Resolution of the fingerprint plays a vital role in determining its characteristics. Resolution of an image indicates the number of pixels per inch (ppi) [2]. A minimum of 250–300 ppi resolution is needed to locate a minutiae in the fingerprint image. Nevertheless, to capture pores in an image of the fingerprint, a higher resolution (around 1000 ppi) is required. Despite designing of practical sensor with such a high resolution is expensive, optical sensors with such high resolutions are feasible. Minutiae-based matching techniques [1, 2, 4, 5] use points like ridge endings and other minutia points as features. Such systems perform better as the minutiae points in fingerprints provide higher discriminatory information. Image-based fingerprint matching techniques extract features directly from the image of the fingerprint [3, 7, 8]. These methods either compute the correlation amongst the input image and template images after a preprocessing stage or the fingerprint features are extracted using filtering or transforms followed by matching function [7]. These methods are advantageous as they do not need minutiae points extraction and they generally offer a compact fixed-size feature vector. Nevertheless, handling rotational alignment offsets may not be properly done in these approaches [7]. To improve the verification accuracy, exploitation of minutiae information is needed [7].

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Reconstruction of fingerprint from template has been proposed in [3, 5, 9]. Many researchers in the field of biometric postulated that a template does not contain sufficient information for the reconstruction of the original fingerprint image. In [9] and [5] reconstruction methods are proposed for latent fingerprints whose quality is always very poor. Authors in [5] have proposed to incorporate a feedback from exemplar for the refinement of feature extraction in latent in order to deal with the complex background noise in the latent.

3 Techniques of Image Inpainting In this section, we review the image inpainting techniques in [6, 10–17], so as to understand the fundamentals of image inpainting. Some of the important applications of image inpainting are restoration of the missing areas, repairing of the images, removal of the objects or scratches in an image and many more. The diffusion-based inpainting introduces smoothness priors through parametric models or partial differential equations to diffuse local structures from the exterior to the interior of the hole [6]. An image I can be mathematically defined as    ⊂ Rn → Rm I :  x → I (x) where x indicates a vector that represents the spatial coordinates of a pixel px. For a 2D image, it can be represented as x = (x, y) [6]. For a color image, each pixel in the image consists of three color components in (R, G, B) color space. Each cth image color channel of I can be denoted Ic:  → R. The problem of image inpainting considers an input image I to have undergone an amount of degradation denoted by M [6]. This results in domain  of the input image I being considered as a composite of two parts:  = S ∪ U, S which is called as the known part of the image I and U is considered to be the unknown part of the source image I. The problem is to estimate the entity U [6]. The degraded image can be represented as F = MI (Fig. 2). Local image geometry is to be retrieved followed by the usage of partial differential equations. The objective of image inpainting is to estimate the pixels that are present in the unknown region with the help of the pixels in the known region of the image [6]. Algorithm aims at filling the holes with the isophote. The isophote are lines of equal gray values. If the size of the unknown image is relatively small, diffusion-based inpainting algorithms could perform better. On the contrary, they tend to introduce smooth effect in the textured region or larger missing region. Exemplarbased methods fill holes by the patches from the surrounding area that have similar texture [17]. The exemplar-based approach [14, 15] perform well for the larger areas but fails to restore the definite shapes. As it concentrates mainly on the texture of image,

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S Source (Known Region)

U Hole (Unknown Region)

Fig. 2 An example image inpainting problem (original image is courtesy of [6])

structure of image is degraded. The hybrid models combine the advantages of both the methods (PDE and exemplar) and thus, the reconstruction of both texture and structure can be properly achieved. The workflow of any image inpainting algorithm can be as follows: Firstly, user selects the regions to be inpainted in a given image. Secondly, the propagation of the known information across the region boundaries so as to fill the gap. Image inpainting is a different method than noise removal. The image restoration problem [6] deals with the recovery of an image from different forms of degradations. As the missing region would be generally small in the image restoration problems, local diffusion and patch-based approaches offer satisfactory performances. Paper [13] proposes a third-order partial differential equation to achieve geometric inpainting on images.

4 Proposed Method The proposed method of fingerprint verification system consists of two parts fingerprint acquisition and template matching shown in Fig. 3. In the first part, the fingerprints of different users are to be acquired using conventional method and stored as database for verification of fingerprints. In the second part, during the template matching the user has to give his/her fingerprint to prove his/her authenticity. The problem arises in the second part while template matching if there are cuts or scratches on the finger of the user. The system fails to authenticate the user. To avoid this problem, the authors propose to use image inpainting algorithm to restore the fingerprint before matching. After the acquisition of template fingerprint

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Fingerprint acquisition

Database

Template Fingerprint acquisition

Fingerprint Restoration by Inpainting

Template Matching

Fig. 3 Proposed system

we propose to use image inpainting then apply the reconstructed fingerprint for verification. Our research work will focus on developing an image inpainting/fingerprint restoration algorithm which will remove the scratches or finger cut marks from the fingerprint. PDE-based geometric image inpainting algorithm [13] and fingerprint restoration algorithms suggested in [5, 9] are the motivations to carry our research work. The detailed discussion on implementation and results of proposed method shall be discussed in our upcoming research paper.

5 Conclusion The use of image inpainting/fingerprint restoration before template matching will increase the accuracy of fingerprint verification system. PDE-based image inpainting or exemplar-based Image restoration will help to implement the proposed methodology. Our research in the future will focus on developing an image inpainting/fingerprint verification algorithm proposed in Sect. 4.

References 1. Agrawal P, Kapoor R, Agrawal A (2014) A Hybrid partial fingerprint matching algorithm for estimation of equal error rate. In: Proceedings of ICACCCT 2014, ISBN No. 978-1-47993914-5/14/$31.00 ©2014 IEEE pp 1295–1299 2. Jain AK, Chen Y, Demirkus M (2007) Pores and ridges: high-resolution fingerprint matching using Level 3 features college. IEEE Trans Pattern Anal Mach Intell 29(1):15–27 3. Cappelli R, Lumini A, Maio D, Maltoni D (2007) Fingerprint image reconstruction from standard templates. IEEE Trans Pattern Anal Mach Intell 29(9):1489–1503 4. Cao K, Jain AK (2015) Learning fingerprint reconstruction from Minutiae Image. IEEE Trans Inf Forensic Secur 10(1):104–117 5. Arora SS, Liu E, Cao K, Jain AK (2014) Latent fingerprint matching: performance gain via feedback from exemplar prints. IEEE Trans Pattern Anal Mach Intell 36(12):2452–2465 6. Guillemot C, Le Meur O (2014) Image inpainting. IEEE Signal Process Mag, pp 127–144

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7. Park CH, Lee JJ, Smith MJT, Park Sl, Park KH (2004) Directional filter bank-based fingerprint feature extraction and matching. IEEE Trans Circuits Syst Video Technol 14(1):74–85 8. Moayer B, Fu KS (1976) A tree system approach for fingerprint pattern recognition. IEEE Trans Comput C-25(3):262–274 9. Feng J, Jain AK (2011) Fingerprint reconstruction: from minutiae to phase. IEEE Ttransactions Pattern Anal Mach Intell 33(2):209–223 10. Carola-Bibiane (2009) Modern PDE techniques for image inpainting. Ph.D. thesis submitted to DAMTP Centre for mathematical sciences, University of Cambridge [online] available: http:// www.damtp.cam.ac.uk/user/cbs31/Publications_files/thesis.pdf 11. Hasegawa M, Kako T, Hirobayashi S, Misawa T, Yoshizawa T, Inazumi Y (2013) Image inpainting on the basis of spectral structure from 2-D Nonharmonic analysis. IEEE Trans Image Process 22(8):3008–3017 12. He L, Wang Y (2014) Iterative support detection-based split bregman method for wavelet frame-based image inpainting. IEEE Trans Image Process 23(12):5470–5485 13. Bertalmío M (2006) Strong-continuation, contrast-invariant inpainting with a third-order optimal PDE. IEEE Trans Image Process 15(7):1934–1938 14. Wohlberg B (2011) Inpainting by joint optimization of linear combinations of exemplars. IEEE Signal Process Lett 18(1):75–78 15. Liu Yunqiang, Caselles Vicent (2013) Exemplar-based image inpainting using multiscale graph cuts. IEEE Trans Image Process 22(5):1699–1711 16. Ruži´c T, Pižurica A (2015) Context-aware patch-based image inpainting using markov random field modeling. IEEE Trans Image Process 24(1) pp 444–456 17. Awati AS, Deshpande SP, Belagal PY, Patil M (2017) Digital image inpainting using modified Kriging algorithm. In: Proceedings of 2nd international conference for convergence in technology (I2CT) available online at IEEExplore pp 945–950

Milind B Bhilavade received his Diploma in Electrical Engineering from WCE Sangli in 1998. Completed BE (Instrumentation Enginnerging) and ME in Control systems from Shivaji University Kolhapur in 2001 and 2008, respectively. Presently, he is research student of VTU Belagavi Karnataka state India. Authors research area includes image processing and digital image inpainting. The author has worked as Lecture BCE Shravanbelgola Karnataka state India from 2003 to 2007. Presently, he is working as assistant professor in JJMCOE Jaysingpur, Maharashtra from 2007. Mr. Bhilavade is life member of ISTE from 2009.

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M. B. Bhilavade et al. Dr. Meenakshi R. Patil (M-07, SM-17) became member IEEE in 2007 and senior member of IEEE in 2017. Author is graduated in Electronics and Communication Engineering from PVPIT Budhagaon in 1994 and received post graduate degree in Electronics Engineering from WCE Sangli in 2002. Author has completed her Ph.D. degree from Shivaji University Kolhapur in 2011. Authors research interest includes digital watermarking, Digital Image processing, Communication and network security. From 1999 to 2007, she was a head of department BCE Shravanbelgola. Since 2011, she has been Professor with the AGM Group of institutions Hubbali, Karanataka state India. She is currently working with JAGMIT Jamkhandi, Karnataka state India. Presently five research students are working on various fields in Signal processing and communication under her supervision. Dr. Patil is life member of ISTE since 2002. Dr. Patil has designed a digital trainer kit which they are using it in their laboratories for educational purpose. Dr. Lalita S. Admuthe, (M’15) member of IEEE, Computer Society. Author has received the M.E. and Ph.D. Degree in electronics engineering both from Shivaji University Kolhapur, India in 1994 and 2013, respectively. Authors research interest includes neural networks, wireless networks, fuzzy logic and optimization problems. Since 2013 she has been a Professor in Electronics Engineering at DKTE’s Textile and Engineering Institute Ichalkaranji. Currently, she is working as Dy-Director and Head of electronics engineering department in the same institute. Her teaching experience includes the topics of artificial neural networks, random signal processing, computer architecture and parallel processing. Dr. Admuthe is Life Member of ISTE. Dr. Admuthe has been the adviser of Ph.D. degree dissertation, Shivaji University Kolhapur on topics related to Decision making optimization in fuzzy environment and artificial intelligence. Dr. K. S. Shivaprakasha received his B.E. (electronics and communication) degree from Bahubali College of Engineering, Visvesvaraya Technological University, Karnataka with IX rank in the university and M.Tech. (Digital Electronics and Communication Systems) degree from Malnad College of Engineering, Visvesvaraya Technological University, Karnataka with I rank with Gold Medal in the university in 2004 and 2007, respectively. Author completed his Ph.D. from National Institute of Technology Karnataka (NITK), Surathkal, Karnataka, in the field of wireless sensor networks in 2015. Authors areas of research interest include wireless sensor networks, mobile adhoc networks, information coding theory and cryptography. Currently, he is an Associate Professor in the department of electronics and communication engineering, N. M. A. M. Institute of Technology, Nitte, Karnataka. He has published more

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than 20 papers in reputed international/national journals and conferences and has co-authored a book on “Information Theory and Coding” for Wiley (India) publications.

PWM Controlled Solenoid Valves for Automatic Gear Change in Four-Wheelers M. R. Anusha and M. G. Veena

Abstract The prodigious growth of automobile users has introduced a strong sense of competition among the manufacturers; eventually, forcing the industry to provide comfort, performance, and serviceability to the consumers. Automobiles with manual transmission do not provide smooth driving. It is difficult to achieve wide ratio coverage through a high number of gears in manual transmission. This paper aims at improving the comfort level of the automobiles with a keen focus on automatic gear changing by incorporating pulse width modulation (PWM) controlled current drivers to control the solenoid valve which in turn governs the automatic gear changing system. In this paper, pulse width modulated voltage signal is given as an input to the MOSFET acting as a switch. The output current from this switch is used to control the movement of the plunger in the solenoid. The torque created due to the movement of the plunger results in the change in pressure of the hydraulic fluid. This pressure controls the clutch pads in turn controlling the planetary gear sets. This results in the change of gear ratio thereby changing the gear of the four-wheeler. Keywords Manual transmission · Automatic gear · Pulse width modulation · MOSFET switch · Solenoid

1 Introduction Transmission system in a four-wheeler assists in transmitting mechanical power from the car engine to the wheels to give kinetic energy. It consists of gears, shafts, and other electrical components. Automatic transmission offers high driving comfort, free the driver of the distraction of manual shifting, and actively contributes to increased transportation safety. Up-to-date automatic transmissions achieve wide M. R. Anusha (B) · M. G. Veena Department of Electronics and Communication Engineering, JSS Science and Technology University (Formerly SJCE), Mysuru, India e-mail: [email protected] M. G. Veena e-mail: [email protected] © Springer Nature Singapore Pte Ltd. 2020 S. Kalya et al. (eds.), Advances in Communication, Signal Processing, VLSI, and Embedded Systems, Lecture Notes in Electrical Engineering 614, https://doi.org/10.1007/978-981-15-0626-0_28

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ratio coverage through a high number of gears. Due to electronic transmission controls, modern automatic transmissions help in fuel consumption compared to their purely mechanical/hydraulic predecessors. They provide smooth shifting of gears, exhaust from the engine can be reduced, more reliability. A transmission solenoid is an electromechanical component that is used to control the flow of hydraulic fluid. The opening and closing of the solenoids are controlled electronically by the transmission control module. The solenoid is controlled by the PWM signal that is generated by the current-controlled application-specific integration circuit (ASIC). The displacement, velocity, and the electromagnetic force response of the solenoid are directly proportional to the exciting current [1]. The torque that is generated by the solenoid results in the pressure of the hydraulic fluid. In an automatic transmission, automatic gear change is due to the change in the gear ratio. Desired gear ratio is achieved by the movement of planetary gear sets. This movement is controlled by the hydraulically actuated wet clutches [2]. In this paper, a feedback mechanism for the current controlled ASIC to generate a PWM signal that controls the actuation of a hydraulically controlled wet clutch that controls the gear change in a four-wheeler is presented.

2 Transmission Model 2.1 Transmission Control Unit Based on the signals received from the transmission control unit, the electrohydraulic valves are controlled in the four-wheelers. Appropriate gear ratio selection can be determined by applying hydraulic pressure to clutches and brake bands in the system. The transmission control unit as shown in Fig. 1 takes decisions based on electrical signals received from various sensors located on the engine and gearbox. Depending on the speed and load condition of the gear, transmission control unit (TCU) stores data along with the correction factors for transmission and engine temperatures provided by the temperature sensors. Using this data, the TCU energizes solenoid valves Fig. 1 Transmission control unit

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so that suitable gear ratio can be selected to the subsisting driving conditions. Selfdiagnosis of the TCU is executed and operated in the fail-safe mode if fault is found. From the above figure, microcontroller controls the low side switch using a current driver. Controller interacts with the driver through Serial Peripheral Interface (SPI) communication.

2.2 Gear Change by the Control of Solenoid Valves Gear change depends on gear ratio, and the gear ratio is defined as the ratio of the input shaft rotation to the output shaft rotation. It is also called a transmission ratio [3]. Different gear ratios are achieved by locking and unlocking same set of gears to the output shaft. This is done by • Bands, clutches to lock the planetary gear set • Hydraulic system to control bands, clutches • Oil pump to control the flow of hydraulic fluid.

3 Literature Review For automatic change of gear in four-wheelers, several literatures have been surveyed and their research outcomes are presented here. Meng et al. proposed the proportional solenoid valve is an actuator for a proportional control valve used in automatic transmission pressure control devices [1]. The proportional solenoid produces flow rates proportional to the current. In this paper, dynamic response of proportional solenoid is investigated by the authors, considering the response of winding current, inductance, flux linkage, mover displacement and velocity, electromagnetic force response of solenoid by the direct current (DC) and PWM controlling. Lazar et al. investigated multiplate wet clutches controlled by an electrohydraulic actuator [2]. In this paper, a model capturing the essential dynamics of an electrohydraulic valve and clutch operating on a given pressure range that is given by transmission shifting signal and based on the model, predictive control strategy for the clutch is presented. Tao et al. proposed a model in which the shift hydraulic system in the automatic transmission generates and maintains desired clutch pressure for shifting operation [4]. The model consists of supply line pressure regulation system, solenoid valve, pressure control valve (PCV), and wet clutch for shift hydraulic system. Wang et al. proposed a nonlinear, low-frequency model capturing the essential dynamics of an variable force solenoid (VFS) and clutch operating on a given pressure

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range that is given by transmission shifting signal [5]. This model describes pressure filling and stroking during clutch engagement. A concept of uninterrupted shift transmission (UST) is introduced by Zhao et al. [6]. The components are similar to automated manual transmission but multimode controllable shifters offer uninterrupted torque from engine to wheels during shifting process. The special control logic involving the engine, clutch, and transmission is proposed to improve UST’s shift quality.

4 Results and Discussions In the present work, the solenoid drivers that control the solenoid valves in turn controlling the pressure of the hydraulic fluid are discussed. This novelty work is presented in this paper. Solenoid valves can be controlled by current drivers. The current driver works in two different configurations hardware mode and software mode. The hardware mode is when the current flowing in the load is controlled by feedback current loop found in the current driver and software mode is where the current driver is actuated through microcontroller pins. Figure 2 shows the current driver with current feedback mechanism to control the movement of the solenoid valve, in turn controlling the change of gears in automatic transmission.

4.1 Hardware Current Control The block diagram of the current driver is as shown in Fig. 3. The working of current driver is explained below. (1) Set point generator generates load current values that depend on wheel speed sensors, voltage regulation, temperature sensors, pressure sensors, and so on. (2) Proportional-integration controller is used to control the current flowing through the load (solenoid). Fig. 2 Control circuit for solenoid valve

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Fig. 3 Control circuit of the current driver

(3) Switching period of the generated PWM signal is varied to improve the settling time of the signal. (4) The pulse width modulated voltage signal is given as the input to the MOSFET. (5) The output average current of the MOSFET controls the movement of the plunger in the solenoid. (6) The output average signal is converted to digital signal using analog-to-digital converter (ADC) and is given as a feedback signal to the system. From Fig. 3, the difference in the set point value and the digital average signal from ADC results in an error signal. This error signal is converted into a output control signal by proportional-integral (PI) controller. This digital value is converted to a PWM signal by the PWM generator. The solenoid valve converts the PWM signal to an average current which is the output of the system. The solenoid valve movement is controlled by the generated PWM signal. Each PWM signal pattern is mapped to desired current value. (1) Set Point Generator: From the above figure, set point generator is used to generate load current values and these values depend on wheel speed sensors, voltage regulation, temperature sensors, pressure sensors, and so on. The set point value is given by the controller to the current driver. If the set point has a value of 0, the solenoid driver can be switched off. (2) Proportional-Integration Controller: Solenoid current is controlled through proportional-integration (PI) controller. To tune the transient response and settling time of the loop that depends on the load, control parameters like controller gain are required.

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Conversion of the resulting error signal into fixed frequency and variable duty cycle PWM signal by the PI controller is used to control the gate of external MOSFET switch. For both variable and fixed PWM frequency control, the following parameters can be changed. KI Integral portion of the loop gain: • In variable frequency mode, it is based on the formula

KI = 2(N +3)

(1)

N be the value stored in the register of a controller [Integral error gain] • In fixed frequency mode, it is based on the formula

KI = 2(N +5)

(2)

N be the value stored in the register of a controller [Integral error gain] KP Proportional portion of the loop gain: KP = 2(N +1)

(3)

N be the value stored in the register of a controller [Proportional error gain] (3) Switching Period of the PWM Signal: The hardware current control feedback works both at variable or fixed frequency PWM signal. The control loop varies the frequency of the generated PWM signal period during transients in order to improve the settling time. In hardware mode, the PWM switching period of each solenoid driver is given by the equation (N ∗ 64 + 1) ∗ T

(4)

From the above (4), T is the time period of the PWM signal in fixed frequency mode and N be the value (PWM signal period) stored in the register of a controller. For variable frequency mode, the formula is given by (N ∗ 64 + 2) ∗ T

(5)

The PWM period is checked against reference minimum time period and maximum time period values. (4) Solenoid Current Feedback: The average current is measured using the sense resistor. The average current is updated for every PWM cycle. The calculation

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Fig. 4 Software current control mode

starts when PWM raises and stops and when a new PWM raises. Instantaneous current in the solenoid valve is read by the PI control loop input after offset compensation and calibration.

4.2 Software Current Control The block diagram of the software current control is as shown in Fig. 4. In the software current control mode, PWM signals are generated by the input pins present in the microcontroller. These PWM signals are given as the input to the current driver which converts the PWM signals into current signal. This current signal is used to control the movement of solenoid valves.

4.3 Results (1) In hardware current control mode, there is a separate circuit to generate the PWM signal, whereas in software current control mode, PWM signal is generated by INx or input pins of microcontroller. This PWM signal pattern with fixed frequency and varying duty cycle is mapped to the desired current value that results in the desired movement of the solenoid, in turn changing the hydraulic pressure in the solenoid. Hydraulic pressure change results in gear change in an automatic transmission. Duty cycle of the PWM signal can be adjusted so that it reaches the target load current. Figure 5 shows the generated PWM signal. Consider PWM signal with signal pattern [101010101010101010101010101010101010101010101010101], frequency 10 Hz, and 50% duty cycle. This signal pattern can be mapped to 0.5 mA current Average voltage can be calculated using = peak voltage ∗ duty cycle the formula average voltage = 1 V ∗ (0.05/0.1) = 0.5 V 0.5V can be given as an input to the MOSFET.

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Fig. 5 Plot of time versus voltage of PWM Signal

(2) In the current driver of hardware current control mode, the generated PWM signal gives as input to the MOSFET switch. The resulting instantaneous current from the MOSFET switch is used to control the solenoid movement in turn changing the hydraulic pressure in the solenoid which results in the gear change. Figure 6 shows the generation of instantaneous current waveform through PWM signal. Consider a MOSFET switch with resistance 1 K, average voltage of 1 V. Instantaneous current is given by the formula

Fig. 6 Instantaneous current waveform

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Instantaneous current = average voltage/resistance of the MOSFET switch = 0.5 V/IK = 0.5 mA The instantaneous current of 0.5 mA is used to control the movement of the plunger in the solenoid. The pressure created due to this controls the clutch pads in turn controlling the planetary gear sets. This part of the work considered to be published in the future article.

5 Conclusion and Future Work As the manual transmission does not provide driving pleasure, transportation safety, automatic transmission came into existence. This automatic transmission in automobiles increases fuel efficiency, provides smoother shifting, reduced engine emissions, greater reliability, and improved vehicle handling. In this paper, a conceptualization of current feedback mechanism for the current drivers to control the solenoid valves is presented. The following conclusion is drawn from the above concept. (1) The PWM signal pattern is mapped to desired current value that is drawn by the solenoid. (2) The electromechanical effect in the solenoid valve results in its movement in turn changing the hydraulic pressure of its fluid. (3) Clutches activated by the hydraulic pressure actuate automatic gear change. (4) Addition of triangular dither signal to the current reduces mechanical hysteresis in the solenoid valves could be considered for the future work. The instantaneous current 0.5 mA is used to control the movement of the plunger in the solenoid. This current creates pressure in the hydraulic fluid. This hydraulic fluid pressure results in the gear change by controlling the gear sets. This part of work considered to be published in the future article.

References 1. Meng F, Tao G, Luo PP (2014) Dynamic analysis of proportional solenoid for automatic transmission applications. In: 2014 International conference on mechatronics and control, Jinzhou, China, 3–5 Jul 2014 2. Lazar C, Caruntu C-F, Balau A-E (2010) Modelling and predictive control of an electro-hydraulic actuated wet clutch for automatic transmission. 978-1-4244-6392-3/10/ IEEE 3. Berjoza D, Pirs V, Jurgena I, Laceklis-Bertmatmanis J (2018) Energy use efficiency of electric automobile depending on transmission gear ratio 23–25.05.2018 4. Tao G, Zhang T, Chen H (2011) Modeling of shift hydraulic system for automatic transmission 978-1-61284-459-6/11/2011 IEEE

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5. Wang Y, Kraska M, Ortmann W (2001) Dynamic modeling of a variable force solenoid and a clutch for hydraulic control in vehicle transmission system. In: Proceedings of the American control conference, Arlington, VA, 25–27 June 2001 6. Zhao K, Liu Y, Huang X, Yang R, Wei J (2013) Uninterrupted shift transmission and its shift characteristics. 1083-4435 2013 IEEE

Literature Survey on Emotion Recognition for Social Signal Processing A. Vijayalakshmi and P. Mohanaiah

Abstract Emotion is a significant aspect o the progress of human–computer interaction systems. To achieve best functionality through HCI, the computer is able to understand the emotions of human effectively. To do so, there is a need for designing an effective emotion recognition system by using the social behavior of human beings into the account. The signals through which human being tries to express the emotions are called as social signals, and the examples are facial expression, speech, and gestures. A vast research is carried out in earlier to achieve effective results in the emotion recognition system through social signal processing. This paper outlines the details of earlier developed approaches based on this aspect. Since there are number of social signals, the complete survey is categorized as audio-based and image-based. A further classification is based on the modality of input, i.e., single modal (single social signal) or multimodal (multiple social signals). Based on the methodology accomplished to achieve the objectives, this survey is further classified into different classes and details are provided more clearly. Brief details about the databases involved in the accomplishment are also explained clearly. Keywords Emotion recognition · Social signal · Speech · Face · Feature extraction · Classification · Databases

1 Introduction In recent years, emotion recognition has become a significant research aspect due to its widespread applicability in various human–computer interaction (HCI)-oriented applications [1, 2]. The main objective of emotion recognition in HCI applications is A. Vijayalakshmi (B) Department of ECE, JNTUCEA, Anantapur, India e-mail: [email protected] Department of ECE, Vardhaman College of Engineering, Hyderabad, Telangana, India P. Mohanaiah Department of ECE, N.B.K.R Institute of Science & Technology, Vidyanagar, Nellore, Andhra Pradesh, India © Springer Nature Singapore Pte Ltd. 2020 S. Kalya et al. (eds.), Advances in Communication, Signal Processing, VLSI, and Embedded Systems, Lecture Notes in Electrical Engineering 614, https://doi.org/10.1007/978-981-15-0626-0_29

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to enhance the human–machine interface by an automatic analysis of emotional states of human beings. However, the critical aspect is to recognize the emotional state such as sadness, boredom, neutral, joy, and anger [3]. Further, the emotion recognition for HCI has become a building task where the human beings exploit personal computers and smart phones to express their feelings. The inevitable activities such as speech, facial expression, and verbal language gradually insisted the interaction between the human beings and the computer-assisted communication attributes such as mobile phones, iPhones, and robots. With the developing and changing uses of HCIs, emotion recognition technologies provide a contingency to boost up the interactions or communication between humans and computers [4, 5]. Mainly, emotion is communicated through various social behaviors along with speech, facial expression, gesture, text. As per earlier studies on the social signalbased emotion recognition, different opinions are given by different researchers. An analysis carried out by Mehrabian [4] found out that facial expression contributes 55% of total expression, the speech contributes 38% and further the semantics like gesture, text contributes 7%. Hence, the facial expression can be modeled as a main social signal to find the emotions perfectly. Further, the speech signal can also be considered as a secondary or supportive signal in the detection of emotions for the HCI system. In the earlier studies, emotion analysis and recognition approaches from a single modal input have been widely proposed [6–9]. For betterment of the quality of an emotion, recognition system based on only the single modal input has its limitations. For improvement of the recognition performance, a challenging area of research has to be explored in which multiple modals of input are considered for emotion recognition. These multiple modals includes the integration of facial expressions, speech and gesture movements. This paper investigates the earlier developed emotion recognition approaches based on single (including facial expression, speech, and gesture movements) and multiple modals. Based on the input signal modal, the emotion recognition system is classified as uni-modal and multimodal. Further, based on the type of input signal, the earlier approaches are categorized as audio-based, image-based, and fusion-based approaches. In the audio-based approaches, the speech signal is considered as input, and in the image-based approaches, the facial images are considered as input, and in the hybrid approaches, both are considered. A next stage classification constitutes the mechanism which focused mainly on the feature extraction and classification. A simple overview of the databases used in earlier studies for evaluation is also given in this paper. Finally, the possibilities to improve the research work in this direction are illustrated in the conclusion part. Rest of the paper is organized as follows: Sect. 2 gives the details of the system model. Under this model, totally the system is divided into three phases: preprocessing, feature extraction, and classification. Section 3 illustrates the complete details of literature survey. Section 4 concludes the paper.

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2 System Model Emotion recognition system consists of preprocessing, feature extraction, and classification. Depending on the input signals, the emotion recognition system can be modeled as uni-modal and multimodal. In the case of uni-modal, only one input signal is used for testing, whereas in the multimodal, greater than one number of signals are used for processing. A general uni-/multi-system modal of emotion recognition is shown in Fig. 1. In the preprocessing phase, the input social signal is getting transformed into the compatible format, for example from symbolic to numeric or vice versa. The preprocessed data is only suitable to process the data for further process. Here the preprocessing phase varies from signal to signal. For a facial image, the preprocessing phase tries to filter out the external noises, makes the image visually attractive and more qualitative by removing unnecessary blurriness, enhances contrast, and adjusts the luminance and chrominance in an adaptive fashion, etc. Similarly, for a speech signal, the preprocessing phase removes the noise, filters out the non-voice components, windowing, etc. Though the process carried out in the preprocessing phase, it is completely to boost the quality of signal such that the important and unimportant components of a signal can be differentiated more clearly which results in an efficient overall system performance. Further, the feature extraction phase extracts the features from preprocessed signal and required to analyze the emotions. This phase also varies from signal to signal. So many techniques are proposed in earlier to extract the features from the signal with different objectives. Some approaches focused to achieve more accuracy in the detection by considering all the feature set, and some more approaches consider only partial feature set. This feature also varies from the dimensions, i.e., 1-D, 2-D, and 3-D, for example, the most popular discrete wavelet transform (DWT). For a speech signal, 1-D DWT is enough to extract the low-pass and high-pass frequencies from the signal. Whereas in the case of facial image or gesture movement, 2-D

Fig. 1 General system model of uni-modal/multimodal emotion recognition

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DWT is required to extract the intermediate frequencies along with low- and highpass frequencies. Hence, the emotion recognition through social signal processing makes challenging in the design of a feature extraction technique that will provide compatibility between different signals and also won’t affect the final performance of system. Finally, the classifier phase involves recognizing the emotion based on the feature set, trained to the system. So many approaches are proposed in earlier aiming to achieve an optimal performance at this phase. Most of the approaches focused to accomplish the data mining technique and machine learning techniques. Examples of data mining techniques are Euclidian distance, distribution law distance, etc., and the machine learning approaches constitute the artificial neural network (ANN), support vector machines (SVM), decision trees, nearest neighbors (NN), etc. Further the database which was used for testing is also important in the emotion recognition performance. There are so many databases for speech signal, facial expressions, and gesture movements. VAM [10] is example of German speech database with 947 utterances with approximately 12 h. Similarly, RML [11] is another database of 500 video samples created in six languages with six emotion categories (anger, disgust, fear, happiness, sadness, and surprise). Some authors utilized the inbuilt databases and some created their own databases. A detailed survey of the databases used for emotion recognition is illustrated in Table 1.

3 Literature Survey According to the system modal described in Sect. 2, the emotion recognition system is accomplished in these phases. So many authors proposed different approaches based on different strategies to achieve the main objectives of this concept. Some approaches purely focused to preprocess the social signal and some methods focused only on the feature extraction and some more only focused to design the classifier through different algorithms like machine learning and data mining methods. Here a brief literature survey is carried out over the earlier developed techniques based on their main focus. The entire survey is divided as a feature extraction technique and classification techniques. Further, the feature extraction techniques are categorized into different classes based on the input social signal like facial expression, speech, and gesture.

3.1 Feature Extraction In emotion recognition system, feature extraction is very important by which the system can analyze in-depth characteristics of social signal such that it can get more information about the signal. Based on the signal types, there are so many approaches are proposed in earlier to achieve efficient results in the emotion recognition system.

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Table 1 Databases for emotion recognition Database name

Number of subjects

Emotions acquired

Year

OuluVS2 [12]

50 speaker stuttering three types of utterances

Acquired views in between frontal and profile under five spans

2015

RECOLA [13]

46 subjects (19 male, 27 female)

Rapport, performance, engagement, dominance, agreement are acquired as social behaviors, and valence and arousal are also acquired

2013

AVDLC [14]

292 subjects (age range from 18 to 63 years

Severe depression, moderate depression, mild depression, and minimal depression

2013

MAHNOB [15]

22 subjects (12 male, 10 female)

Speech laughter, posed laughter, speech, laughter, and some other vocalizations

2013

AFEW [16]

330 subjects (single and multiple subjects per sample, age range from 1 to 70 years)

Seven emotions, namely surprise, sadness, neutral, happiness, fear, disgust, and anger

2012

MHMC [17]

7 actors (both genders)

Four emotions, namely neutral, anger, sadness, happiness

2012

SEMAINE [18]

150 participants

Twenty-seven allied emotions; five affective dimensions, namely emotional intensity, power expectation, activation, and valence

2010

SAVEE [19]

Four male actors

Seven classes of emotions, namely neutral, surprise, sadness, happiness, fear, disgust, anger

2009

RML [11]

Eight subjects

Six emotions, namely surprise, sadness, happiness, fear, disgust, and anger

2008

TUM AVIC [20]

21 subjects

Five non-linguistic vocalizations, namely laughter, hesitation, grab age, consent, and breathing

2007

eNTERFACE’05 [21]

42 subjects (34 men, 8 women from 14 different nationalities)

Six emotions, namely surprise, sadness, happiness, fear, disgust, and anger

2006

CUAVE [22]

36 individual speakers, 20 pair speakers

Facial images with front and back, all sides, and tilted heads

2002

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Most of the approaches considered the speech and facial signals as inputs for emotion recognition system and the details are illustrated here. 1. Audio features Representing the speech signal with only certain set of features are focused in most of the earlier state-of-art methods for audio-based emotion recognition. Among those, acoustic and prosodic are the two different set of features discussed in earlier [23–27]. Furthermore, among these two, prosodic features are observed as effective features through which the emotion states of humans are recognized effectively in verbal communication [28–30]. An emotion recognition system was proposed by Rao et al. [31] based on the global and prosodic features. Rao considered pitch, energy, and duration as prosodic features to detect the emotion from speech signals. Here the global prosodic features describe the gross properties like maximum, minimum, slope, mean, and standard deviation of the prosodic contours. Further, the local characteristics are described by the temporal dynamics of prosody. Idris et al. [32] evaluated a hybrid set of features integrating the quality of voice with prosodic features and hybrid features for the purpose of emotion detection. Here totally two features are taken from the voice quality; one is from prosodic features and two more from hybrid statistics. Simulation experiments are accomplished over the standard “Berlin emotional database”. Jacob et al. [33] developed an emotion recognition system based on the segmentation of prosodic features and suprasegmental (SS) English speech signals. Totally, this method considered 1050 segmental and 1400 SS features. Totally six types of emotions are investigated here acquired from 10 female English speakers. The statistical features evaluated from signals are speech rate, duration, pitch, and intensity. Since both prosodic and spectral features have gained their own importance in the detection of emotions from speech signals, integrating them will result in an enhanced performance. Based on this strategy, Zhou et al. [34] proposed to combine the spectral features with prosodic features. A novel fusion mechanism is also developed in this approach to fuse these two set of features into a fine feature. Further in [35], an emotion recognition system was developed which was both text-independent and speaker-independent. This system was accomplished over Sambalpuri, Cuttack, and Berhampuri dialects of Odia language. Here the prosodic features considered for recognition are formant, duration, energy, and pitch. An “Orthogonal Forward Selection (OFS)” algorithm was used here for evaluation. Further, Morrison et al. [25] were summarized the correlations between the prosodic features and emotions. Along with pitch and energy features, some more features such as mel-frequency cepstral coefficients (MFCCs), spectral formants, shimmer or jitter, and harmonics-to-noise ratio (HNR) are also used for emotion recognition in earlier studies [6, 7, 35–38]. MFCCs [39–41] are the features which represent the local temporal characteristics of the speech signals. A 39-D feature vector is constructed based on 12 MFCCs and energy, and first and second derivations by Metallinou et al. [40]. Further, the MFCCs are combined with so many features to improve the emotion recognition performance. In [42], features are extracted from audio characteristics of emotional speech by “mel-frequency cepstral coefficient

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(MFCC),” and “sub-band-based cepstral parameter (SBC)” method. Zhang et al. [43] studied the effect of features’ number and their statistical values over the accuracy of emotion recognition system. Based on the “Gaussian mixture model (GMM),” two effective features are extracted form speech signals and they are MFCCs, and “autocorrelation function coefficients (ACFC).” Based on these two features, a new vector is constructed and accomplished over the Berlin emotional database with different emotions such as sad, neutral, happy, fear, disgust, and angry. For speech emotion recognition, based on model properties speech features are categorized into local (frame level) and global (utterance-level) features [6, 44]. The local features characterize the speech features which are drawn from the unit of speech “frame,” whereas the global features are extracted from the entire “utterance” [45, 6]. 2. Facial Features The facial features can be partitioned into appearance and geometric features [46, 9]. Folds, lumps, and furrows of the facial texture represent the appearance features. The shape and position of the facial components are represented by the geometric features. Considering the active appearance model (AAM), a new method is proposed by Saatci and Town [47] to detect both gender and emotions. Wilhelm et al. [48] present a comparison between the use of independent component analysis and AAM using several classifiers to recognize the identity, gender, age, and facial expressions. A Bayesian tangent shape model (BTSM) was proposed by Zhou et al. [49] based on Bayesian inference solution. Next, the facial recognition system developed by Elgammal and Lee in [50] considered a novel nonlinear generative model based on the empirical kernel maps and conceptual manifold embedding. This approach deals with the deformations in shapes of facial images and also can provide a most accurate synthesis based on the emotional states. Liebelt et al. [51] build up an interactive multi-level algorithm for AAM [52] decent to 2-D images and 3-D shape alignment to disparity data. Antonini et al. [53] utilize the AAM to extract a set of high-level features and analyzed the performance of various classifiers. In [54], Mathew introduced a schema for the categorization of emotions, based on the static face images. This approach used AAM [55, 56] for training the facial images gained from a publicly available database to describe the variations in texture and shape for representation. Specifications from the AAM are used to identify six universal emotions. Further in [57], an AAM-assisted facial expression recognition approach is developed based on the texture and shape of facial image feature points. Initially, the significance of texture and shapes is analyzed in the provision of discrimination of different facial features through AAM [17, 58, 59]. And then these two features are used to classify the facial expression through a machine learning algorithm. The local binary patterns as a dense local appearance descriptors are used for facial expression recognition [60–63] and also used as baseline feature for challenges in AVEC 2011– 2014 challenges [64–67]. After the normalization of the face region, LBP histograms are obtained by segregating the region into blocks using binary comparisons and the LBP features are integrated into a feature vector to represent a facial image.

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In [68], a useful preprocessing algorithm pooled with “feature extraction with LBP followed by classification using KLD” is anticipated to perform emotion recognition. In [69], a usual process of facial expressions detection with the application of random frog algorithm [70] is proposed using the high-dimensional LBP. This method was evaluated using the “static facial expressions in the wild (SFEW)” [71] database, which consists of the face images coming from movies and is comparable to realworld scenarios. 3. Fusion Approaches In this category, the features of the speech signal and face image signal are fused to construct a new feature set such that the emotion recognition performance will be enhanced. In the past few years, many data fusion strategies [72] have been developed [73–75]. In feature-level fusion [76–78], a joint feature vector is designed by joining facial and vocal features and is then modeled by a classifier for emotion recognition. Metallinou et al. [76] concentrated on detection of the emotional content at utterance level within a multimodal using “hierarchical approach: bidirectional long short– term memory (BLSTM) [79], neural networks, hierarchical hidden Markov model classifiers (HMMs),” and hybrid HMM/BLSTM classifiers are considered. Further in [77], to increase the performance of detecting emotions from a spontaneous speech, a bimodal feature decision approach is proposed. In this, a feature vector of speech is united with individual key frames of video and a decision-level fusion is applied to the related frames. A “log-linear model, termed as named bimodal log-linear regression (BLLR),” is proposed in [78] to measure the feature interaction between two models. The performance is measured with respect to two emotions, laughter and speech, because both the events are generally audio visual events. The fusion at feature level of combining audio and visual cues consists of a problem of data sparseness due to for not considering the interactions among the features. In decision-level fusion [40, 63, 76, 80], the fusion is applied to the results of the classifier model of multiple signals. Error weighted combination (EWC) [40, 76] is an example of decision-level fusion approach proposed for emotion recognition by combining the speech and image features. HMM was used for training the voice modality, and GMM is used for training the facial data, and finally, a weighted sum of individual decision is evaluated to effectively determine the emotion. The fusion at decision level is improper because the facial and vocal features are uncorrelated in emotional expressions. For this, correlation between multiple modalities is used in model-level fusion strategy [17, 39, 58, 81–85].

3.2 Classification Once the required features are drawn out from the signals, these features are trained through various classifiers. Here the classification can be carried out thorough data mining technique and also through the machine learning approaches. In the case

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of data mining approaches, Euclidean distance, power distribution law distance, correlative measures, KLD [68], and entropy are used to perform classification, whereas in the machine learning approaches, ANN [32], SVM [70, 86, 87], and HMM [58, 84] techniques are used for classifying the input signal into its respective emotion. Sinith et al. [88] proposed a SVM-based emotion recognition system based on the speech features, and the extracted features are principally related to statistics of pitch and energy. In [86], the complete emotional expressions are extracted from acoustic features and textual contents using threshold-based fusion. [87] principally focused on learning methods and implemented SVM and deep boltzmann machine for facial emotion recognition. Recently, deep learning [89–93] has been attained a greater research interest due to its more flexibility in the data analysis through its deep characteristics. In [89], a new emotion recognition framework is proposed based on the convolutional neural networks. This approach consists of a face detection model with the group of three standard face detectors followed by a classifier with the bunch of multiple deep convolutional neural networks. The models which are pre-trained are then fine-tuned over the trained set of SFEW 2.0. Two separate methods are accomplished to integrate the multiple CNN models to learn the network responses ensemble weight. They are hinge loss minimization and log-likelihood loss minimization. Further based on the success of CNN, a new method is proposed for classifying emotions based on statistical facial images. The proposed method is applied over the CASIA web face database to evaluate the performance analysis. Along with the approaches discussed above, there are number of approaches proposed in earlier to achieve effective recognition results in the case of different emotions. A simple comparative analysis of the earlier proposed approaches is described in Table 2.

4 Conclusion Since emotion plays a vital role in the understanding of a human behavior, recognizing emotion constitutes a major research problem in the human–computer interface systems. Hence, there is a need to develop an efficient emotion recognizing system that integrates the social behavior of human beings to understand the intentions in a more clear way. Basically, the emotion is expressed through social signals including facial expression, speech, gestures, and text. This paper focused to perform a literature survey over the earlier studies developed with an aim of the efficient emotion recognition system. According to the above analysis, most of the work is carried out over the facial images and then over the voice signals. One more thing noticed form the above report is that compared to single social signal, multiple social signals will result in an effective performance achievement. Here most of multimodal approaches considered the facial expression and speech as input social signals. Further to validate, various standard databases are utilized and some authors developed their own databases.

Emotions

Anger, happiness, neutral, sadness

4 cognitive states and 7 prototypical emotions

Neutral, sadness, fear, anger, joy, and surprise

Anger, disgust, fear, happiness, sadness, surprise

Anger, happiness, neutral, sadness

Valence, arousal

Name

Metallinou et al. [40]

Zeng et al. [83]

Song et al. [81]

Paleariet al. [82]

Metallinou et al. [94]

Nicolaou et al. [85]

1. Mel filter bank coefficients 2. Corners of the eyebrows (4 points), eyes (8 points), nose (3 points), mouth (4 points), and chin (1 point)

1. MFCCs 2. Facial marker coordinates

1. F0, first five formants, intensity, harmonicity, ten MFCC, and 10 LPC 2. Facial FP absolute movements and relative movements of couples of facial FP

1. 48 prosodic, 16 formant frequency features 2. Facial animation parameters (FAPs)

1. Pitch, energy 2. 12 facial motion units

1. 39-dimensional MFCCs 2. The positions official markers are separated into six facial regions

Feature set

Table 2 Literature review on the emotion recognition through social signals

HMM, SVM, Panic particle filtering tracking

HMM, GMM, Bayesian fusion

NN, SVM, Neural network based on evidence theory (NNET)

HMM, Tripled HMM (T-HMM)

HMM, multi-stream fused HMM (MFHMM)

GMM, Bayesian classifier, weighting scheme

Methods

2010

2010

2009

2008

2008

2008

Year

(continued)

Sensitive artificial listener (SAL)

IEMOCAP

eNTERFACE’05

Self-created

Self-created

IEMOCAP

Database

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Emotions

Surprise, sadness, happiness, fear, disgust, and anger

Activation and valence

Neural, angry, sad, happy, and emotion quadrant I, II, III, and IV.

Positive, negative

Anger, disgust

Happiness intensity levels

Name

Jiang et al. [39]

Lu et al. [84]

Wu et al. [58]

Rosas et al. [62]

Idris et al. [32]

Dhall et al. [71]

Table 2 (continued)

1. Pyramid of histogram gradient 2. Local phase quantization

1. 2 voice quality features 2. 1 prosodic feature 3. 2 hybrid feature

1. Loudness, intensity, duration of pause 2. Camera gaze and duration of smile

1. Formants from F1 to F5, energy, and pitch. 2. 30 FAPs

1. Energy, pitch and 12 MFCC features 2. Ten distance-based geometric features

1. 42-dimension MFCC 2. 18 facial features, 7 FAU

Feature set

Group expression model (GEM)

MLP-NN

SVM with linear kernel

HMM, 2H-SC-HMM

HMM, Boosted Coupled HMM

HMM, T_AsyDBN

Methods

Self

Berlin emotional database

Spanish Multimodal opinion

MHMC SEMAINE

Self-created

eNTERFACE’05

Database

2015

2014

2013

2013

2012

2011

Year

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Though there is a vast research carried out over this concept, there is a room to improve the performance of an emotion recognition system. Almost all of the approaches did not focus on the deep characteristics such as intensities of emotions. A deep analysis of a social signal constitutes an excessive time delay and also results in an unnecessary computational complexity. In the case of standard databases, only standard emotions are created that too under the ideal environment. But this is the main problem with real-time emotions which constitutes of too many variations including noises, intensities for speech and color, shape, luminance, texture, etc., for facial images. Hence, there is a need to design an effective emotion recognition system by including all these factors to make the system robust and adaptable to any environment.

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Low-Power Analysis of Full Adder and Subtractor Design Using Adiabatic Logic Styles Akshitha and Niju Rajan

Abstract With improvements in VLSI technologies, the number of gates per chip increases at same rate, and as a result, power dissipation increases and heat removal becomes complex and expensive. Therefore, power dissipation is one of the critical issues in low-power circuits in VLSI design. Adiabatic logic is a promising technique that is used in low-power VLSI circuits to achieve high-performance levels with reduced power consumption. By limiting the flow of current through low-voltage devices, by utilizing the stored energy from node capacitance (C L ), and also using sinusoidal or trapezoidal type of power supply adiabatic circuits exhibit a low power dissipation [1]. Full adder and full subtractor are designed using adiabatic techniques and conventional CMOS technique and analysis of power is performed using Cadence Virtuoso Tool at 180 nm Technology. The results proved that power saving is more for full adder and subtractor implemented using adiabatic logic compared to CMOS logic. Keywords Conventional design · Adiabatic design · Efficient charge recovery logic style · Full adder · Full subtractor · Positive feedback adiabatic logic style · 2N-2N2P logic · Clocked adiabatic logic style

1 Introduction Electronic circuits and system design have to deal with difficulties of offering good performance with minimal power dissipation. One of the major constraints of lowpower design is low power consumption. Increasing complex applications that are used in many portable devices require high performance. As the use of portable electronic gadgets increases, the reduction of power dissipation has been one of the key elements of modern electronics. Akshitha (B) · N. Rajan Department of E&C, N.M.A.M Institute of Technology, Karkala, India e-mail: [email protected] N. Rajan e-mail: [email protected] © Springer Nature Singapore Pte Ltd. 2020 S. Kalya et al. (eds.), Advances in Communication, Signal Processing, VLSI, and Embedded Systems, Lecture Notes in Electrical Engineering 614, https://doi.org/10.1007/978-981-15-0626-0_30

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Due to low power consumption and high level of integration, CMOS design is of great demand in VLSI technology [2]. The main criteria are recognizing the fact for power dissipation and appropriate measures to be taken by knowing the source for dissipation of power. Static and dynamic power dissipation are the main sources of power dissipation. Static power is due to DC-bias and leakage current and is less observed in CMOS circuits. In CMOS circuitry, dynamic power dissipation is dominating and is due to circuit switching activity. By decreasing the switching activity, the capacitance of the node and the voltage swing power saving can be achieved.

2 Literature Survey Bhati et al. [2] provided comparative study between conventional CMOS design and positive feedback adiabatic logic (PFAL). Power analysis was carried out for the MUX design and 1bit full adder design at different frequencies in Cadence Virtuoso environment at 180 nm technology. The results conveyed that the average power consumption in case of PFAL logic was less compared to conventional design. Jayanthi et al. [3] proposed different logic circuits and adders using conventional CMOS design and adiabatic design (PFAL and ECRL). The design was analyzed using SPICE and the results proved that more than 50% of power saving is achievable in case of adiabatic design compared to conventional design and also PFAL consumes less power when compared to ECRL design. Pindoo et al. [4] provided comparative study on adiabatic logic families (PFAL, ECRL, PAL, etc.) with CMOS technique. Constant power source was used for designing logic and sinusoidal power source for adiabatic logic. Analysis was carried out for inverter circuits simulated in Cadence Virtuoso environment at 180 nm technology. Result proved that, power dissipation was less for inverter designed using adiabatic logic compared to CMOS technique. Chaudhuri et al. [5] explained about the power efficiency of 4:1 multiplier, implemented using different adiabatic logic families. The result proved that power dissipation was less in case of positive feedback adiabatic logic (PFAL) as compared to several other adiabatic logic families. All the logic design was simulated in Cadence Virtuoso Spectree at 180 nm Taiwan Semiconductor Manufacturing Company (TSMC) technology. Haiyan et al. [6] proposed adiabatic flip-flops and sequential circuits using improved clocked Adiabatic Logic (ICAL). Comparison of power was performed between adiabatic logic style and conventional CMOS technique by designing mod10 counter. The layout for the circuit was drawn using Cadence Virtuoso editor with NCSU Free Process Design Kit (PDK) 45 nm technology library. The comparison of results conveyed that the power consumed by ICAL logic was less compared to conventional CMOS design. Mishra [7] provided comparative study on NAND gate using conventional CMOS design and positive feedback adiabatic logic (PFAL) adiabatic technique. The logic

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gate was realized under Mentor Graphics IC design architect using standard Taiwan Semiconductor Manufacturing Company (TSMC) 0.35 µm technology and an average power was obtained by varying frequency and load capacitance. The result proved that the adiabatic PFAL logic style was advantageous in application where power dissipation was of prime importance. Kaur [8] provided comparative study on full adder using conventional transmission gate and partial adiabatic technique. Focus was to reduce power consumption. The simulation results ensured that power dissipated by PFAL logic was less as compared to ECRL logic and the design was simulated using TANNER simulator V7 technology. Yadav et al. [9] proposed different adiabatic logic families such as positive feedback adiabatic logic (PFAL) and subthreshold adiabatic logic (SAL). Using PFAL, energy efficient adiabatic Logic (ECRL) and SAL techniques 4 bit carry look-Ahead Adder (CLA) was designed and an analysis validates the credibility of the logic in terms of power dissipation and delay. The simulation was obtained by launching ADEL from Cadence Virtuoso environment under 180 nm technology. Results proved that the power reduction in the ECRL topology was much better than the other existing topology (PFAL and SAL) of adiabatic technique. Tulasi et al. [10] provided comparative study on full adder using conventional complementary metal oxide semiconductor (CMOS) design and an adiabatic logic design. The design of low power CMOS cell structure uses fully complementary CMOS logic and an adiabatic positive feedback Logic (PFAL) style. These logic units were realized under Mentor Graphics IC design architect using standard Taiwan Semiconductor Manufacturing Company (TSMC) 0.35 µm technology. The analysis was carried out by varying the frequencies about MHz range. Results conveyed that average power dissipation in case of adiabatic positive feedback logic was less compared to conventional CMOS logic. Based on the available information, partial adiabatic technique has proved to be very efficient in reducing power (dynamic power, static power). The objective of the adiabatic technique is to reduce power dissipation by using sinusoidal or trapezoidal power supply instead of constant power supply and to reuse the charge stored in the node capacitance that is dissipated as heat in case of other CMOS design.

3 Switching Techniques 3.1 Conventional CMOS Switching The topology of conventional CMOS inverter with constant power supply (V dd ) is as shown in Fig. 1a. Leakage of power occurs at the time of switching event, in case of conventional CMOS logic. The constant power supply (V dd ) is used and due to switching event of the circuit, transfer of energy or charge occurs from supply voltage to output (V out ) or from output to ground with output voltage swing [3]. The pull-up

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Fig. 1 a Topology of conventional CMOS inverter, b charging up and charging down path of conventional CMOS Logic

path consists of PMOS transistor and pull-down path consist of NMOS transistor. The node capacitance (C L ) is connected across the drain terminals of PMOS and NMOSFETs. Figure 1b shows the charging and discharging path in the conventional CMOS design. Consider that the PMOS transistor in the pull-up path is ON. From Fig. 1a, the NMOS in pull-down path is OFF during 0 to V dd transition. Amount of energy driven from the power supply is given as, 2 E total = CL Vdd

(1)

The total charge stored at the node capacitance (C L ) at end of transition is given as, 2 E stored = 1/2CL Vdd

(2)

In PMOS network, half of the energy stored from the power supply is dissipated and the remaining energy is stored in the node capacitance. While there is a transition from V dd to 0, the charge or the energy stored in the node capacitance is discharged to ground via NMOS transistor. By reduction of switching events, node capacitance and voltage swing power saving is achievable in circuits.

3.2 Adiabatic Switching Adiabatic technique adopts recovery logic in electronic circuits designed using low power. Here power saving is achieved by reusing the energy stored in the node capacitance (C L ) rather than releasing it to ground as in case of conventional CMOS design at the time of switching and thus efficiency of the circuit is achieved. Adiabatic circuit is used to reuse the charge by using sinusoidal power supply that works at four

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Fig. 2 a Topology of adiabatic inverter logic, b charging up and charging down path of adiabatic logic

phases of the clock namely; idle phase, precharge phase, hold phase, and recovery phase instead of constant power supply and also obtaining outputs under certain condition. Figure 2a shows the topology of adiabatic logic representing basic inverter circuit and Fig. 2b shows the charging up and charging down path of adiabatic logic with complementary power supply [3]. The total energy dissipation at time of switching is given by, 2 /T E diss = RC2L Vdd

(3)

where E diss V dd T R CL

energy dissipated at the time of adiabatic switching process supply voltage Time period ON resistance of MOS switch Load capacitance

4 Logic Design at Transistor Level 4.1 Full Adder Design at Transistor Level (1) Sum block of full adder at transistor level: The XOR gate logic gives output to be high when number of inputs are dissimilar. The output results only if one or all inputs to the gate is true. Figure 3 shows the transistor-level representation of full adder sum block. The full adder sum block output can be analyzed as in (4).

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Fig. 3 Transistor-level representation of full adder sum block

¯ + ab sum = a¯ bc ¯ c¯ + a b¯ c¯ + abc

(4)

(2) Carry block of full adder at transistor level: Fig. 4 shows the transistor-level representation of full adder carry block. The carry is generated if two of the inputs are high or all the three input bits are high. Inputs are arranged in SOP form, and carry output is analyzed as in (5).

carry = ab + bc + ca

(5)

Low-Power Analysis of Full Adder and Subtractor … Fig. 4 Transistor-level representation of full adder carry block

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4.2 Full Subtractor at Transistor Level (1) Difference block of full subtractor at transistor level: Fig. 3 shows the transistorlevel diagram of full adder sum block. The difference block can be analyzed in the same method. Using K-map, the difference equation can be analyzed which is denoted in SOP form as in (4). The pull-up path consists of parallel connected PMOS transistor and the pulldown path consists of serially connected NMOS transistors shown in Fig. 3. The output is obtained only if one or all the inputs are high, for rest of the cases the output remains to be low. 2) Borrow block of full subtractor at transistor level: Fig. 5 shows the transistorlevel diagram of full subtractor. Using K-map, the Boolean expression obtained is in SOP form represented as in (6).

borrow = ab ¯ + ac ¯ + bc

(6)

The pull-up path consists of parallel-connected PMOS transistor and the pull-down path consists of series-connected NMOS transistors. Outputs are set at precharge phase of power clock if borrow is considered from the next stage during evaluation of logic, and for rest of the phase of power clock, the output remains unchanged.

5 Partial Adiabatic Technique and Implementations 5.1 Positive Feedback Adiabatic Logic (PFAL) An alternative technique to overcome the drawback of ECRL is PFAL which offers robustness against fluctuation in technology parameters. Figure 6 shows topology of PFAL technique which consists of latch made of two PMOS and NMOS transistors which are arranged in cross-coupled manner to prevent logic-level degradation on output nodes. Using this logic, various logic gates were implemented [4]. PFAL is one of the technique among the different adiabatic logic techniques where power saving could be achieved. The functional blocks are placed in parallel with PMOSFET latch. Compared to all other logic families of adiabatic, PFAL dissipates less power.

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Fig. 5 Transistor-level representation of full subtractor borrow block

5.2 Efficient Charge Recovery Logic (ECRL) Figure 7 shows the topology of ECRL design which consists of cross-coupled PMOS load and the pull-down path consists of NMOS functional blocks (F and /F). The precharge and evaluation operation is performed simultaneously, due to the presence of PMOS load [11] and one of the output is grounded at the hold phase of the power clock [11].

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Fig. 6 Topology of PFAL

Fig. 7 Topology of ECRL

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Fig. 8 Topology of 2N-2N2P logic

5.3 2N-2N2P Logic This adiabatic logic family is an alternative to ECRL design to eliminate the coupling effect faced by the circuits. Floating outputs are obtained in large part of recovery phase in circuit of ECRL and is less observed in case of 2N-2N2P logic. The functional blocks are placed in parallel to the cross-coupled NMOSFETs. This logic family’s timing and operations are identical to the ECRL family [5] and the general topology of 2N-2N2P Logic is as shown in Fig. 8.

5.4 Clocked Adiabatic Logic (CAL) M1 –M4 cross-coupling transistors provide memory functionality. Single power clock (pwr supply) is used to analyze adiabatic logic functions [6]. An auxiliary timing clock signal “Cx” is placed parallel to the M3 and M4 transistor, as shown in Fig. 9. This “Cx” signal controls the transistors in series with the NMOS logic trees represented by the F and /F function block.

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Fig. 9 Topology of CAL

6 SIMULATION R ESULT a ND DISCUSSION The working of 1-bit full adder and full subtractor comparison has been performed using conventional CMOS logic design and adiabatic logic design, namely ECRL, PFAL, 2N-2N2P Logic, and CAL under Cadence Virtuoso environment at 180 nm technology [12]. For full subtractor and full adder designed using adiabatic logic techniques, the outputs are obtained only when power clock (supply voltage) reaches its peak value which is contradiction to conventional full adder and full subtractor design. Simulation is performed at 200 MHz frequency with input 1.8 V at constant load capacitance of 10 f F and power reports are obtained for the same.

6.1 Simulation Results of Full Adder The simulation results for full adder design is obtained using adiabatic logic techniques with inputs applied as “a”, “b”, “c” and outputs obtained as sum and carry. Figure 10 shows the test circuit of PFAL full adder Fig. 11 shows the transient response of PFAL full adder at 200 MHz frequency. Figure 12 shows the test circuit of ECRL full adder. Figure 13 shows the transient response of ECRL full adder at 200 MHz frequency.

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Fig. 10 Test circuit of full adder using PFAL

Fig. 11 Transient response of full adder using PFAL

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Fig. 12 Test circuit of full adder using ECRL

Fig. 13 Transient response of full adder using ECRL

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Fig. 14 Test circuit of full adder using 2N-2N2P logic

Figure 14 shows the test circuit of 2N-2N2P Logic full adder. Figure 15 shows the transient response of 2N-2N2P logic full adder at 200 MHz frequency. Figure 16 shows the test circuit of CAL full adder. Figure 17 shows the transient response of CAL full adder at 200 MHz frequency.

6.2 Simulation Results of Full Subtractor The simulation results of full subtractor designed using adiabatic logic styles are obtained with inputs applied as “a,” “b,” “c” with outputs “Difference” and “borrow”. For full subtractor designed using adiabatic logic, the outputs are obtained only when the power clock reaches its peak value which is contradiction to conventional full subtractor design. Figure 18 shows the test circuit of PFAL full subtractor. Figure 19 shows the transient response of PFAL full subtractor at 200 MHz frequency using 10 f F load capacitance. Figure 20 shows the test circuit of ECRL full subtractor. Figure 21 shows the transient response of ECRL full subtractor at 200 MHz frequency. Figure 22 shows the test circuit of 2N-2N2P Logic full subtractor. Figure 23 shows

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Fig. 15 Transient response of full adder using 2N-2N2P logic

the transient response of 2N-2N2P logic full subtractor at 200 MHz frequency. Figure 24 shows the test circuit of CAL full subtractor. Figure 25 shows the transient response of CAL full subtractor at 200 MHz frequency.

6.3 Average Power Comparison Results Table 1 shows the power reduction of adiabatic logic compared with conventional CMOS design of full adder. From the report obtained, more than 50% power saving is achieved in case of full adder designed using adiabatic logic compared to CMOS logic design, that is about 74.55% power reduction is achieved in ECRL logic as compared to CMOS logic and about 85.57, 56.25, and 96.82% of power saving is achievable by 2N-2N2P Logic, CAL, and PFAL compared to CMOS logic. Table 2 shows the power reduction of adiabatic logic compared to conventional CMOS design. More than 50% power saving is achieved for full subtractor designed using adiabatic logic compared to CMOS full subtractor design, that is about 67% reduction of power is achievable in case of ECRL logic as compared to conventional CMOS logic and about 87.2, 84, and 90.4% of power saving is achievable using 2N-2N2P Logic, CAL logic, and PFAL compared to CMOS logic.

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Fig. 16 Test circuit of full adder using CAL

Fig. 17 Transient response of full adder using CAL

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Fig. 18 Test circuit of full subtractor using PFAL

Fig. 19 Transient response of full subtractor using PFAL

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Fig. 20 Test circuit of full subtractor using ECRL

Fig. 21 Transient response of full subtractor using ECRL

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Fig. 22 Test circuit of full subtractor using 2N-2N2P logic

Fig. 23 Transient response of full subtractor using 2N-2N2P logic

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Fig. 24 Test circuit of full subtractor using CAL

Fig. 25 Transient response of full subtractor using CAL

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382 Table 1 Power comparison of full adder

Table 2 Power comparison of full subtractor

Akshitha and N. Rajan Design method

Average power(µW)

Conventional design

30.08

CAL design

13.16

ECRL design

7.655

2N-2N2P design

4.339

PFAL design

0.956

Design method

Average power (µW)

Conventional design

58.48

ECRL design

19.2

CAL design

9.292

2N-2N2P design

7.456

PFAL design

5.586

7 Conclusion This paper proposes different techniques of adiabatic logic. A comparative study is performed between conventional CMOS design and adiabatic design [12]. Constant supply voltage was replaced by time-varying supply voltage for analysis and the output was obtained under certain condition in case of adiabatic logic which was contradiction to conventional CMOS design. The result obtained from the simulation shows that average power consumption for full adder designed using adiabatic logic techniques consumes more than 50% less power compared to conventional full adder design. Similarly, for full subtractor design, designed using adiabatic logic style, more than 50% power saving was achievable.

References 1. Mahmoodi-Meimand H, Afzali-Kusha A, Nourani M (2001) Adiabatic carry look-ahead adder with efficient power clock generator. IEEE Proc Circ Dev Sysl 148:229–234 2. Bhati P, Rizvi NZ (2016) Adiabatic logic: an alternative approach to low power application circuits. In: International conference on electrical, electronics and optimization techniques (ICEEOT) 3. Jayanthi D, Shankar AB, Raghavan S, Rajasekar G (2016) High speed multi output circuits using adiabatic logic. In: IEEE international conference on emerging trends in engineering, technology and science (ICETETS) 4. Pindoo IA, Singh T, Singh A, Chaudhary A, Mohan Kumar P (2015) Power dissipation reduction using adiabatic logic techniques for CMOS inverter circuit. In: 6th IEEE international conference on computing, communication and networking technology (ICCCNT) 5. Chaudhuri A, Saha M, Bhowmik M, Pradhan SN, Das S (2015) Implementation of circuit in different adiabatic logic. In: 2nd IEEE international conference on electronics and communication

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system (ICECS), pp 353–359 6. Haiyan N, Jianping H (2011) Near-threshold sequential circuits using improved clocked adiabatic logic in 45 nm CMOS processes. In: 54th IEEE (MWSCAS), pp 5–8 7. Mishra A (2016) Low power CMOS cell structures based on adiabatic switching. In: IEEE international conference on communication and electronics systems (ICCES) 8. Nayak SP, Kaur B (2016) Design of full adder in 180 nm technology using TG and adiabatic logic. Int J Comput Tech 3:164–170 9. Yadav R, Bakshi A, Chowdhury J, Das JK (2018) Adiabatic approach for charge restoration in low power digital circuits. In: 2nd IEEE international conference on inventive systems and control (ICISC), pp 473–477 10. Tulasi GR, Venugopal K, Vijayabaskar B, Prakash RS (2012) Design and analysis of full adders using adiabatic logic. Int J Eng Res Technol (IJERT) 1:1–6 11. Keote ML, Karule PT (2015) Design and implementation of energy efficient adiabatic ECRL and basic gates. In: IEEE international conference on soft computing techniques and implementations (ICSCTI), pp 87–91 12. Pratap S, Kushawaha S, Sasamal TN (2015) Modified positive feedback adiabatic logic for ultra low power VLSI. In: IEEE international conference on computer, communication and control

Design and Implementation of Multiple-Output CMOS Voltage Level Shifter S. Swaroop and K. S. Ravindra

Abstract Different parts such as digital, analog, passive components are manufactured on a single chip in system on chip (SoC) design and require different voltages to achieve optimum performance. The voltage level shifter (LS) is a device that changes over level of voltage to other level of voltage. Different circuit squares working at various supply voltages are interfaced with voltage LS. The SoC voltage LS is used at the edge of various islands of voltage. Single-output and multiple-output CMOS LS are implemented. The proposed voltage LS converts low voltage input to high voltage output with higher speed and lower power consumption. The design of the architecture is implemented using CMOS technique. Multi-threshold voltage CMOS technology is used to decrease power and delay when designing the voltage LS. To minimize delay, device with low-threshold voltage is used. Using high-threshold voltage devices, power dissipation can be reduced. In 45 nm technology, the design was implemented. Comparison is made of the power dissipation and propagation delay. Keywords Very large scale integrated circuit (VLSI) · Complementary metal oxide semiconductor (CMOS) · Level shifter (LS) · Low voltage transistors (LVT) · High voltage transistors (HVT) · Standard voltage transistor (SVT)

1 Introduction This is the era where the electronic devices are ruling the world. Almost in every field, electronic devices are used [1]. Due to this low power consumption, the development of a circuit and a system plays a very important role. Increasing power consumption results in a reduction in responsibility, and the value of packaging is high. VLSI circuit power consumption is made up of dynamic and static power consumption. S. Swaroop (B) · K. S. Ravindra Department of ECE, NMAM Institute of Technology, Nitte, Karkala, India e-mail: [email protected] K. S. Ravindra e-mail: [email protected] © Springer Nature Singapore Pte Ltd. 2020 S. Kalya et al. (eds.), Advances in Communication, Signal Processing, VLSI, and Embedded Systems, Lecture Notes in Electrical Engineering 614, https://doi.org/10.1007/978-981-15-0626-0_31

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Dynamic power consumption due to the loading and unloading of the load capacity and the static power consumption due to nonzero input waveform rise and fall times. As complementary metal oxide semiconductor (CMOS) circuits have a static power. Whereas the static power of the complementary metal compound semiconductor (CMOS) circuits dictated by the surge through every intersection transistor. VLSI circuit control utilization is normally decreased by scaling the voltage and limit. At the point when voltage is decreased, issues, for example, little voltage swing; light commotion edge and overflowing flows emerge. With the innovation occasion in the submicron locale, out fueling has turned into a noteworthy issue of aggregate dispersal of intensity. Static power ought to be considered as a component of intensity utilization if current patterns in the scaling size and voltage supply are to be kept up. Multi-level voltage domain technology is an effective way to reduce dissipation of power [10]. Wherever each domain operates at different power supply levels, the planning is divided into separate voltage domains during this technology. The voltage LS is used in multi-level voltage style to interface different domains. CMOS LSs unit area consist of two types, low LSs and high LSs [2].

1.1 Literature Survey Summarizing the papers [1–20], the concepts that help for the presented work are basic level shifter, conventional level shifter, single supply level shifter, modified single supply level shifter, single-output CMOS voltage level shifter, multiple-output CMOS voltage level shifters and also about reducing power dissipation and propagation delay in various CMOS level shifters.

1.2 Basic CMOS LS Basic CMOS LS is shown in Fig. 1. It consists of two PMOS transistors MP1 and MP2, and two NMOS transistors MN1 and MN2. One voltage source is VDDH. MN2 is given an inverted input of MN1. Two PMOS transistors MP1 and MP2 are arranged in cross-coupled form.

2 Multi-level Voltage Design Principle Using Single-Output CMOS Voltage LS In up to date chips, the technique of multi-level voltage region is wide accustomed trade-off power and speed [10]. It is utilized in LSs as numerous blocks work on distinct voltages. To remodel from one voltage domain to a different, LSs are used, significantly from low voltage to elevated voltage [4]. It is accustomed remodel the

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Fig. 1 Basic CMOS LS [1]

signals between the two threshold voltage domains within the variety of the differential cascade voltage switch (DCVS). Time-critical domain runs at high voltage of power provide (VDDH), and non-critical domain operates at reduced voltage of supply (VDDL). Variation within the delay, static power and price of energy dissipation happens in line with the voltage amendment. Once SoCs’ energy domain or breadth will increase the number of level shifters, it improves delay and power, particularly from low voltage to high voltage. Low power consumption has become a major design in current devices. With increased power consumption, irresponsibility also increases and packaging value increases [8]. The multi-level voltage design in Fig. 2 consists of a 4:1 multiplexer, a shifter at voltage level and a static random-access memory (SRAM). The 4:1

Fig. 2 Multi-level voltage design using SRAM

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Fig. 3 Multi-level voltage design using DRAM

multiplexer operates at low voltage compared to SRAM, which means that the CMOS level up shifter increases the voltage level suitable for SRAM operation. The multi-level voltage design in Fig. 3 consists of a 4:1 multiplexer, voltage LS and a dynamic random-access memory (DRAM). The 4:1 multiplexer operates at low voltage compared to DRAM, which means that the CMOS level up shifter increases the voltage level suitable for DRAM operation.

2.1 Single-Output CMOS Voltage LS The schematic of single-output CMOS voltage LS is shown in Fig. 4. LVT are MN1, MN2, MN3, MP1, MP2 and MP3 transistors. Transistors from MP4 to MP11 are HVT, and transistors from MN4 are SVT thresholds. The structure operates with provided voltages from VDDL and VDDH. Once MP4 and MP5 are off, HVTs, MP4 and MP5 are wont to cut back the pull-up network outpouring current. The parallel connected transistors MP6–MP10 and MP7–MP11 are wont to cut back the N1 and N2 node shift delay as HVTs decrease node switching. The MP10 and MP11 transistors are sized to limit the flow of outpouring gift through N1 and N2 nodes. With serially coupled HVTs MP8, MP9 and SVT MN4, this at node N1 is drastically cut. Once the Vin signaling is little and Vin high, the N1 node voltage level at N2 is high and low. Transistors MP5 and MP10 are shifted which implies node N3 voltage is smaller than VDDH thanks to MP6 saturation voltage because it may be a diode-connected electronic transistor. Conjointly switched on is MP4 and MP11, and N4 is that the same as VDDH. As a result of node N1 is massive, the result of that output node Vout is coupled to the ground is on MN4. The node N1 discharges, once input Vin will increase from low to elevated, whereas node N2 starts charging at node N4 by voltage. The MP4 electronic transistor switches off and accelerates the discharge of the N1 node. Transistor MP5 activates once the total discharge of the N1 node is attributable to MP7 saturation voltage, and node N3 voltage is VDDH once input Vin transition and voltage level N4 are smaller than VDDH. It activates the MP8 and MP9 electronic transistor as N1 is a force all the way down to the ground, increasing the Vout node to VDDH (Table 1).

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Fig. 4 Schematic implementation of single-output CMOS voltage LS

2.2 Multi-level Voltage Design Schematic Implementation Using SRAM Figure 5 shows the multi-level voltage design, i.e., combination of 4:1 MUX, singleoutput CMOS LS and SRAM. The 4:1 MUX operates at low voltage, but SRAM requires comparatively high voltage for its operation; hence, the output (M) of 4:1 MUX is given as an input to CMOS voltage LS. The CMOS voltage level shifter shifts the voltage of input signal to the voltage required for the operation of SRAM. The CMOS voltage LS output (L) is given as a SRAM input.

390 Table 1 Transistor sizes of single-output CMOS voltage LS

S. Swaroop and K. S. Ravindra Transistor

W/L

MP1

120/45

MP2

120/45

MP3

120/45

MP4

320/150

MP5

320/150

MP6

320/150

MP7

320/150

MP8

320/150

MP9

320/150

MP10

320/150

MP11

320/150

MN1

120/45

MN2

120/45

MN3

120/45

MN4

120/45

Fig. 5 Combination of 4:1 MUX, CMOS LS and SRAM

2.3 Multi-level Voltage Design Schematic Implementation Using DRAM Figure 6 shows the multi-level voltage design, i.e., combination of 4:1 MUX, singleoutput CMOS LS and DRAM. The 4:1 MUX operates at low voltage, but DRAM requires comparatively high voltage for its operation. The output of 4:1 MUX is

Fig. 6 Combination of 4:1 MUX, CMOS LS and SRAM

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therefore given as the CMOS voltage LS input. The CMOS voltage LS transfers the input signal voltage to the voltage required for DRAM operation. The CMOS voltage LS output is given as a DRAM input.

3 Multi-level Voltage Design Principle Using Multiple-Output CMOS Voltage Ls The multi-level design shown in Fig. 7 consists of 4:1 multiplexer, multiple-output CMOS voltage level up shifter, SRAM and DRAM. The 4:1 multiplexer operates at low voltage compared to SRAM and DRAM; hence, CMOS level up shifter is used to increase the voltage levels which is suitable for the operation of SRAM and DRAM.

3.1 Conventional Multiple-Output CMOS Voltage LS Conventional multiple-output CMOS voltage LS shown in Fig. 8 consists of only one voltage source VHIGH = 5 V, one input signal Vin, which is the output from low voltage operating device. It has two outputs OUT1 and OUT2. OUT1 and OUT2 are the complement of OUT1 and OUT2, respectively. It has four input signals A, B, C, D with voltage levels 1 V, 1 V, 3.3 V and 3.3 V, respectively. The signals at Vin and Vin nodes are digital signals and Vin s signal comes from the digital controller

Fig. 7 Multi-level voltage design using multiple-output CMOS voltage LS

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Fig. 8 Schematic implementation of conventional multiple-output CMOS voltage LS

circuit. Due to coupling or load loss, the voltages at one of the outputs drop, there is no circuit to pull that node to the desired state which results in improper functionality.

3.2 Proposed Multiple-Output CMOS Voltage LS Proposed multiple-output CMOS voltage LS shown in Fig. 9 consists of only one voltage source VHIGH = 3.3 V, one input signal Vin, which is the output from low voltage operating device. It has two outputs OUT1 and OUT2. OUT1 and OUT2

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Fig. 9 Schematic implementation of proposed multiple-output CMOS voltage LS

are the complement of OUT1 and OUT2, respectively. It has four input signals A, B, C, D with voltage levels 1 V, 1 V, 2 V and 2 V, respectively. Vin and Vin node signals are digital signals, and Vin’s signal comes from the circuit of digital controller. The LS comprises of half latch consisting of two MP9 and MP10 PMOS transistors. MP9 and MP10 provide the circuit with positive feedback and accelerate the settlement of OUT2 and OUT2 nodes after being excited by MN1 and MN2 driven inputs from Vin and Vin . The pull-up and pull-down strengths of MP9 (MP10) and MN1 (MN2) must be balanced in the circuit so that the pull-down transistors can discharge the output nodes that exceed the output status sufficiently that remain latched by the MP9 and MP10 PMOS transistors. The transistors MN3–MN6 and MP1–MP8 are used in cascaded fashion to avoid any voltage stress in the devices.

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Table 2 Transistor sizes of proposed multiple-output CMOS voltage LS Transistor

W/L

Transistor

W/L

MP1

120/45

MP9

120/45

MP2

120/45

MP10

120/45

MP3

120/45

MN1

120/45

MP4

120/45

MN2

120/45

MP5

120/45

MN3

120/45

MP6

120/45

MN4

120/45

MP7

120/45

MN5

120/45

MP8

120/45

MN6

120/45

When the Vin is logic low transistor MN1 will be ‘OFF’ and transistor MN2 will be ‘ON,’ since the complemented input is given to transistor MN2. The node OUT1 and OUT2 will be charged to 2 V and 3.3 V, respectively. When Vin is logic high, transistor MN1 will be ‘ON’ and transistor MN2 will be ‘OFF.’ The node OUT1 and OUT2 will be charged to 2 V and 3.3 V, respectively (Table 2).

3.3 Multi-level Design Schematic Implementation Multi-level voltage design implemented using multiple-output CMOS voltage LS is shown in Fig. 10, i.e., combination of 4:1 MUX, multiple-output CMOS LS, SRAM and DRAM.

Fig. 10 Combination of 4:1 MUX, multiple-output CMOS LS, SRAM and DRAM

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The 4:1 MUX operates at low voltage, but SRAM and DRAM requires comparatively high voltage for its operation; hence, the output of 4:1 MUX is given as an input to multiple-output CMOS voltage LS. The multiple-output CMOS voltage level shifter shifts the input signal voltage to the voltages required for SRAM and DRAM operation. The outputs of the CMOS voltage LS is given as an input to SRAM and DRAM.

4 Simulation Results 4.1 Output Waveforms Figure 11 shows the output waveform of single-output CMOS voltage LS. The given input signal is 0.7 V, VDD = 3.3 V, and it is observed that the voltage output is up to 3.3 V. Figure 12 shows the output waveform of proposed multiple-output CMOS voltage LS. The given input signal is 0.7 V, VDD = 3.3 V. It is observed that the output voltage level is up-shifted to 3.3 and 2 V. The threshold voltages of the transistors in 45 nm technology is found to be 0.3 V, and hence, the output voltage levels are shifted to 3.3 and 2 V. Figure 13 shows the output waveform of multi-level voltage design. The output of the 4:1 MUX is given to CMOS LS to level up the voltage. The LS output is given to the SRAM as an input.

Fig. 11 Output waveforms of single-output CMOS voltage LS

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Fig. 12 Output waveforms of multiple-output CMOS voltage LS

Fig. 13 Final output waveforms of the combinational circuit (MUX + single-output CMOS LS + SRAM)

Figure 14 shows the output waveform of multi-level voltage design. The output of the 4:1 MUX is given to CMOS LS to level up the voltage. The LS output is given to the DRAM as an input.

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Fig. 14 Final output waveforms of the combinational circuit (MUX + single-output CMOS LS + DRAM)

Figure 15 shows the output waveform of multi-level voltage design. The output of the 4:1 MUX is given to multiple-output CMOS LS to level up the voltage. The LS output is given as SRAM and DRAM input.

Fig. 15 Final output waveforms of the combinational circuit (MUX + multiple-output CMOS LS + DRAM + SRAM)

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Fig. 16 Power plot of single-output CMOS voltage LS

4.2 Power Plots Figure 16 shows the power plot of single-output CMOS voltage LS. The overall power dissipation of the CMOS LS is 20.21 µW. The single-output CMOS voltage LS uses current generator circuit, which provides voltage conversion current only during transition to reduce the dissipation of static power [8]. Figure 17 shows the power plot of multiple-output CMOS voltage LS. The overall power dissipation of the CMOS LS is 9.214 µW. By using high-threshold voltage devices, power dissipation is reduced [8] (Figs 18, 19 and 20).

Fig. 17 Power plot of multiple-output CMOS voltage LS

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Fig. 18 Power plot of combinational circuit (MUX + single-output CMOS voltage LS + SRAM)

Fig. 19 Power plot of combinational circuit (MUX + single-output CMOS voltage LS + DRAM)

5 Conclusion See Table 3. Multi-level voltage design has been implemented using single-output and multiple-output CMOS voltage LS in Cadence tool. Multi-level design includes 4:1 multiplexer, single-output CMOS voltage LS, SRAM and DRAM. A single-output and multiple-output CMOS voltage LS has been implemented for multi-level voltage designs in 45 nm technology. The power dissipation and propagation delay of the multi-level design implemented using single-output and multiple-output CMOS LSs are compared. The power dissipation of combinational circuit implemented using single-output CMOS LS is found to be 127.374 µW and propagation delay 456 ps.

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Fig. 20 Power plot of combinational circuit (MUX + single-output CMOS voltage LS + SRAM + DRAM)

Table 3 Comparison of combinational circuit implemented using single-output CMOS LS and multiple-output CMOS LS Level shifter

Power consumption (µW)

Propagation delay(pW)

Single output

127.374

456

Multiple output

100.21

74.02

The power dissipation of the combinational circuit implemented using multipleoutput CMOS LS is found to be 100.21 µW and propagation delay 74.02 ps. It is observed that the multi-level design implemented using multiple-output CMOS LS has low power dissipation and propagation delay compared to multi-level design implemented using single-output CMOS LS. It is observed that the power dissipation of multiple-output CMOS voltage LS is decreased by 21.33% when compared to single-output CMOS voltage LS. Hence, multiple-output CMOS LS is preferred over single-output CMOS LS when both power dissipation and speed is concerned. Also, area can be reduced using multiple-output CMOS voltage LS.

References 1. Nisha RM (2016) High speed level shifter design for low power application using 45 nm technology. IEEE Trans Very Large Scale Integr (VLSI) Syst 13(9):1103–1107 2. Wang W-T, Ker M-D, Chiang M-C, Chen C-H (2001) Level shifters for high-speed 1–3.3V interfaces in a 0.13 µm Cu-interconnection/low-k CMOS technology. In: International symposium on VLSI technology, systems, and applications, pp 307–310, IEEE 3. Han S-M, Nam W-J, Park H-S, Kim S-J, Park K-C, Han M-K (2006) A low power wide range CMOS poly-Si level shifter for active matrix display. In: Proceedings of Asian symposium on information display (ASID), New Delhi

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4. Kumar M, Arya SK, Pandey S (2010) Level shifter design for low power applications. Int J Comput Sci Inf Technol (IJCSIT) 2(5) 5. Gupta Shweta, Kumar Manoj (2013) CMOS voltage level-up shifter—a review. Int J Adv Eng Sci 3:71–74 6. Thakur S, Mehra R (2013) CMOS design and single supply level shifter using 90 nm technology. In: Conference on advances in communication and control systems, vol 8, No 7 7. Liu W, Salman E, Sitik C, Taskin B (2015) Enhanced level shifter for multi-voltage operation. In: International symposium on circuits and systems (ISCAS), pp 1442–1445, IEEE 8. Gosatwar P, Ghodeswar U (2016) Design of voltage level shifter for multi-supply voltage design. In: International conference on communication and signal processing (ICCSP), pp 0853–0857, IEEE 9. Badal MT, Reaz MM, Farayez A, Ramli SA, Kamal N (2017) Design of a low-power CMOS level shifter for low-delay SoCs in silterra 0.13 µm CMOS process. J Eng Sci Technol Rev 10(4):10–15 10. Rana V, Sinha R (2018) Stress relaxed multiple output high-voltage level shifter. IEEE Trans Circ Syst II Express Briefs 65 2:176–180 11. Gupta HS, Kirkire S, Bhati S, Chaurasia RS, Mehta S, Choudhary AR, Patel D, Vaghela J (2015) Bipolar voltage level shifter. In: International symposium on VLSI design and test (VDAT), pp 1–5, IEEE 12. García JC, Juan A, Nooshabadi S (2017) Single supply CMOS up level shifter for dual voltage system. In: International symposium on circuits and systems (ISCAS), pp 1–4, IEEE 13. Cai J, Halak B, Rossi D (2016) Analysis of BTI aging of level shifters. In: International symposium on on-line testing and robust system design (IOLTS), pp 17–18, IEEE 14. Haas M, Ortmanns M (2016) A floating high-voltage LS with high area efficiency for biomedical implants. In: Conference on Ph.D. research in microelectronics and electronics (PRIME), pp 1–4, IEEE 15. Gak J, Miguez M, Arnaud A, Mandolesi PS (2017) Blind range level shifters from 0 to 18 V. In: Latin American symposium on circuits and systems (LASCAS), pp 1–4, IEEE 16. Pashmineh S, Killat D (2015) Design of high-voltage level shifters based on stacked standard transistors for a wide range of supply voltages. In: Symposium on integrated circuits and systems design (SBCCI), pp 1–6, IEEE 17. Patkar K, Akashe S (2016) Design of level shifter for low power applications. In: Symposium on colossal data analysis and networking (CDAN), pp 1–4, IEEE 18. Kim TTH (2018) An area and energy efficient ultra-low voltage level shifter with pass transistor and reduced-swing output buffer in 65 nm CMOS. IEEE Trans Circ Syst II Expr Briefs 65(5):607–611 19. Thomas S, Varghese GT (2017) Design of optimum power, delay efficient level shifter for biomedical applications. In: International conference on intelligent computing, instrumentation and control technologies (ICICICT), pp 219–222, IEEE 20. Frenila JB, Paglinawan AC (2017) Design of a 1.8 V-input 6.5 V-output digital level shifter for trimming application. In: International conference on humanoid, nanotechnology, information technology, communication and control, environment and management (HNICEM), pp 1–6, IEEE

Design and Development of Multi-output Isolated Supply for SiC MOSFET Gate Driver Using Flyback Topology C. Shreya, G. Praveen Kumar, Vikhyath D. Amin and K. Suryanarayana

Abstract Power electronic converters have undergone major advancements in last few decades and have influenced human life in many aspects. Design of any converter is an arduous task. One of the major challenges faced in converter design is to drive high-side MOSFETs, since the source terminal has no specific reference. To address this, isolated supply employing flyback topology is designed to provide proper reference to top switches. In the current design, twelve isolated power supplies are generated to cater a requirement of four-leg system. The flyback topology is operated in discontinuous conduction mode and accepts universal voltage inputs. The current-mode PWM controller is used to generate necessary gate signal for the flyback MOSFET. Theoretical approach towards the flyback converter design, transformer windings and snubber calculation are discussed in this paper. Simulations are carried out using MATLAB/Simulink and compared with the practical results. Keywords Multi-output · Isolated supply · SiC MOSFET · Gate driver · Flyback topology

1 Introduction Linear voltage regulators were one of the simple methods of stepping down unregulated DC to regulated DC voltage. In linear regulators, semiconductor device is operated in active region. This leads to the voltage difference from input to output C. Shreya · G. Praveen Kumar (B) · V. D. Amin · K. Suryanarayana Department of Electrical and Electronics Engineering, N.M.A.M. Institute of Technology, Nitte, India e-mail: [email protected] C. Shreya e-mail: [email protected] V. D. Amin e-mail: [email protected] K. Suryanarayana e-mail: [email protected] © Springer Nature Singapore Pte Ltd. 2020 S. Kalya et al. (eds.), Advances in Communication, Signal Processing, VLSI, and Embedded Systems, Lecture Notes in Electrical Engineering 614, https://doi.org/10.1007/978-981-15-0626-0_32

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that appears across the switch. In applications with higher voltage conversion ratios, large voltage will appear across the switch leading to huge power dissipation and poor system efficiency [1]. In today’s world, there is a demand for reliable, compact and efficient system that can be achieved by an alternate method, namely switch-mode power supplies [2]. Switch-mode power supply circuits employ semiconductor devices like MOSFETs, IGBTs, etc. [1]. The semiconductor devices are operated in saturation and cut-off region resulting in lower power dissipation, increased efficiency and reduced cost. In converters employing SiC MOSFETs, driving scheme demands both positive and negative voltages to turn ON and OFF the switches. When positive voltage is applied across gate–source terminals, gate-to-source capacitance gets charged and power device turns ON, allowing current to flow from drain-to-source terminal. When negative voltage is applied, gate-to-source capacitance discharges and device turns OFF, and a large voltage is blocked across drain and source terminals [3]. Switch-mode DC–DC power supplies can be step-up or step-down voltages and are classified as isolated and non-isolated converters [4]. Circuits with galvanic isolation are termed as isolated converters. Buck, boost, buck–boost and Cúk are nonisolated and flyback, forward and push–pull are isolated converter topologies. Among these topologies, flyback is widely used SMPS for low-power applications [4, 5]. In converter circuits, the major challenge is to drive top-side switch due to variation in potential at source terminal. Various driving methods like gate-driver transformer, Bootstrap bias supply with capacitive signal isolation, isolated bias supply with isolated high-side gate driver, bootstrap bias supply with high/low-side gate driver and gate-driver transformer [6] are widely used techniques in driving the high-side switches. Bootstrap provides reference to the floating power supply for high-side switch gate drivers. Bootstrap circuits are preferred over high-frequency transformer circuits due to its less complexity, low cost and high reliability. Bootstrap technique has its own limitations due to the periodic charging time requirement. One of the approaches to overcome the limitation is auxiliary charge pumps [7]. The amount of charge to be pumped depends on charge required by the gate terminal. Another widely used approach is isolated bias supply with isolated high-side gate driver which demands independent supply for every top-side switch. Silicon devices like MOSFET or IGBT demand voltage swing between 0 and 15 V. However, state-of-the-art devices like SiC MOSFETs expect the voltage swing from −3.3 to 15 V leading to increased design complexity. A low-power isolated supply in the range from 20 to 30 W is desirable for SiC-based four-leg system (stack). This paper discusses the design and implementation of flyback converter for four-leg system with SiC MOSFETs. The paper is organized as follows: Sect. 1 gives brief introduction of gate-driver requirements. Theoretical background is discussed in Sect. 2. Design considerations are discussed in Sect. 3, and Sect. 4 addresses compensator design for the converter. Section 5 deals with simulations of open- and closed-loop flyback converter. Section 5.1 deals with hardware implementation of gate-driver circuit of SiC-based 2 kW stack. Practical results of designed converter are discussed in Sect. 5.1, and Sect. 6 concludes overall design strategy.

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2 Theoretical Background Driving power electronic devices is a challenging task. When the control terminal device is referred to common reference, control signal generation will be easier. However, while driving the top-side switches, the reference point will have different potential and such situations demand isolated power supplies. One of the most widely used supplies is flyback converter.

2.1 Flyback Topology Flyback converter consists of a coupled inductor, primary switch (MOSFET), secondary diode and output filter capacitor [8]. The basic circuit diagram of flyback converter is shown in Fig. 1. Primary inductance of the converter will govern the mode of operation as continuous conduction mode (CCM) or discontinuous conduction mode (DCM) [9]. The circuit operation could be analysed as: Mode 1—When the MOSFET is ON In this mode, applied DC voltage appears across primary of the transformer, and energy is stored. Energy is not transferred to the secondary as diode in the circuit is reverse-biased in the circuit. Desired output voltage is maintained by the filter capacitor C. Figure 2 shows the equivalent circuit when MOSFET is turned ON. In DCM, primary current rises from zero to i PEAK , and voltage across the switch VDS is zero as shown in Fig. 3a. In CCM, primary current ramps from i out to i PEAK , and VDS is zero as shown in Fig. 3b. Voltage across the primary winding and the diode could be written as: di L m (t) dt   N2 vD = −V0 − Vs N1

vL (t) = vg (t) = L m

Fig. 1 Flyback converter

(1) (2)

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Fig. 2 Equivalent circuit when MOSFET is ON

Fig. 3 Timing diagram

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Fig. 4 Equivalent circuit when MOSFET is OFF

Mode 2—When the MOSFET is OFF In this mode, the switch is OFF and primary current is interrupted as in Fig. 4. Due to the reversal of transformer voltage polarities, diode in the secondary is forwardbiased, and stored energy in the primary is transferred to secondary. In DCM, current to zero as shown in Fig. 3a. VDS will be Vin +kVout through diode D will drop from iPEAK k till secondary current i s reaches zero, and VDS remains at Vout till t2 . In CCM, current to iOUT as in Fig. 3b, and VDS will be through the diode D linearly falls from iPEAK k k Vin + kVout . Flyback converter is a buck–boost-derived converter, and its output voltage is given by: Vout = where k =

N2 N1

Vin ∗ D k ∗ (1 − D)

(3)

and D is the duty cycle.

2.2 Snubber Circuit Design Ideal characteristics during MOSFET switching are a square wave. However, due to leakage inductance of the transformer, a large voltage spike will be seen across the MOSFET during turn OFF process. Leakage inductance along with stray capacitance produces unavoidable ringing across the switch [10]. Snubber circuits are widely used techniques to minimize voltage spikes. They provide alternative path to dissipate leakage energy and reduce stress on the switch. Figure 5 shows RCD and TVS diode snubber circuit used in flyback converters. In RCD snubber, D turns ON when drain voltage of the switch exceeds the clamp capacitor voltage. The clamp capacitor provides current path once diode starts conducting. Major drawback of RCD is that energy stored in leakage inductance is dissipated in the resistor R1 . To overcome this, R&C is replaced with diode known as transient voltage suppressor (TVS). TVS

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Fig. 5 Snubber circuit for flyback converter, a RCD, b TVS

diode pumps the stored energy back to the source. Therefore, TVS diode results in better performance by clamping the voltage across primary switch [11].

3 Design Considerations The proposed converter is designed to have twelve isolated power supplies with wide input voltage range as in Fig. 6. Flyback converter provides isolated supply of +15 V and −3.3 V to the gate driver. In a four-leg system, high-side switches require eight and low side requires two isolated supplies. A 15 V winding is used as an auxiliary supply to power flyback PWM controller IC. A 9 V is generated to cater requirement of on-board ICs and circuits. The converter specifications are as shown in Table 1.

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Fig. 6 Sub-system block diagram Table 1 Design parameters S. No.

Description

Specification

1

Input DC

250–700 V

2

Maximum output power

30 W

3

Switching frequency

50 kHz

4

Output ripple

1%

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3.1 Power Rating Power rating of the supply depends on gate charge of the MOSFET [12]. The average power per gate driver could be computed as:   PGD,avg = Q g ∗ f SW ∗ VGS,on − VGS,off

(4)

PGD,avg is found to be 640.5 mW for Q g = 35 nC (C3M0065100 K device), f sw = 1 MHz, VGS,on = +15 V and VGS,off = −3.3 V. Hence, individual power supply wattage is chosen as 1 W. To drive entire four-leg system, the power requirement is estimated to be 20 W.

3.2 Current-Mode PWM Controller UCC28C44 from Texas Instruments is a PWM controller with peak current-mode control [13]. Initial, start-up current for PWM controller IC is derived from the rectified DC using start-up resistors. Start-up resistors are configured such that when DC bus voltage reaches 250 V, UCC28C44 will start operating and 15 V will appear on auxiliary winding. Desired output voltage must be signal conditioned to 2.5 V which will be compared with the reference voltage to generate the error signal. The current feedback is obtained from voltage across a current sense RSENSE resistor that senses the primary current. The value of RSENSE could be computed as: RSENSE =

1 1.1 ∗ IDS,PEAK

(5)

The voltage at current sense pin has a threshold of 1 V that could be used to protect the system from over current or short circuit. In order to initiate the process of PWM generation from UCC28C44 controller, RC oscillator circuit is used and the oscillator frequency is given by: f =

1 RC

(6)

For switching frequency of 50 kHz, the designed values of R = 8.2 k and C = 2200 pF are used. PWM generated at the output terminal of IC is used to drive the gate of MOSFET.

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Table 2 System parameter values S. No.

Component

Value

1

Primary inductance

4 mH

2

Peak primary current

0.5 A

3

Transformer core

EE 30/15/7

4

Primary turns

120

5

Auxiliary turns

1

6

Auxiliary capacitor

1 µF

7

Secondary capacitor

10 µF

8

Snubber resistor

78.7 

9

Snubber capacitor

150 pF

3.3 Flyback Converter Design Flyback topology-based SMPS unit is designed considering the parameters shown in Table 2[14].

3.4 Flyback Transformer Winding Transformer construction plays an important role in reducing the leakage inductance of primary winding. Leakage inductance leads to voltage spikes during turn OFF process of MOSFET. In order to minimize the leakage inductance, split primary winding technique is adopted [15]. In multi-output system, primary winding is split according to the number of secondary windings. In split primary winding technique, the winding sequence is primary 1, a layer of insulation tape, secondary 1, a layer of insulation tape, and primary 2 as in Fig. 7. The flyback transformer winding table is as shown in Table 3.

Fig. 7 Transformer winding pattern

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Table 3 Transformer winding table S. No.

Supply details

Voltage (V)

Current (A)

No. of turns

1

PWM controller

15

0.5

11

2

Microcontroller

9

0.5

7

3

Switches +ve ref

15

0.07

11

4

Switches –ve ref

0.03

3

3.3

4 Compensator Design The design of any switch-mode power supply requires good compensator design for the system to be stable. An uncompensated system may result in instability and poor regulation. A proper compensator would help in better regulation and also stable operation of the system. Loop compensation stabilizes the unstable system and reduces the oscillations [16]. For a given system, open-loop transfer function is given by [17]:  G(s) = 20 log

PWRTSGgain (1 + s( f )ESRCOUT ) 1 + s( f )ROUT COUT

 (7)

where PWRTSGgain is power-stage DC gain and is given by:  PWRTSGgain =

VIN IPEAK

k ROUT 2L P f SW

(8)

VIN is input DC voltage, f SW switching frequency and k=

N2 N1

(9)

ROUT and COUT are the load resistor and capacitor of auxiliary winding, ESR is equivalent series resistance of COUT . Bode plot of loop gain is shown in Fig. 8. The open-loop gain has a cross-over frequency of 6 kHz with a phase margin of 90°. The compensator has a cross-over frequency of 9.9 kHz with a phase margin of 37.3°. Error amplifier transfer function is given by: EAgain =

20 log(1 + s RC1 )

1 C2 ) s R FB (C1 + C2 ) 1 + (s(CRC 1 +C 2 )

(10)

where R = RFB ∗ 10

EAgain 20

(11)

Design and Development of Multi-output Isolated Supply …

413

Fig. 8 Bode plot of the implemented system

C1 =

1 2π f ZERO

(12)

C2 =

1 2π f POLE

(13)

where f ZERO = 5 Hz and f POLE = 5 kHz was chosen. Figure 8 shows the compensated bode plot.

5 Simulation and Results The flyback converter is simulated for open- and closed-loop conditions using MATLAB/Simulink tool and model as shown in Figs. 9, 10 and 11. Components used for the simulation include a DC voltage source, MOSFET, linear transformer model, diode, capacitors, resistors and scopes. The significant difference between open and closed loops is that in closed loop, the output voltage is fed back so that PWM controller can regulate the output to a desired value. Simulation results of open and closed loops are shown in Figs. 12 and 13. From the simulation results, it can be observed that in closed-loop system, the output voltage is regulated to 12 V.

414

Fig. 9 Simulink model of flyback converter—open loop

Fig. 10 Simulink model of flyback converter—closed loop

Fig. 11 Flyback converter—closed loop PWM generation

C. Shreya et al.

Design and Development of Multi-output Isolated Supply …

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Fig. 12 Open loop output voltage

Fig. 13 Closed loop output voltage

5.1 Hardware Implementation A three-phase 2 kW SiC-based stack is designed and developed and shown in Fig. 14. The designed flyback converter is a subsystem of three-phase stack. It is used to provide isolated supply for the gate drivers of SiC MOSFETs. The subsystem is designed with parameters shown in Table 1. The designed converter is tested for rated voltage of 325 V DC. Drain-to-source voltage across the MOSFET is shown in Fig. 15. Figure 16a shows the waveform of regulated output

416

Fig. 14 2 kW stack with flyback converter

Fig. 15 Drain to source voltage of flyback switch

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Fig. 16 Measurements, a regulated 15 V, b unregulated 9 V

of 15 V, and ripple is observed to be less than 1%. Figure 16b is the waveform of isolated unregulated output of 9 V which could be used to power the microcontroller circuit.

6 Conclusion This paper deals with design and development of multi-output flyback converter for gate-driver circuit. The converter is designed for 12 multiple outputs. The flyback converter is tested and found to be working within the limits maintaining constant voltage regulation with ripple voltage less than 1%. Compensation loop of flyback converter is studied to maintain constant output voltage. The flyback-based gate driver proved to be a better alternative method compared to traditional bootstrap, to drive high-side SiC MOSFETs. MATLAB/Simulink simulated results were compared with practical test results, and a similar performance was observed. Acknowledgements Authors would like to thank management of NMAM Institute of Technology for funding the project, Dr. Niranjan N. Chiplunkar, Principal, NMAMIT and Dr. Nagesh Prabhu, HOD, Department of EEE for supporting throughout the project journey. A special thanks to Mr. Ravikiran Rao M., Mrs. Swathi Hatwar H. and Mrs. Raksha Adappa for their constant support and motivation.

References 1. Mohan N, Undeland T (2007) Power electronics: converters, applications, and design. Wiley India, 2007 (Online). Available: https://books.google.co.in/books?id=oxR8vB2XjgIC 2. Hart DW (1996) Introduction to power electronics (3rd edn). Prentice Hall, PTR 3. Sapre S Analog dialogue, isolated gate drivers-what, why and how? Analog Dialogue, Tech. Rep

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4. Sreedevi A, Gopal M (2015) Simulation and hardware implementation of 24 watt multiple output flyback converter. In: 2015 international conference on power and advanced control engineering (ICPACE), Aug 2015, pp 366–370 5. Mohammed AA, Nafie SM (2015) Flyback converter design for low power application. In: 2015 International conference on computing, control, networking, electronics and embedded systems engineering (ICCNEEE), Sep. 2015, pp 447–450 6. Application Report (2018) SLUA669A using a single-output gate-driver for high-side or lowside drive. Texas Instruments, Tech. Rep 7. Jahns TM (2005) A self-boost charge pump topology for a gate drive high-side power supply. IEEE Trans Power Electr 20(2):300–307 8. Erickson RW, Maksimovic D (2001) Fundamentals of power electronics (2nd edn) Springer 9. Application Report (2013) Design guide for off-line fixed frequency DCM flyback converter. Infineon, Tech Rep 10. Ridley DR Designer series XII Flyback converters snubber design. Switching power magazine, Tech Rep 11. Alganidi A Electronic thesis and dissertation repository 5153, A comparison between different snubbers for flyback converters, Tech Rep 12. Markovi´c P, Lepojevi´c N, Popov N, Vukosavi´c S (2015) A compact isolated power supply for MV SiC MOSFET gate driver, 10 2015 13. Texas Instruments (2017) UCCx8C4x BiCMOS low-power current-mode PWM controller, Texas Insrtum Tech Rep 14. Application note AN4137, Design guidlines for off-line flyback converters using fairchild power switch (FPS). On Semiconductors, Tech. Rep 15. Adams J Application note AN-1024, flyback transformer design for the IRIS40xx series. International IOR rectifiers, Tech Rep 16. Zhang HJ Application note modeling and loop compensation design of switching mode power supplies. Linear Technologies, Tech Rep 17. Dinwoodie L Application report, UCC38C44 12-V isolated bias supply, Tech Rep

Design of Error Correction Engine Based on Flexible Unequal Error Control Code (FUEC) for Flash Memory Faults in Space Applications G. Amrutha Shree and Veena S. Chakravarthi

Abstract Due to vast integration density in CMOS technology, faults in the embedded or external memory have been increased. This manifests as single-cell upsets (SCU) and multiple cell upsets (MCU) for function, especially in flash memories. Flash memory provides far greater storage capacity at lower operating cost than SDRAM. Memories that operate in harsh environment like space can suffer from multiple errors. Due to the faults, data can be flipped from 1 to 0 or 0 to 1 or sometimes the message bits even get deleted. So, an embedded error correction code-based functional block is used along with dense memory, to ensure that the errors do not cause data corruption. This paper presents a method to protect memories from multiple cell upsets by adding redundancy. The error detection and correction can be done by using flexible unequal error control code (FUEC)-based design. The FUEC can detect and correct double, triple, and quadruple adjacent error. By using this method, low redundancy can be achieved in memory. The ECC engine was designed successfully, verified, and ready for integration to the memory. The design details are discussed below. Keywords Error correction codes (ECC) · Multiple cell upsets (MCU) · Redundancy · SCU · SEC · SEC–DED

1 Introduction The trend in the very-large-scale integration (VLSI) circuits has been increased because of low power consumption, high speed, and high package density. Embedded memory consumes a large portion in the system on Chip. The major reliability G. Amrutha Shree (B) BNM Institute of Technology, Bangalore, India e-mail: [email protected] V. S. Chakravarthi Sensesemi Technology, BNM Institute of Technology, Bangalore, India e-mail: [email protected]; [email protected] © Springer Nature Singapore Pte Ltd. 2020 S. Kalya et al. (eds.), Advances in Communication, Signal Processing, VLSI, and Embedded Systems, Lecture Notes in Electrical Engineering 614, https://doi.org/10.1007/978-981-15-0626-0_33

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issue for embedded memories is bit flipping, data retention, endurance, bad block handling, etc. As flash memories provide greater storage capacity they are used for space applications [1]. The flash memories guarantee nonvolatile storage and power loss. These memories can either be NAND flash memories or NOR flash memories [2]. The environment in the space is harsh because it contains harmful radiations so, the memories undergo single-cell upsets and multiple cell upsets [3]. The multiple bits in the memory get affected causing adjacent errors and burst errors. To protect standard memories, error correction codes (ECCs) have been employed. There are various techniques available to detect the errors; they are parity checking, cyclic redundancy check, longitudinal redundancy check, checksum, etc. Flexible unequal error control code is one such error correction code to make embedded memories in the system on chip more reliable. In this paper, the reliability block of flexible unequal error control code (FUEC) has been designed to detect and correct multiple bit errors and the design details are discussed in further sections. The research done in the field of reliable embedded memories and ECC is discussed and few lists of works are mentioned in Sect. 2. In Sect. 3, the specification, design methodology, design of reliability block, and verification of the design will be discussed. The specification tells the requirements that have to be met during the design of the reliability block. In Sect. 4, the results of the different reliable blocks to make embedded memory more reliable will be discussed. As well the power, area and delay of FUEC designs will be presented. In Sect. 5, the conclusion and future scope are provided.

2 Literature Survey By Tambatkar [4]. Fault detection and correction method for data stored in memory or buffer. The faults in 3D parity check matrix are corrected using this method. Hamming code is used in this method to detect and correct 3-bit errors of any combination. The arrangement of information bits is in the matrix format. For each row and column, parity bits are calculated. The faults in data and parity bits can be detected and corrected by this method. By Li [5]. To correct multiple bit errors in the memories, two methods have been designed. They are interleaving of adjacent codes and decoding using syndrome bits. The parity check bits obtained using the first method are more and reduce the complexity of decoding and delay. The parity bits obtained using the second method are less. Hence, the memory overhead is reduced. The result shows that the memory overhead is increased and the main goal is to reduce the memory overhead. By Santhia [6]. The survey of different fault correction codes has been done. The requirement of redundant bits is more and few designed codes do not provide protection level for large multiple cell upsets. They also fail to provide the reliability of embedded memory.

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By Revirigo [7]. The proposed method unequal error protection code is derived from single error correction-double error detection. In the presence of double faults, the proposed code can recover the set of critical bits. Signal processing and multimedia are some of the applications where the effect of error depends on the affected bit. The proposed method is extended single error correction–double error detection; the extended bits are used for additional faulty bits. By Jew [8]. Microcontroller applications use SRAM and flash as a basis of embedded memory subsystems. The factors which drive a complex mix of static RAM and flash memories requirements in microcontroller are power, safety, human interface, and security. Some of the aspects of the applications which drive how muchembedded SRAM and flash memory are required as well as how these memories are embedded in a microcontroller.

3 Flexible Unequal Error Control Code Methodology 3.1 Design Specification Table 1 shows the design specification needs to be kept while designing flexible unequal error control code. The 16-bit data is sent to encoder, 23-bit encoder data is obtained along with 7 redundant bits, and later 2-bit adjacent error is introduced and then sent to syndrome block obtaining 7 syndrome bits. After decoding, we obtain original data of 16 bit using FUEC–DAEC-based design. The 16-bit data is sent to encoder, 24-bit encoder data is obtained along with 8 redundant bits, and later 3-bit adjacent error is introduced and then sent to syndrome block obtaining 8 syndrome bits. After decoding, we obtain original data of 16 bit using FUEC–TAEC-based design. The 16-bit data is sent to encoder, 25-bit encoder data is obtained along with 9 redundant bits, and later 4-bit adjacent error is introduced and then sent to syndrome block obtaining 9 syndrome bits. After decoding, we obtain original data of 16 bit using FUEC–QAEC-based design. Table 1 Design specification

Parameter

DAEC

TAEC

QAEC

Data

16

16

16

Error injection

2

3

4

Encoded data

23

24

25

Redundant bits

7

8

9

Syndrome bits

7

8

9

Error correction

2

3

4

Error detection

3

4

5

16

16

16

Data out

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3.2 Methodology The reliability block of FUEC was designed with baseline hamming code to verify the results. The reliability block consists of encoder block, syndrome block, lookup table block, and decoder block. The reliability block of FUEC is able to detect and correct double adjacent error using DAEC design, triple adjacent error using TAEC design, and quadruple error using TAEC design. FUEC and hamming code-based design consist of encoder block, syndrome block, lookup table block, and decoder block. In the encoder block, the data is encoded and at the output of encoder, redundant bits are generated. The error is introduced to the encoded data. The corrupted encoded data is sent to syndrome design block and syndrome bits are generated. For particular syndrome, error positions are generated using lookup table. After decoding, original information bits are obtained.

3.3 Design of FUEC Methodology The SoC consists of many components to make embedded memory more reliable the reliability block of FUEC is used. The reliability FUEC block consists of encoder block, syndrome block, lookup table block, and decoder block. The block diagram of SoC with reliability block and embedded memory is shown in Fig. 1. In Fig. 1 for DAEC m = 23, n = 7; For TAEC, m = 24, n = 8; For QAEC, m = 25, n = 9. The encoded data from encoder is written into the memory. The designed reliability block helps protects the data. While reading the data from the memory if faults occur, the data is sent to the syndrome for fault detection. Later, decoding process gets the corrected data. The FUEC methodology was designed to correct multiple errors and burst errors. DAEC is one such methodology comes under FUEC. DAEC was designed to correct all double adjacent errors, single-bit errors, and detect 3-bit burst error anywhere in the input sequence. TAEC methodology also comes under FUEC. TAEC was designed to correct single-bit errors, two adjacent bit errors, 3-bit burst errors, three adjacent bit errors and detect 4-bit burst errors anywhere in the input sequence. QAEC was designed to correct single-bit errors, two adjacent bit errors, 3-bit burst errors, three adjacent bit errors, 4-bit burst errors, four adjacent bit errors, and detect 5-bit burst errors anywhere in the input sequence.

3.4 Verification The test bench of reliability block of DAEC, TAEC, and QAEC is shown in Fig. 2.

Design of Error Correction Engine Based …

Fig. 1 Block diagram of SOC with reliability block and embedded memory

Fig. 2 Test bench of reliability block of FUEC design

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DUT is initialized in test bench and test bench will contain clock generator, reset generator and enable logic generator, data generator, comparator and monitor, error injector, memory. The input and output data are compared and simulation results will be shown on monitor.

4 Verification and Synthesis 4.1 Simulation Results of Reliability Block of DAEC Design (a) Test Case 1: No Error Injection The above figure shows the simulation results of DAEC code. 16-bit data 16’h3991 is sent to the encoder. 23’h1cc8fd encoded data is obtained, with 7’b7d redundant bits. The data is read by syndrome block with syndrome of 7’h00. After decoding, the original data is obtained with 16’h3991. The count signal shows the number of errors corrected, as no errors were introduced count is 0. The match signal goes high if both input and output data bits are same. The simulation result is shown in Fig. 3. (b) Test Case 2: Introducing 2-Bit Error The above figure shows the simulation results of DAEC code. 16-bit data 16’h3991 is sent to the encoder. 23’h1cc8fd encoded data is obtained, with 7’b7d redundant bits. The 2-bit error is introduced. The data is read by syndrome block with syndrome of 7’h15. After decoding, the original data is obtained with data_out 16’h3991. The count signal shows the number of errors corrected, as errors were introduced count is 2. The match signal goes high if both input and output data bits are same. The simulation result is shown in Fig. 4.

Fig. 3 Simulation result of test case 1 of DAEC design

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425

Fig. 4 Simulation result of test case 2 of DAEC design

(c) Test Case 3: Introducing 3-Bit Error The above figure shows the simulation results of DAEC code. 16-bit data 16’h3991 is sent to the encoder. 23’h1cc8fd encoded data is obtained, with 7’b7d redundant bits. The 3-bit error is introduced. The data is read by syndrome block with syndrome of 7’h0d. The detectable errors may have same syndrome. The errors can only be detected and cannot be corrected. The simulation result is shown in Fig. 5.

Fig. 5 Simulation result of test case 3 of DAEC design

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4.2 Simulation Results of Reliability Block of TAEC Design (a) Test Case 1: No Error Injection The above figure shows the simulation results of TAEC code. 16-bit data 16’h8999 is sent to the encoder. 24’h899929 encoded data is obtained, with 8’b29 redundant bits. The data is read by syndrome block with syndrome of 8’h00. After decoding, the original data is obtained with 16’h8999. The count signal shows the number of errors corrected, as no errors were introduced count is 0. The match signal goes high if both input and output data bits are same. The simulation result is shown in Fig. 6. (b) Test Case 2: Introducing 3-Bit Error The above figure shows the simulation results of TAEC code. 16-bit data 16’h8999 is sent to the encoder. 24’h899929 encoded data is obtained, with 8’b29 redundant bits. The 3-bit error is introduced. The data is read by syndrome block with syndrome of 8’he7. After decoding, the original data is obtained with data_out 16’h8999. The count signal shows the number of errors corrected, as errors were introduced count is 3. The match signal goes high if both input and output data bits are same. The simulation result is shown in Fig. 7. (c) Test Case 3: Introducing 4-Bit Error The above figure shows the simulation results of TAEC code. 16-bit data 16’h8999 is sent to the encoder. 24’h899929 encoded data is obtained, with 8’b29 redundant bits. The 4-bit error is introduced. The data is read by syndrome block with syndrome of 8’hab. The detectable errors may have same syndrome. The errors can only be detected and cannot be corrected. The simulation result is shown in Fig. 8.

Fig. 6 Simulation result of test case 1 of TAEC design

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Fig. 7 Simulation result of test case 2 of TAEC design

Fig. 8 Simulation result of test case 3 of TAEC design

4.3 Simulation Results of Reliability Block of QAEC Design (a) Test Case 1: No Error Injection The above figure shows the simulation results of QAEC code. 16-bit data 16’h8999 is sent to the encoder. 25’h113334d encoded data is obtained, with 9’b14d redundant bits. The data is read by syndrome block with syndrome of 9’h000. After decoding the original data is obtained with 16’h8999. The count signal shows the number of

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Fig. 9 Simulation result of test case 1 of QAEC design

errors corrected, as no errors were introduced count is 0. The match signal goes high if both input and output data bits are same. The simulation result is shown in Fig. 9. (b) Test Case 2: Introducing 4-Bit Error The above figure shows the simulation results of QAEC code. 16-bit data 16’h8999 is sent to the encoder. 25’h113334d encoded data is obtained, with 9’b14d redundant bits. The 4-bit error is introduced. The data is read by syndrome block with syndrome of 9’h1de. After decoding the original data is obtained with data_out 16’h8999. The count signal shows the number of errors corrected, as errors were introduced count is 4. The match signal goes high if both input and output data bits are same. The simulation result is shown in Fig. 10. (c) Test Case 3: Introducing 5-Bit Error The above figure shows the simulation results of QAEC code. 16-bit data 16’h8999 is sent to the encoder. 25’h113334d encoded data is obtained, with 9’b14d redundant bits. The 5-bit error is introduced. The data is read by syndrome block with syndrome of 8’h16e. The detectable errors may have same syndrome. The errors can only be detected and cannot be corrected. The simulation result is shown in Fig. 11. As the redundant bit increases, area, power and delay of each code increases. Hamming code can correct single-bit errors whereas FUEC can correct multiple errors. The power consumption of memory has not considered in these results. The area, power and delay for different FUEC are shown in Table 2.

Design of Error Correction Engine Based …

Fig. 10 Simulation result of test case 2 of QAEC design

Fig. 11 Simulation result of test case 3 of QAEC design

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Table 2 Area, power, delay for different fuecs Design

Delay (ps)

Area (nm2 )

Power (nW)

Hamming code

329

1081

15,160

Double adjacent error control

409

1370

17,678

Triple adjacent error control

629

1390

17,456

1051

1259

14,526

Quadruple adjacent error control

5 Conclusion The reliability block using FUEC has been successfully designed and integrated with memory model. The reliability block of FUEC design is able to detect and correct double, triple and quadruple error in the embedded memory and successfully demonstrated by simulations. More the redundancy, more the errors can be detected and corrected. The embedded memories are made more reliable but integrating reliability block of FUEC design. As the redundant bits increases for FUEC design, the multiple errors and burst errors in the embedded memory will be detected and corrected. Acknowledgements I would like to thank ECE department, BNMIT for supporting in this work with lab facilities. I would like to thank Dr. Veena S. Chakravarthi for guiding me throughout the completion of this project.

References 1. Caramia M (2009) Flash memories in space applications: trenda and challange, researchgate.net publication, July 2009 2. Nakamura T, Deguchi Y, Takeuchi K (2017) AEP-LDPC ECC with error dispersion coding for burst error reduction of 2D and 3D NAND flash memories. 978-1-5090-3274-7/17/©2017 IEEE 3. Chen CL, Hsiao MY (1984) Error-correcting codes for semiconductor memory applications: a state-of-the-art review. IBM J Res Develop 58(2):124–134 4. Tambatkar S, Narayana Menon S, Sudarshan V, Vinodhini M, Murty NS (2017) Error detection and correction in semiconductor memories using 3D parity check code with hamming code, IEEE. 978-1-5090-3800-8/17/$31.00©2017 5. Li J, Xiao L (2018) Efficient implementations of 4-bit burst error correction for memories. 1549-7747 © 2018 IEEE 6. Santhia TE (2017) Error detection and correction using decimal matrix code: survey. In: 2017 International conference on electrical, instrumentation and communication engineering 7. Reviriego P, Liu S (2016) Unequal error correction codes derived from SEC-DAEC. Electron Lett 52(8):619–620 8. Jew T (2015) Embedded microcontroller memories: application memory usage. In: 2015 IEEE international memory workshop (IMW), Date of conference: 17–20 May 2015 9. Kurinec SK, Iniewski K Nanoscale semiconductor memories: technology and application. CRC Press, FL 10. Fujiwara E (2006) Code design for dependable systems: theory and practical applications. Wiley, NJ, p 11111

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11. Takenaka H, Okamoto E, Toyoshima M (2015) Low-density generator matrix code for correcting errors with a small optical transponder. In: 2015 IEEE 2015 IEEE International Conference on Space Optical Systems and Applications (ICSOS). 978-1-5090-0281-8/15© 12. Saiz-Adalid LJ et al (2013) Flexible unequal error control codes with selectable error detection and correction levels. In Proceedings of 32th International Conference Computer. Safety, Reliability Secure (SAFECOMP), Sep 2013, pp 178–189 13. Silva F et al (2017) Evaluation of multiple bit upset tolerant codes for NoCs buffering. In: Proceedings of IEEE 8th Latin American Symposium Circuits Systems (LASCAS), Feb 2017, pp 1–4 14. Gracia Moran J, “Improving error correction code for multiple cell upsets in space applications. This work was supported by the Spanish government under the research project TIN201681075-R, 1063-8210 © 2018 IEEE 15. Liu S, Reviriego P, Maestro JA (2012) Efficient majority logic fault detection with difference-set codes for memory applications. IEEE Trans Very Large-Scale Integr Syst (VLSI) 20(1):148– 156 16. Pedro Gi Vicente J (2014) Selectable error and correction level error control code area of interest: fault tolerant system, researchgate.net publication, July 2014 17. Gupta N (2016) Memory architecture design for nano satellites. 978-1-4673-7676-1/16 © 2016 IEEE

Analysis of Cryptographic Algorithms for Secured Data Transmission in VANETs Kalkundri Ravi, Rajashri Khanai and Kalkundri Praveen

Abstract The popularity of VANETSs is growing very rapidly. VANETs are part of mobile ad hoc networks and are dynamic in nature. VANETs provide vital information and a major revolution in automobile industry. As the VANETs nodes communication in open, the information is vulnerable for any type of attacks. Providing security is one of the upcoming issues in any type of open network. A proper security measures must be implemented for VANETs, as the nodes are dynamic in nature, and the nodes travel with varying speed. An appropriate cryptographic algorithm is to be selected for VANTE. In our work, we have tested the traditional RSA algorithm and a hybrid ECC-AES algorithm for different typed of data, such as text, image and text plus image, for various sizes of files in a Cryptool simulator. Further, we suggest the appropriate algorithms depending upon the results obtained. Keywords RSA · ECC · Hybrid · VANET

1 Introduction Vehicular ad hoc networks (VANETs) are a new form of networks and that are a special case of mobile ad hoc networks (MANET). Nodes in VANETs are cars or any intermediate nodes that establish a network. VANETs are self-established, selforganized networks and are dynamic in nature. Communicate takes place between K. Ravi (B) Department of Computer Science and Engineering, K.L.S’s Gogte Institute of Technology, Belagavi, Karnataka, India e-mail: [email protected] R. Khanai Department of Electronic and Communication, KLE Society’s College of Engineering & Technology, Belgaum, Karnataka, India e-mail: [email protected] K. Praveen Department of Electronic and Communication, K.L.S’s Gogte Institute of Technology, Belagavi, Karnataka, India e-mail: [email protected] © Springer Nature Singapore Pte Ltd. 2020 S. Kalya et al. (eds.), Advances in Communication, Signal Processing, VLSI, and Embedded Systems, Lecture Notes in Electrical Engineering 614, https://doi.org/10.1007/978-981-15-0626-0_34

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vehicle-to-vehicle (V2V) or between a vehicle-to-infrastructure (V2I). In V2V, two or more nodes may be involved in communication. VANET has features like the nodes are mobile in nature, nodes change their locations dynamically, so their topology changes dynamic, motion restriction in geographical structure and openness to power accessibility [1] (Fig. 1). The drivers experience in smart vehicles system can be made more efficient, if the vehicles exchange messages among themselves. The message must be exchanged in real time so that the driver can take instant and accurate decisions. The messages among the vehicles can be concern to the traffic congestion, or with some issues like accident, or landslide, or with the concern with the root, or various other messages. This increases the drivers, passengers or even the entire vehicles safety. Even though VANETs have various advantages, there are some issues that have to be taken care or at least try to reduce, that can cause various troubles to the VANET network. There are various security issues that have to be handled between the vehicles while information communication. Since the VANET network is open, and if security is not taken care, then any malicious node can affect the node or the entire network. The malicious node can also misdirect other vehicles, transmit false messages in the network, flood unwanted messages in the network, create traffic jams, create duplicate packets in the

Fig. 1 Example of VANET structure

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network, etc. [2, 3]. Further, the malicious node can also violate other security issues like privacy of the nodes, denial-of-service (DoS) attacks, cause wormhole attach, etc. Appling security to VANET is not easy and is more challenging, as the entire network is open. The nodes can join the network and leave at any time, further, the nodes are dynamic in nature, i.e., each node travel at their own speed and the nodes communicate at varying speed, hence applying security becomes more difficult to all nodes in the network [3]. With the various pros and cons of the VANET network, applying security to VANET is very important in the modern digital world. We need to find a suitable secure mechanism that is very much suitable to VANET that solves the different security issues in an efficient and effective way. The main advantage is that VANETs are part of MANETs, so the security techniques that are applicable to MANETs are also inherited to VANETs by default [2, 4]. But all the methods of MANETs will not be suitable as they are used for MANET, hence some modification or some new methods have to be found that is suitable to VANETs. The paper is organized as follows; we see the security issues in VANET in Sect. 2. In Sect. 3, we discuss the security scheme in VANET. Section 4 briefs the comparison of cryptographic algorithm. Further, we see the results in Sect. 5. We conclude in Sect. 6 with the help of some results.

2 Security Issues in Vanet Security is required in VANET’s for the following issues: A. Authentication: Authentication ensures the realness of the message, since the nodes in VANETs are in open, only the intended sender must send a message and only an intended receiver must receive the message. In some cases, only the sender’s ID may be confirmed by the receiver to know the property of the sender, like its location, speed, direction, etc. [4]. B. Integrity: Integrity implies the originality of the message; and that any unauthorized person or node does not tamper the message. It is easy to manipulate the message, as the nodes transmission of the message is open. The malicious node may modify the original message or simply add unwanted or false message to the receiver [4]. C. Confidentiality: Confidentiality refers to the data keeping safe. Confidentiality also refers to keeping the data safe from any type of attack or modification from any unauthorized users in the process of transmission. Once the message is encrypted that message is then sent to the receiver or to the next node. The receiver has to decrypt the message to get the original message. This process prevents the unauthorized nodes from accessing the content of the messages [4].

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D. Availability: It is the property by which the communication setup is made between the nodes for communication. Availability also deals with the resources to be utilized by the nodes. Many applications require faster responses from the sensors since delays make certain messages meaningless or result in devastating consequences [4, 5]. E. Non–Repudiation: It is the method by which the sender and receiver could map out the transaction of the message as if it was sent and received by the corresponding entities or nodes [4].

3 Security Schemes for Vanets VANET security is one of the upcoming research areas. Various security techniques can be used in VANETs. Below we list the basic security techniques that can be used or implemented for VANET: 1. Symmetric Key Cryptography: In this technique, algorithms use the same cryptographic keys for both encryptions of the message and decryption of cipher text. The keys may be identical or there may be a simple transformation to go between the two keys [2]. The keys, in practice, represent a shared secret between two or more parties that can be used to maintain a private information link. The major drawback is that both parties have access to the secret key, in comparison to public-key encryption [1]. 2. Public-Key Cryptography: PKC is a cryptographic system that uses pairs of keys, where the keys are generated by each node in the network. Encryption is done using the public keys, which may be broadcasted widely, and decryption takes place at the receiver side using the private keys, which is known only by the receiver. Generation of both the keys, i.e., the public and private keys depends on the cryptographic algorithms. In this scenario, a sender can encrypt a message using the receiver’s public key, and the encrypted message can only be decrypted with the receiver’s private key [5]. 3. Hybrid Cryptography: The Hybrid Cryptography can improve security. It is a combination of pubic key and private-key cryptographic method (hybrid) cryptographic algorithms. This method resolves the limitation of other cryptography algorithms. The major challenge is to have an efficient cryptographic algorithm which is faster and consumes less resources as well as it must provide strong security [1]. 4. Lightweight Technique: Based on asymmetric and symmetric cryptography, some lightweight protocols are designed to enhance future automotive security and meet the VANET security requirement [6].

Analysis of Cryptographic Algorithms … Table 1 Comparison of RSA/DSA and ECC algorithm [7]

Table 2 Comparison of RSA, ECDSA and NTRU algorithm [7]

437

Symmetric

RSA/DSA

ECC

Time to break in MIPS years

80

1024

160

1012

112

2048

224

1024

128

3072

256

1028

192

7680

348

1047

256

15,360

512

1066

Key and signature size:

Key generation time

PKCS

Key, sig size (bytes)

PKCS

In mili seconds (ms)

RSA

256 ECC

30,255

ECC NTRU

28 197

NRTU

1.5687

4 Comparision of Cryptographic Algorithm Many cryptographic algorithms provide security for different applications. RSA is one of the traditional cryptographic algorithms that is used in various applications in wide area. We compare few algorithms that can be suitable for VANET application. We choose RSA/DSA, NTRU and ECC cryptographic algorithms. Table 1 shows the comparison of RSA and ECC for key sizes and the time to break the algorithms. We can clearly see that ECC algorithm definitely used smaller key size compared to the symmetric algorithms or RSA/DSA algorithm. Even though the key size of ECC is smaller, it requires the same time to break as the RSA/DSA algorithm. Further, we compare the keys sizes or RSA, ECDSA and NTRU algorithms, shown in Table 2. Here also, we can see that ECDSA used a smaller key size, i.e., 28 bytes compared to the other two. We also compare the key generation time of ECC and NTRU, here, we can see that NTRU is faster in key generation, but has a big key size compared to ECC. Bigger key size means it consumes larger bandwidth in the network, which is not suitable for application like VANET. Thus, ECC is suitable for VANET.

5 Results We have compared various cryptographic algorithms, with various parameters. We have used the Cryptool simulator to compare RSA algorithm and a hybrid ECC-AES algorithm. The messages that are used are of the type like, text file, image file and text plus image file. We have tested the algorithms with various sizes of files. We have compared 15 different sizes of files, ranging from 54 to 603 Kb. We have compared

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Table 3 Comparison of text files S. No.

File size in Kb (text file)

Encryption (time in seconds)

Decryption (time in seconds)

RSA

ECC_AES

RSA

ECC_AES

1

54

0.031

0.843

0.486

0.014

2

102

0.063

1.422

0.891

0.031

3

108

0.078

1.422

0.952

0.031

4

136

0.094

1.796

1.188

0.016

5

161

0.11

2.17

1.406

0.031

6

203

0.141

2.686

1.766

0.032

7

264

0.172

3.547

2.327

0.047

8

303

0.219

4.016

2.656

0.046

9

351

0.234

4.78

3.079

0.046

10

401

0.281

5.407

3.531

0.047

11

442

0.297

6.331

3.859

0.079

12

476

0.312

6.375

4.141

0.063

13

500

0.328

6.639

4.389

0.063

14

561

0.375

7.796

4.889

0.078

15

603

0.39

8.407

5.28

0.078

same sizes of files of text, image and text plus image for RSA and ECC-AES. The main parameter is time. As shown in Table 3, here, we have compared the text files with both RSA and ECC-AES. As shown in Table 4, here, we have compared the image files with both RSA and ECC-AES. We can observe that from Tables 3 and 4, the decryption time of ECC-AES for image is less, but decryption time for test is more. This may be because the text files are word file. The word file takes more time for conversion than the simple JPEG image files. As shown in Table 5, here, we have compared the file that includes text and image files with both RSA and ECC-AES. As seen in all the tables, Tables 3, 4 and 5, and the graphs, Figs. 2, 4 and 6 shows, for encryption, RSA takes less time an average of 0.2025 s for three types of files, but where as ECC-AES takes more time for encryption, an average time of 4.2211 s for three types of files as shown in Figs. 3, 5 and 7. Similarly from Tables 3, 4 and 5 and the graphs, Figs. 3, 5 and 7, we can see that for decryption RSA takes more time than ECC-AES. RSA takes an average time of 2.66 s to decrypt three types of files, whereas ECC-AES takes 0.042 s to decrypt three types of files.

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Table 4 Comparison of image files S. No.

File size in Kb (image file)

Encryption (time in seconds)

Decryption (time in seconds)

RSA

ECC_AES

RSA

ECC_AES

1

54

0.031

0.734

0.391

0.031

2

102

0.063

1.375

0.797

0.032

3

108

0.063

1.468

0.875

0.032

4

136

0.094

1.875

1.125

0.032

5

161

0.094

2.202

1.328

0.032

6

203

0.125

2.718

1.855

0.031

7

264

0.193

3.625

2.399

0.031

8

303

0.204

4

2.561

0.031

9

351

0.219

4.796

2.968

0.031

10

401

0.266

5.516

3.406

0.031

11

442

0.281

5.828

3.75

0.032

12

476

0.297

6.312

4.03

0.047

13

500

0.312

6.671

4.234

0.047

14

561

0.359

7.844

4.766

0.047

15

603

0.391

8.375

5.139

0.047

Table 5 Comparison of text and image files S. No.

File size in Kb (text + image file)

Encryption (time in seconds)

Decryption (time in seconds)

RSA

ECC_AES

RSA

1

54

0.031

1.435

0.422

ECC_AES 0.016

2

102

0.062

1.375

0.843

0.016

3

108

0.063

1.469

0.89

0.014

4

136

0.094

1.828

1.125

0.016

5

161

0.093

2.172

1.344

0.17

6

203

0.141

2.718

1.703

0.16

7

264

0.172

3.468

2.234

0.031

8

303

0.203

4.016

2.577

0.014

9

351

0.234

4.594

2.984

0.014

10

401

0.25

5.296

3.422

0.031

11

442

0.281

5.734

3.766

0.032

12

476

0.313

6.391

4.062

0.031

13

500

0.328

6.687

4.234

0.031

14

561

0.359

7.609

4.812

0.047

15

603

0.375

8.186

5.219

0.047

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Fig. 2 Encryption of text files

Fig. 3 Decryption of text files

Though ECC takes more time for encryption, the encryption takes place at the sender side, which does not affect the network in communication. The main advantage of using ECC is that it uses smaller key size without using its security level. Thus, ECC is very much suitable for VANET, as it consumed less bandwidth, space and computation time.

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Fig. 4 Encryption of image files

Fig. 5 Decryption of image files

6 Conclusion and Future Scope VANET security is one of the major concerns for the automobile industry and the researchers. Since the communication is vulnerable for any type of attacks, providing security to VANET is necessary. As we have seen the advantage of ECC aver RSA/DSA and NTRU, and the results obtained by Cryptool simulator, we can conclude that ECC is suitable for VANET structure. ECC uses less key size with the same amount of security level compared to RSA/DSA and NTRU.

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Fig. 6 Encryption of text + image files

Fig. 7 Decryption of text + image files

In the future, we intend to use ECC with various algorithms like ECDSA and ECDH for VANET. We also intend to implement ECC on VANETs with the help of a microcontroller and implement a WSN scenario in VANETs.

References 1. Ahmed W, Elhadef M (2018) Securing intelligent vehicular Ad hoc networks: a survey. In: Park JJ et al (eds) Advances in computer science and ubiquitous computing, lecture notes in electrical engineering, 474. Springer Nature Singapore Pte Ltd, College of Engineering, Abu Dhabi University, UAE. https://doi.org/10.1007/978-981-10-7605-3_2

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2. Kaur R, Pal Singh T, Khajuria V (2018) Security issues in vehicular Ad-hoc network (VANET). In: Proceedings of the 2nd international conference on trends in electronics and informatics (ICOEI 2018) IEEE conference record: #42666; IEEE Xplore. Department of Computer Science and Engineering, Chandigarh University, Mohali. ISBN: 978-1-5386-3570-4 3. Greeshma TP, Roshini TV (2018) A review on privacy preserving authentication in VANETs. In: IEEE-International conference on control, power, communication and computing technologies (ICCPCCT). Department of Electronics and Communication, Vimal Jyothi Engineering College, Kannur, 1-5386-0796-1/18/$31.00 ©2018 IEEE 4. Mathew N, Uma V (2018) VANET security-analysis and survey. In: IEEE-International conference on control, power, communication and computing technologies (ICCPCCT). Department of Computer Science, School of Engineering and Technology, Pondicherry University, India, 1-5386-0796-1/18/$31.00 ©2018 IEEE 5. Kulkarni P, Khanai R (2016) Security frameworks for mobile cloud computing: a survey. In: International conference on electrical, electronics, and optimization techniques (ICEEOT)— 2016. 978-1-4673-9939-5/16/$31.00 ©2016 IEEE 6. Jadoon AK, Wang L, Li T, Zia MA (2018) Lightweight cryptographic techniques for automotive cybersecurity. Hindawi Wireless Commun Mobile Comput 1640167:15. https://doi.org/10.1155/ 2018/1640167 7. Ravi K, Kulkarni SA (2013) A secure message authentication scheme for VANET using ECDSA. In: 4th ICCCNT—2013. Department of Computer Science, K.L.S. Gogte Institute of Technology, Belgaum, India, July 4–6, 2013

Classification of Landsat 8 Imagery Using Kohonen’s Self Organizing Maps and Learning Vector Quantization B. R. Shivakumar and S. V. Rajashekararadhya

Abstract Image classification is the most commonly employed technique for extricating land cover report from remotely sensed images. In the last two decades, advanced image classifiers have been extensively applied in remotely sensed (RS) image classification studies. Kohonen’s Self Organizing Maps (SOM) and its supervised version Learning Vector Quantization (LVQ) algorithms have been applied in a variety of machine learning and pattern recognition studies as they are derived from neural networks. In this paper, the classification ability of SOM, LVQ-1 and LVQ-2 techniques are investigated using medium resolution Landsat 8 OLI/TIRS RS imagery. The study presents a detailed analysis of SOM and LVQ algorithms in RS data classification based on the LULC separability. The study uses Divergence (Div) and Transformed Divergence (TD) as metrics for measuring LULC separability. Results of SOM and LVQs were compared with conventional maximum likelihood and minimum-distance- to-means classifiers. Supervised Kohonen’s LVQ algorithms produced better accuracies than conventional classifiers. Also, LVQ algorithms showed great efficiency in avoiding overfitting of the dominant classes and separating spectrally overlapping classes. The study is indication of the applicability of Kohonen’s algorithms for RS data classification. Keywords Self-organizing maps · Learning vector quantization · Classification · Land-use/land-cover · Remote sensing

B. R. Shivakumar (B) Department of E&C Engineering, N.M.A.M. Institute of Technology, Nitte, Karkala, India e-mail: [email protected] S. V. Rajashekararadhya Department of E&C Engineering, Kalpataru Institute of Technology, Tiptur, India e-mail: [email protected] © Springer Nature Singapore Pte Ltd. 2020 S. Kalya et al. (eds.), Advances in Communication, Signal Processing, VLSI, and Embedded Systems, Lecture Notes in Electrical Engineering 614, https://doi.org/10.1007/978-981-15-0626-0_35

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1 Introduction The process of remotely sensed (RS) image classification can be broken down as follows. The sensor placed on the satellite on a geostationary or sun synchronous orbit collects the data and transfers it to the base station. The data collection is not necessarily errorless due to factors such as the curvature of the earth surface, sensor calibration, and atmospheric conditions and hence requires proper corrections. The raw data is thus pre-processed to make it free from errors such as geometric and radiometric errors. This is followed by the feature selection and extraction steps in which the information of interest is extracted from the data for further processing. The remotely sensed data can be enormous in content, and hence there is a need for data dimensionality reduction which can be treated as a type of compression. Next step is the classification. RS image classification is broadly categorized based on the requirement of the training phase as supervised and unsupervised classification techniques. In supervised classification, an analyst provides appropriate training data to the machine running the classification algorithm. This can be thought of as some kind of supervision and hence the name. The analyst feeds the machine with sample values of the regions of interest and the machine then performs classification of the input imagery based on the training samples provided to it. Since RS imagery spans large areas, it is often difficult to identify and collect reliable training information due to factors such as the cost of field studies, the time consumed, limited training locations, and various other logistical constraints [1, 2]. In such scenarios, unsupervised image classification methods are employed. In unsupervised classification, the machine running the classification algorithm performs segmentation of the input imagery, without any kind of training data, by grouping pixels of similar type based on the algorithm used. Neural networks have found themselves in the centre of RS classification approaches in the last two decades. A neural network can be defined as a set of connected nodes, in which each node acts as a processing unit. Each processing unit executes a fixed function on its input to produce a single node output [3, 4]. Two important properties of neural networks are the ability to learn from the input data and ability to generalize and predict new patterns [5]. Added with their inherent nonparametric characteristics makes them applicable to a large variety of RS imagery. The nodes are connected to each other by connections, usually weighted, and can be modified during the training process. The overall learning of an ANN is based on the modification of weights [6]. One of the biggest advantages of neural networks in RS applications is its ability to work with non-parametric data sets. Hence, neural networks are applicable to a wide variety of datasets [2, 7]. A self-organizing map (SOM), also called a Kohonen network, is a singlelayered fully connected linear network, whose output is a two-dimensional, organized arrangement of nodes. The basic idea behind SOM is the soft competition between the output layer nodes, i.e., the algorithm not only updates the winner node but also its neighbours, thereby creating a topographically ordered mapping between the input data elements and the output nodes [3, 8, 9]. Creating topology preserving

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maps while maintaining the neighbourhood relations of the input pattern is a characteristic feature of SOM [6, 10, 11]. Another important characteristic of SOM is the ability to simultaneously perform feature extraction and classification [12, 13]. Self-organizing networks can learn and detect regularities and correlations in the inputs and can predict responses [3, 9]. The neurons in a SOM study the input data to identify analogous input vectors such that neurons that are physically in close proximity act in response to comparable input vectors. This makes SOM a valid candidate for the remotely sensed data classification. One of the important applications of SOM is based on exploratory data analysis. They have a characteristic of reducing the higher dimensional input space into 1 or 2- dimensional output grid [14]. A similar approximation can also be obtained by U-matrix technique [15]. Another important characteristic of SOM is the ability to train with data from multiple sources. This characteristic is made use by several authors to combine satellite data information with other ancillary data [16], radar data [17], data collected from meteorological stations [18], and airborne lasers [19]. Advantages of SOM are [3, 5, 14, 20]; (i) cluster centres are found by iterative training, (ii) easy to implement and interpret, (iii) has the capability to map complex and large input data distributions, and (iv) produces a good generalization for input vectors which are not in the training data. The basic unsupervised SOM has been used in many RS studies. Some of the note worth studies in this regard are clustering and classification [21–23], identifying ocean current patterns [24, 25], detecting borders [26], identifying wind patterns and sea surface temperature patterns [24, 27, 28], cloud identification [29], rainfall [18, 30], forest and land cover mapping [31], river flow forecasting [32], mineral identification [33], and analyzing the land cover post natural hazards such as tsunami [34]. SOM has also been widely suggested and used in a variety of applications as an alternative to k-means clustering [5]. There exist multiple variants of the SOM algorithm. In general, SOM and most of its variants are basically employed on vector data [14]. Variants of SOM that can work on non-vector data were also developed [35]. Hierarchical SOMs combine multiple SOMs to process the data at a lower level and use their outputs as inputs to a higher-level SOM that later fuses the results [36, 37]. A variant of SOM called GeoSOM, applicable for geographical information system problems has also been developed [38]. A complete review of every SOM variant is beyond the scope of this paper. Detailed information on these variants can be found in [38, 39]. The supervised version of SOM is named Learning Vector Quantization (LVQ) and was developed by Kohonen [6]. It is based on the winner-takes-all approach and is a precursor to SOM. The winner-takes-all approach calculates a winner node, for each data point, that is closest to the input according to a given distance measure. The winner node’s position is then adapted as per the classification result. The winner node, for correct classification, is moved closer to the data point and vice versa. One of the advantages of winner nodes is that they are easy to interpret in application domains [40]. Similar to unsupervised SOM, LVQ can be used in multiclass classification problems [41–43]. In the study presented by Ji [44], LVQ performed better than conventional Maximum Likelihood Classifier (MLC). Similar to SOM, a variety of

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LVQ variants were presented by researchers. Some important variants of LVQ are Generalized Relevance LVQ (GRLVQ) [23], GRLVQ improved (GRLVQI) [45], Fuzzy LVQ [46], and Gaussian LVQ [47]. The rest of the paper is organized as follows: Sect. 2 provides a brief introduction to the study area and data type used. Section 3 provides the mathematical background on SOM, LVQ1, and LVQ2 algorithms. Section 4 discusses the methodology implemented. Section 5 presents and discusses the results obtained during the course of the study. Lastly, Sect. 6 presents the conclusions drawn from the results obtained.

2 Data and Study Area Landsat 8 OLI/TIRS data of Kumta taluk in North Canara district, India was acquired from Earthexplorer Website [48]. The Landsat 8 OLI/TIRS data consists of 11 spectral bands. A detailed description of the Landsat 8 OLI/TIRS sensor bands can be found in [49]. This study used the first 8 bands from OLI sensor data. The first 7 bands are of 30 m spatial resolution at the nadir. These bands are used to create a composite multispectral image using the process of layer stacking. Band 8 is the panchromatic band with a spatial resolution of 15 m at nadir and is used to enhance the spatial resolution of the layer-stacked image. This process is termed resolution merging. The outcome of resolution merge is a 15 m multispectral imagery. The data is subjected to multiple standard pre-processing steps by the provider itself using processing software LPGS v2.6.2. The map of the study area is shown in Fig. 1. By conducting a detailed inspection of the study area, seven Anderson’s [50] level1 and level-2 land cover classes were identified in the study area. Level-1 classes are Water Body (WB), Evergreen Forests (EGF), Scrub Land (SL), Kharif (KH), and Built Up (BU). Level-2 classes are Deciduous Forests (DF) and Double Crop (DC). By principle, level-2 classes are derivatives of level-1 classes [50]. 50–60% of the study area is covered by lush Evergreen Forests, which are a part of the Western Ghats. Aghanashini River and its estuary form the major source of Water Body in the area. Some regions around the banks of the river and its estuary are used for cultivation (Kharif). The city of Kumta forms the major settlement in the region (Built Up). Due to sufficient rainfall in the inland regions, vegetation is the major land cover type. Class separability was measured for each class pair in terms of Divergence (Div) and Transformed Divergence (TD). These values are shown in Table 1. A TD value of 2000 indicates an excellent separability between the class pairs in signal space. Any value less than 2000 indicates an overlapping between the class pairs in signal space. Higher the proportion of overlapping, lower will be TD value. A similar approximation is also applicable to divergence measure, although, no upper bound exists. By careful observation of the class separability values, the following class pairs were identified to be severely overlapping each other; EGF-DC, SL-KH, SLDF, SL-BU, and KH-BU.

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Fig. 1 Map of the study area

Table 1 LULC class separability in terms of divergence and transformed divergence Class pair

TD

DIV

Class pair

TD

DIV

Class pair

TD

DIV

WBEGF

2000

422.96

EGF-SL

2000

218.55

DC-BU

2000

988.81

WB-DC

2000

758.91

EGF-KH

2000

869.91

SL-KH

1998.97

60.60

WB-SL

2000

237.52

EGF-DF

2000

111.10

SL-DF

1999.99

100.00

WB-KH

2000

370.41

EGF-BU

2000

955.05

SL-BU

1999.96

WB-DF

2000

200.19

DC-SL

2000

267.23

KH-DF

2000

WB-BU

2000

210.26

DC-KH

2000

850.66

KH-BU

1996.31

EGF-DC

1917.48

25.50

DC-DF

2000

253.21

DF-BU

2000

87.45 217.09 50.35 306.66

3 Mathematical Background In this section, a brief mathematical background on SOM and LVQ techniques is discussed.

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3.1 Self Organizing Maps SOM can be regarded as a mapping from an input data space R n onto a twodimensional map grid. Thus, each SOM network consists mainly of two layers: the input layer and the output layer. The input layer constitutes of data vectors while output layer is characterized by reference vectors. Each node i in the map grid is represented by a parametric reference vector m i ∈ R n . The map grid can be projected onto a rectangular or a hexagonal lattice. Each node or reference vector in the output map grid is connected to the adjacent ones by the neighbourhood function characterized by the topological structure of the map grid as in Fig. 2 [12]. During the operation, each input vector x is compared with every reference vector mi and is mapped to the reference vector to which it matches the best. This creates a nonlinear projection effect causing the reduction of dimensionality of the input data to that of the two-dimensional map grid. The learning by the Kohonen network is by the use of successive approximation technique. During learning, initially, the selection of cluster centres is random. The algorithm then iteratively learns from the process and progressively finalizes on the best cluster centres. The most commonly used metric for mapping an input vector onto the two-dimensional map grid of reference vectors is the Euclidean distance. The winning node or the best matching unit (BMU) is identified as [3, 51]; ||x − m c || = min{||x − m i ||}

(1)

c = argmin{||x − m i ||}

(2)

t

or

t

and x is mapped onto c relative to the parameter values mi [3, 51]. The input vector x is mapped to the reference vector mc if it produces the smallest Euclidean distance relative to all other reference vectors. Every time an input vector

Fig. 2 SOM architecture (PE: Processing elements or nodes in the map grid) [9]

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is mapped to a reference vector, the nodes spatially close to the winning node will learn and update themselves according to the input node as [3, 51]; m i (t + 1) = m i (t)+ ∝i (t)h c,i (t)[x(t) − m i (t)]

(3)

where t is the discrete-time coordinate, h c,i is the kernel function defining the neighbourhood around mc at time t, and ∝i (t) is the learning rate parameter and is a function of time [3, 20]. ∝i (t) can take on values in the range [0, 1] and is determined as [20]; ∝i = ∝0 ei

(4)

where t and i represent the iteration rate and number, respectively. The value of h c,i (t) defines the way in which the input data vectors can be fitted to the nodes in the map grid and is defined as [12, 51]; h c,i (t) = h(||rc − ri ||, t)

(5)

where rc , ri  R are the location vectors of nodes c and i, respectively, in the map grid. As the Euclidean distance between r c and r i increases indicating they are moving away from each other, the neighbourhood function value gradually decreases to zero. This effect creates a local relaxation or smoothing effect of the reference vectors in the output map grid within the neighbourhood of the BMU [12, 51]. This causes the grouping of the similar input vectors associated with a single reference vector at the end of the learning phase. The two most commonly used neighbourhood functions are the Gaussian and bubble functions. In both cases, the neighbourhood radius, r, decreases to 0 or 1. When r tends towards zero, the topographical ordering may be lost but the final quantization error will be minimal. On the other hand, when r tends towards 1, the final quantization error will not be minimized, but the topographical ordering will be maintained. However, this also causes the border effect, where vectors near the border will be pushed towards the centre, causing high quantization errors [14, 51]. The basic algorithm for training the network is then [8, 14]: For each input vector x: (a) Calculate the Euclidean distances between the vector x and all reference vectors, mi in the output map grid. (b) Select the nearest reference vector as best matching unit (BMU). (c) Update each node in the output map grid according to Eq. (3). (d) Repeat the process until convergence.

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3.2 Learning Vector Quantization (LVQ) Algorithm As the name itself implies, LVQs belong to the set of algorithms that involve a learning process based on the training set. The objective of the learning or training phase is to calculate the optimal values of network weights so as to achieve the highest classification accuracy [52]. The learning phase is iterative in nature and learning parameters, and network weights change at every new training data provided to the algorithm. Depending on the learning algorithm, the values of one or more weights will vary for every new training data. After every successful classification, the winning nodes are moved towards x(t) and vice versa. The update equations for LVQ are very similar to that of SOM and are given by [40]; m i (t + 1) = m i (t) + m i (t + 1) m i (t + 1) = m i (t) +

∝ f ({m i (t)(t)}x(t)yi (t))(x(t) − m i (t)). n

(6) (7)

The function f () is algorithm dependent and yi (t) are the target vectors. Further, the choice of initial weights plays a vital role in efficiency and time consumed for training [52].

3.3 LVQ1 Algorithm Kohonen provided the first variant of LVQ algorithm and is named as LVQ1. In LVQ1 technique, the reference vector with minimal distance to the training pattern is updated. Depending on the classification result, the winning node is moved towards the training sample for successful classification, and vice versa. The training phase of the LVQ1 involves the following steps [52]; i. Randomly select a training sample; ii. Find the winning node m i (t) using the equation;

d{m i (t) − x(t)} = min d{m i (t) − x(t)} t

(8)

iii. Update m i (t) using the equations [52];  m i (t) =

m i (t)+ ∝ (x(t) − m i (t)) if c(m i (t)) = yi (t) m i (t)− ∝ (x(t) − m i (t)) if c(m i (t)) = yi (t)

(9)

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3.4 LVQ2 Algorithm The idea behind LVQ2 is to better separate reference vectors in vector space. For a training sample (xi (t); yi (t)), the  two nearest reference vectors m i (t) and m j (t) are updated, if c(m i (t)) = c m j (t) and c(m i (t)) = yi (t). Further, the training sample should fall in the window given by [52], 

d(x(t), m i (t)) d(x(t), m i (t)) ,   min  d x(t), m j (t) d x(t), m j (t)

 >s

(10)

. where s = 1−ω 1+ω The parameter ω characterizes the width of the window and determines the active region of the algorithm [52, 53]. The update equations for LVQ2 algorithm are [52];  m i (t) =

m i (t)+ ∝ (x(t) − m i (t)) if c(m i (t)) = yi (t) m i (t)− ∝ (x(t) − m i (t)) if c(m i (t)) = yi (t)

(11)

4 Methodology Image classification was performed using IDRISI Selva v17.0 GIS/RS software package. The software package embeds the SOM module which is based on the technique originally proposed by Kohonen. The software package provides a platform for classifying RS imagery using Kohonen’s SOM (unsupervised classification) as well as Kohonen’s LVQ (supervised classification). The package also provides an option to perform k-means clustering within the unsupervised package.

4.1 SOM Classifier The Landsat 8 imagery is pre-processed as indicated in Sect. 2 and prepared for classification. A composite RS image is created using the first 8 bands of the data. The spatial resolution of the composite image is 15 m. The sampling intervals are selected as 3 for column and 7 for rows. No training data is required for unsupervised SOM and hence are not relevant here. The network parameters are selected as the number of input layer neurons is 7, the number of output layer neurons is 3 × 3 = 9, initial neighbourhood radius is 5.24, the minimum learning rate is 0.5, and maximum learning rate is 1. The number of output clusters was restricted to 9 for easier post-processing of the clustered image. Fuzzy concepts were not employed and hence the algorithm produces an output hard classified map.

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4.2 LVQ Classifiers LVQ is a supervised classification technique and requires correct training data for efficient classification results. The GIS package used provides an option to collect training data (endmembers) by drawing polygon structures on the input imagery and then labelling them. By rigorously studying the data and taking Wikimapia maps [54], previous studies [55, 56], and government census documents [57] as reference, seven land use land cover classes were identified on the study area. For each identified class, multiple endmembers are collected to create a signature set. IDRISI toolbox provides an option to create a signature file either as an image or a vector file. The sampling and network parameter values are kept to the same values as specified for SOM. i. Course Tuning The toolbox begins training with the coarse tuning of the network parameters. The process is regressive and the algorithm trains using the given training data until it converges. Convergence is achieved when either the maximum learning rate is achieved, or learning radius reaches the minimum value, or no gain is observed between consecutive iterations. It was observed that radius decreased as the number of iterations increased indicating that the algorithm is moving towards convergence. The number of iterations itself is proportional to the training set size. Larger the training set size, larger will be the number of iterations required to coarse tune the algorithm. During this study, the coarse tuning operation returned the following parameters for running statistics; learning rate = 0.5, radius = 1.00, quantization error = 0.0094, and number of iterations = 276,000. ii. Fine Tuning Fine tuning immediately follows course tuning and is optional (although recommended). During fine tuning, the parameters and their values are selected as minimum gain term = 0.0001, maximum gain term = 0.0005, the fine-tuning rule is LVQ1 or LVQ2, and fine-tuning epochs = 50. These parameters can be varied as per the analyst’s requirement. Fine-tuning operation returned the following parameters for running statistics; learning rate = 0.5, radius = 1.00, gain term = 0.0003, and number of iterations = 50. Weights of the network after tuning are saved for classification. iii. Classification The classification was performed using the weights generated during the training phase. The output of the classification phase is a map grid indicating LULC classes as per the training set. If a pixel is not classified to any predefined LULC class by LVQ, the IDRISI package provides three options. The analyst can further classify them by using minimum mean distance or minimum distance algorithms. If the analyst does not wish to use them, then a third option lets the analyst to leave the pixels unclassified. This study classifies the study area using both LVQ1 and LVQ2

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algorithms. Also, the minimum distance algorithm is used for classifying pixels not identified by LVQ1 and LVQ2. iv. Accuracy Assessment The results of hard classification are a two-dimensional map structure and do not provide quantified results. The process of accuracy assessment enables quantization of the classification results. A total of 1000 pixels were selected using stratified random strategy for performing accuracy assessment. All classified images are assessed for their accuracy using the same set of pixels. This provides a common platform for analyzing the results. A detailed explanation on accuracy assessment is beyond the scope of this paper. We suggest books by Jenson [7] and Richards [58] for detailed information on accuracy assessment. The classification results were analyzed using standard accuracy assessment metrics; User’s Accuracy (UA), Producer’s Accuracy (PA), Kappa Statistic (khat ), and Overall Classification Accuracy (OCA).

5 Results and Discussions SOM created 9 clusters by means of unsupervised classification approach. Since only seven LULC classes were identified during training, a recoding process was conducted to bring the number of output classes to predefined value. This was carried out using Fuzzy Recode package in ERDAS IMAGINE v14® GIS toolbox. However, some of the classes in the SOM-classified image were highly similar, and as a result, all classes were not identified after recoding. The classes that were not identified after recoding are Double Crop and Deciduous Forest classes. It should be noted that, both these classes are Anderson’s level-2 LULC classes. The main reason behind the package failing to identify Double Crop class was its spectral similarity to Evergreen Forest. Double Crop is the less dominant class of the EGF-DC spectral class pair. The spectral distance in terms of Divergence between EGF and DC is 25.50, which is the lowest of all the class pairs. The absence of Deciduous Forest at the output of recoding is believed to be mainly because of less number of training pixels. Deciduous Forest class was the smallest land cover class in the study area and only very limited number of training pixels were collected. During recoding, the regions of Deciduous Forest were identified as Scrub Land. To bring a fine balance to the classification accuracy and number of unclassified pixels, both Double Crop and Deciduous Forest classes were treated as background data during recoding. Out of 1000 pixels selected for accuracy assessment, 118 pixels were not assigned to any of the five recoded classes. This caused the classification performance to degrade severely. The overall classification accuracy and Kappa statistic of SOM classification are 69.10% and 0.5088, respectively. The results of SOM classification are shown in Table 2. Although SOM classifier failed to identify less dominant classes (Anderson’s level-2 classes) of the spectral class pairs, its ability in extracting dominant classes (Anderson’s level-1 classes) cannot be undermined. Evergreen Forest was extracted with best users accuracy value of 89.66%. This is better than the supervised LVQ1

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Table 2 Accuracy assessment results of the SOM classifier Class name

Reference totals

Classified totals

Number correct

Background

118

0

0

Water body

79

245

78

Evergreen F

600

551

494

Scrub land

112

160

Kharif

76

40

Built up

15

4

Producers accuracy (%)

Users accuracy (%)

Kappa

00.00

00.00

0.0000

98.73

31.84

0.2599

82.33

89.66

0.7414

80

71.43

50.00

0.4369

35

46.05

87.50

0.8647

4

26.67

100.00

1.0000

Overall classification accuracy = 69.10% Overall Kappa statistic = 0.5088

and LVQ2 techniques. Kharif and Built Up classes were also extracted with excellent User’s Accuracies. However, SOMs inability to extract the most spectrally separable class, Water Body, requires further investigation. LVQ1, being a supervised classifier, identified all seven LULC classes on the study area. LVQ1 extracted the Water Body class with the best accuracy. The highest accuracy value is credited to the nature of the LULC class, i.e., its separability. Out of 83 pixels classified as Water Body, 75 pixels were correctly classified creating the best User’s Accuracy (UA) value of 90.36%. Also, LVQ1 did not create many misclassifications for Water Body. It was the class with least number of misclassifications. The efficiency of LVQ1 in LULC mapping studies can be emphasized by the way it separated EGF-DC spectral class pair. LVQ1 separated EGF (UA = 82.32%) and DC (UA = 80.00%) class-pair excellently despite them having least spectral separation. LVQ1 also separated KH (UA = 78.13%) and BU (UA = 83.33%) class pairs very efficiently. LVQ1 extracted Scrub Land class with medium efficiency. The decline in Scrub Land class accuracy is due to its spectral overlapping with Kharif and Built Up classes. It should be noted that, no class was badly extracted (UA ≤ 40%) by the classifier amidst some class pairs having severe class overlapping as indicated by Table 1. The overall classification accuracy and Kappa statistic of LVQ1 classifier are 79.40% and 0.6254, respectively. LVQ2 classification results were very similar to LVQ1 classification results except for the case of Double Crop class. LVQ2 produced an User Accuracy value of 66.67% for Double Crop class as compared to 80.00% by LVQ1 classifier. This is credited to the way in which LVQ2 updates its reference vectors as compared to LVQ1. Among other classes, Water Body and Evergreen Forest classes were extracted with similar efficiency values as that of LVQ1 classifier. A small decrease in User’s Accuracy value was observed for Scrub Land class. Kharif, Deciduous Forest, and Built Up classes were extracted with slightly better accuracies as compared to LVQ1. The overall classification accuracy and Kappa statistic for LVQ2 are 79.00% and 0.6181, respectively. Table 3 indicates the accuracy assessment results for LVQ1 and LVQ2 classification techniques.

94.94

97.00

04.49

63.39

65.79

24.14

33.33

Evergreen forest

Double crop

Scrub land

Kharif

Deciduous forest

Built up

83.33

50.00

78.13

58.68

80.00

82.32

90.36

0.8308

0.4851

0.7663

0.5347

0.7805

0.5580

0.8953

40.00

27.59

60.53

64.29

02.25

96.83

94.94

LVQ2 PA (%)

Kappa

PA (%)

UA (%)

LVQ1

Water body

Class name

85.71

53.33

76.67

57.60

66.67

82.18

90.36

UA (%)

0.8550

0.5194

0.7475

0.5225

0.6341

0.5545

0.8953

Kappa

Table 3 Accuracy assessment results of individual classes of all supervised classifiers MLC

66.67

65.52

63.16

55.36

38.20

90.50

82.28

PA (%)

22.22

26.03

84.21

50.00

80.95

91.57

98.48

UA (%)

0.2104

0.2382

0.8291

0.4369

0.7909

0.7892

0.9835

Kappa

MD

20.00

79.31

48.68

72.32

10.11

85.33

84.81

PA (%)

33.33

27.38

78.72

50.00

21.95

86.93

98.53

UA (%)

0.3232

0.2521

0.7697

0.4369

0.1433

0.6732

0.9840

Kappa

Classification of Landsat 8 Imagery … 457

458 Table 4 Overall classification results of classifiers tested

B. R. Shivakumar and S. V. Rajashekararadhya Classifier

Overall classification accuracy (%)

Overall Kappa statistic

SOM

69.10

0.5088

LVQ1

79.40

0.6254

LVQ2

79.00

0.6181

MLC

78.10

0.6435

MD

73.20

0.5630

To analyse the capability of SOM in RS image classification, the results of LVQ1 and LVQ2 were compared with traditional maximum likelihood (MLC) and minimum-distance-to-means (MD) classifiers. The accuracy assessment results for maximum likelihood and minimum-distance-to-means classifier are also indicated in Table 3. Both these classifiers are supervised techniques and identified all seven predefined LULC classes during classification. Same training data set was used for both MLC and MD to create equal platform for result comparison. The overall classification results of all supervised classifiers are shown in Table 4. It is observed that, although SOM failed to identify two LULC classes during classification, its classification accuracy is comparable to that of minimum-distance-to-means classifier. In some of our own previous studies [59], minimum-distance-to-means classifier has produced results comparable and sometimes better than computationally efficient MLC. Hence, the results of SOM could not be phrased unsatisfactory. On the other hand, supervised LVQ1 and LVQ2 results were superior to both MLC and minimum-distance-to-means classifiers in terms of overall classification accuracy. Similar results were obtained by [44]. However, Kappa statistic for MLC was superior to both LVQ1 and LVQ2 indicating its classified map, in an average sense, is more similar to the input image. Comparing the results of LVQ1 and LVQ2 with maximum likelihood classifier and minimum distance-to-means classifiers, following observations were made; a. MLC and MD extracted spectrally independent classes, in this case Water Body, more efficiently than LVQ techniques. b. Both MLC and MD favoured dominant class of the overlapping spectral class pairs causing the less dominant class of the class pair to suffer severe reduction in class accuracies. This was observed for EGF-DC and KH-BU class pairs. This, called as overfitting, is a characteristic of MLC [60]. c. LVQ classifiers extracted spectrally overlapping classes, in this case EGF-DC and KH-BU class pairs, with considerably better class accuracies hence, avoiding overfitting of the dominant classes. d. LVQ classifiers were highly successful in extracting classes with less number of training pixels. Both MLC and MD produced very low classification accuracies for these classes.

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6 Conclusions The significance of classification techniques in extraction of information from remote sensing (RS) cannot be undermined. The sheer amount of information in RS imagery enables RS data to be multipurpose resources. With improved classification techniques proposed in the field of classification, an analyst is required to have knowledge on the suitable classification technique based on the application. This requires characterization of image classifiers applicable to RS classification. In this paper, Kohonen’s self-organizing map and linear vector quantization algorithms are characterized by conducting a case study using Landsat 8 RS imagery. Kohonen’s algorithms show great efficiency in not only extracting LULC information from the RS imagery but also show some advantages in doing so. Specifically, from the results obtained during the study, the capability of LVQ algorithms in separating spectrally overlapping classes is noteworthy. Hence, they are advised for use with heterogeneous multispectral data sets with spectral overlapping classes. Also, the ability of LVQs in extracting less dominant classes of the spectrally overlapping class pairs indicates their superiority over conventional maximum likelihood and minimum distance-tomeans classifiers. However, the inability of unsupervised SOM in identifying all of the LULC classes is a backset. It is believed that, SOM can identify all LULC classes if the number of clusters is set to a higher value. But this would unavoidably increase the number of post-processing steps causing an increase in recoding complexity. Considering the advantages provided by Kohonen’s classifiers, it is strongly recommended to use higher clusters to achieve better classification accuracy for SOM.

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Solar Based Inverter Design: A Brief Review A. Vishwitha and Anil Kumar Bhat

Abstract Agriculture is one of the highly contributing sectors of Indian economy. Successful agriculture mainly depends on availability of water, fertilizer and seeds. Ever-increasing energy demand and the depletion of fossil fuels have lead to research on the use of renewable energy in agriculture. An inverter converts DC voltage into AC voltage. Solar-powered inverters are capable of reducing the dependency on electricity supply and are capable of working in hybrid mode. This paper reviews some of the work carried out related to different types of inverter design. Out of the various inverter architecture like Square wave, Quasi sine wave and Sine wave, the Sine wave inverter provides the best efficiency and low harmonic noise. MPPT control is required to have a better power efficiency in PV panel, and Perturb and Observe method is best suited in terms of cost and simplicity. Compared to MOSFET, IGBT offers easier drive control and better efficiency. FPGA/Microcontroller-based design provides reprogrammability and ensures reliable design. Keywords PWM · Boost converters · MPPT technique · Perturb and observe method · Incremental conductance method · HERIC · IGBTs · LC filter

1 Introduction Agriculture is one of the highly contributing sectors of Indian economy. It is the primary source of livelihood for a majority of India’s population. Agriculture is the profession which is very close to the nature. Successful agriculture depends on farmers having adequate access to water, fertilizer and seeds. Inadequate water supply leads to crop crash. Irrigation issues are of two types. One is due to unavailability of water, and the other is due to unavailability of means to supply water to the field. So, good modern techniques in irrigation can help the farmers to increase their produce A. Vishwitha (B) · A. K. Bhat Department of ECE, NMAM Institute of Technology, Nitte, India e-mail: [email protected] A. K. Bhat e-mail: [email protected] © Springer Nature Singapore Pte Ltd. 2020 S. Kalya et al. (eds.), Advances in Communication, Signal Processing, VLSI, and Embedded Systems, Lecture Notes in Electrical Engineering 614, https://doi.org/10.1007/978-981-15-0626-0_36

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and also income. Motor pumps are used for irrigation. Electric motors are precisely selected for size, application, performance and maintenance to ensure efficiency. AC and DC motors are generally adopted for irrigation purpose. AC motors are more common and best suited for the applications where the power performance is required for extended periods. AC motor uses both inverter and converter. An inverter is basically a converter that converts DC to AC power. As the demand for better inverters has surfaced, there has been a lot of progress in the inverter design and technology. Currently, inverters find multiple uses and applications in ensuring DC to AC conversion. The renewable resources have a massive potential for the agriculture industry. Hence for the sustainable agriculture, there is a need for encouraging the use of renewable energy systems. As compared with a diesel generator set, the underground submersible solar photovoltaic (PV) water pump is an environmental friendly and economically feasible option. Their costs have gone down, and their efficiencies have gone up. To utilize the naturally obtainable solar energy, solar inverters are introduced. In addition, solar inverters are eco-friendly since the solar panels produce power without waste or emission. Solar-based irrigation tends to use DC motors. Although it is an effective device, the cost becomes prohibitive factor as the farmer has to install a complete new setup. In order to incur less cost and utilization of existing pumps, we can use solar-based inverter to drive power. This paper presents a review on different approaches for the solar inverter designs.

2 Literature Review A lot of literature is available for solar power harvesting and inverter design. Here, an attempt has been made to identify the different design aspects, comparison between different architecture and to draw a conclusion on a strategy that is best suited for designing a solar-based inverter which is cost effective and efficient. Different types of power inverters are discussed in [1]. The types include current source and voltage source inverters, stand-alone grid-tied inverters, square, modified sine and sine wave inverters. Open loop strategy is used for the MATLAB simulation of the different types of Pulse Width Modulation (PWM) inverter. Brief explanation of battery, charge controller and the PV array is presented. Maximum Power Point Tracking (MPPT) algorithm is used to track the maximum power from the solar array. A comparison of different PWM techniques on the basis of cost, size, type of load and application is presented. Among the inverter types, grid-tied microinverter has been considered as the efficient one. The MPPT ensures maximum power from each individual PV panel. A design of single-phase grid-tied PV inverter is presented in [2]. For the implementation of MPPT technique, a boost converter is used, which provides the maximum power from the PV array. By using the Sinusoidal Pulse Width Modulation (SPWM) technique with Proportional Integral (PI) controller, the current injected into the grid is controlled. MATLAB Simulink is used for simulation, and the results

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for diverse cases are presented. In the paper, the grid-tied system is proved to be the best under different test conditions. Design of a single-phase PV inverter without galvanic isolation is presented in [3]. The output from the PV array is fed to the DC to DC boost converter. By using MPPT control technique, the gate pulse of the IGBT of boost converter is controlled. In order to efficiently convert the DC into AC, the boosted output is given to the Highly Efficient and Reliable Inverter Concept (HERIC) inverter. The large number of switches in the HERIC inverter in turn leads to higher complexity. To reduce the leakage current, the idea of HERIC configuration is presented in the paper. The analysis and verification of the simulation are done using MATLAB. A single-phase inverter with improved control strategy is presented in [4]. The Multiple Pulse Width Modulation (MPWM) is used as a control unit, which provides the output waveform with reduced harmonic content. Microcontroller 8051 is used to provide the triggering pulse, and this reduces the circuit complexity. For the harmonic analysis, the simulation of power circuit is done in MATLAB. Different load conditions are included and for the high-current inductive load, snubber parameters are calculated. A single-phase photovoltaic pure sine wave inverter with less harmonic distortion is presented in [5]. The energy from the PV panel is converted into regulated DC and fed to the inverter. The PIC16F876 microcontroller provides SPWM for the MOSFET driver. The output of the inverter is detected by the sensor and fed to the microcontroller. The compensation voltage is provided by the microcontroller for any lag in the pre-set value. The result is highly accurate since it uses closed loop. The output waveform is the distorted sine wave. Therefore, LC filter is introduced to eliminate the harmonic interference. The design includes a transformer at the output to ensure minimum eddy current loss. The objective of an efficient inverter with less harmonic distortion and low cost is achieved here. Design and real-time implementation of single-phase sine wave inverter is presented in [6]. SPWMs are generated by using PIC24F microcontroller. The SPWM simulation is carried out in MPLAB and implementation in Proteus. The isolation circuit uses TLP250 gate drivers for MOSFETs. For every test, the LCD displays the voltage, current and the delivered power to the load. Mainly, the PIC microcontroller used in the circuit avoids the drawbacks of the analog circuits. The design makes the circuit efficient for resistive load. A single-phase inverter design with new control method called Artificial Fish Swarm Algorithm (AFSA) is discussed in [7]. The Perturb and Observe algorithm is generally used in MPPT method for control because it is easy and simple to implement. But the control is not precise. Therefore, to provide a better control AFSA is used. AFSA has the advantage of providing strong optimization and speedy dynamic response, and thus increasing the PV efficiency. In the paper, AFSA control method is compared with the Perturbation and observation method by the simulation. A design of single-phase inverter with numerical control method based on ATmega32 is presented in [8]. The microcontroller-based control technique generally reduces the harmonics. For the generation of PWM signals, ATmega32 microcontroller is used. The main aim is to provide the alternative for conventional method

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with fewer harmonics and also to provide the dead-time control. The dead-time period must be proper in order to avoid the damage to the switches. To obtain the desired analog value, LC filter circuit is included. The paper [9] gives the design of three-phase sine inverter with 12 V DC source. DC to DC converter is used to convert the source voltage into the desired high voltage level, i.e., 565.6 V. The circuit is designed to generate appropriate pulses to switch the Insulated Gate Bipolar Transistors (IGBTs). The PWM voltage is then fed to threephase LC circuit to generate the desired sinusoidal waveform. The circuit simulation is done using PSIM software. The design and implementation of firing circuit for a three-phase PWM inverter is given in [10]. PWM signals are used to reduce the harmonics in the output. The phase shift circuit for single phase and three phases is discussed in the paper. Also, the paper summarizes the challenges of the design and modifications needed to meet the requirements, and the demonstration circuit for the PWM generation that can be used in the application like inverter. A three-phase voltage source inverter design using 500 V DC as the input is presented in [11]. SPWM technique provides the easier implementation of the design. The harmonics that is caused from the PWM is eliminated by Selective Harmonic Elimination (SHE) technique. SHE is based on reverse harmonic injection, and it mainly eliminates the lower order harmonics from an output. The paper presents the calculation of Total Harmonic Distortion (THD) for different order harmonics and then the opposite harmonics are injected. The disordered resultant sine wave is compared with triangular wave, and the gate pulses are produced. The simulation is carried out by using MATLAB. Design and implementation of driver circuit for three-phase inverter by using microcontroller ATmega16 is presented in [12]. The microcontroller reduces the circuit complexity. The design includes regulated power supply, microcontroller, isolation circuit and voltage source inverter. In the design, H-bridge is fed with 12 V DC supply. Depending on the load, MOSFET drives the high voltage and current. Optocoupler is used as an isolation device between the microcontroller and H-bridge. A fuse is connected to protect the component from over current. In the proposed design, output frequency of the inverter can be changed without changing the hardware. The design can be easily adopted for the applications like elevators and induction motors. A design of three-phase inverter with MPPT and V /f control is discussed in [13]. The design uses solar energy as an alternative to electricity. Perturb and Observe and Incremental conductance methods of MPPT are used to ensure the maximum power from the PV array. The pumping system is fed with the maximum power from PV array. V /f control is provided instead of sensor control. In V /f control system, the Space Vector PWM (SVPWM) signals are fed to the pump. The PWM signals are generated by using dsPIC30F2010 microcontroller. The constant torque is generated by maintaining a constant V /f ratio. In the prototype, ten solar panels are arranged in series to provide MPPT to PV pump. Three-phase micro inverter design with phase skipping control technique is presented in [14]. Generally, because of the variable weather conditions, the output of

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the PV panel varies. This affects the micro inverter operation. The phase skipping control is used to improve the light load efficiency. The control method is applied at the DC-AC stage of the Half-Bridge Inverter. Based on the available power from the PV panel, the selective power is injected and is monitored through the microcontroller. The main objective of the design is to achieve the increase in the efficiency of the inverter at light loads. The design of Field Programmable Gate Array (FPGA)-based PV inverter with SPWM control mechanism is discussed in [15]. MPPT controller is used to get the maximum power from the PV array. The control algorithm is implemented in FPGA, which provides speedy computation and reprogramming ability. FPGA plays a key role in reducing the hardware requirements and hence cost and is also a better alternative to the microcontroller system. In the paper, SPWM technique is used, which is designed using VHDL and implemented on Spartan 3A DSP FPGA. The power analysis is carried out for different frequencies to ensure the maximum efficiency.

3 Summary and Observations From the reviewed literature, we can classify the inverters into three main types based on the output namely Square, Modified sine and Sine wave inverters. Square wave inverters produce a square wave output and can be designed to operate with feedback and without feedback. As the output is square wave, this type of inverter is noisy and has a lot of harmonic distortion. This inverter topology is small in size and cost effective. The feedback topology allows controlling of voltage and frequency and hence can give better THD performance. If used with pumps or motors, this can cause heating effect. Modified sine wave inverters’ output is a multilevel signal with abrupt rise and fall in voltage at specific phase angle. This offers better noise performance than square wave inverters but is more costly. Motor efficiency reduces when running with this inverter. Pure sine wave inverters produce a sinusoidal waveform with smooth rise and fall in the voltage and phase angle. It is suitable for nearly all type of loads. AC motors can run efficiently with pure sine wave inverter. This design is bulky as it requires LC filters and is also costly. To obtain the maximum power from the PV array, MPPT technique is used. A brief summary of different MPPT methods obtained through the literature review is provided here. In constant voltage method, initially reference voltage (V ref ) is set, and the PV panel voltage is determined. The panel operates at the Maximum Power Point (MPP) when the panel voltage is equal to V ref . In case, panel voltage is greater or lesser than V ref , then the error signal is used to change the duty cycle. Implementation of this method is simple but not accurate. In constant current method, initially the short circuit current (I sc ) is measured and is multiplied with current factor (M c ) to obtain MPP current (I mp ). At fixed I mp value, the power is measured for different values of voltages. The difference between the computed power and the peak power

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is compared with the tolerance value. If it is larger, then depending on the obtained power, the value of voltage is either decremented or incremented. Until the difference is equal to the tolerance value, the process is repeated. This is one of the fastest methods, but it is difficult to choose the optimum value for current factor. In Perturb and Observe method, initially the voltage and current values are set and then the power from the array is calculated. Then, the power corresponding to the perturbed voltage value is measured and is compared with the previous value of the power. If the resultant power is greater than the previous value, then the system is perturbed in the same direction by changing the duty cycle. Otherwise, the system is perturbed in the opposite direction. This method is simple and accurate. Incremental conductance method of MPPT uses source incremental conductance to track MPP. Initially, the operating current and voltage are measured from the PV array. By comparing the most recent voltage and current values with the previous values, the incremental changes in the voltage and current are measured. Then, the conductance and the differential conductance values are compared. If both the values are equal, then the system operates at MPP, and there is no need to change the operating voltage. Otherwise, increase or decrease the duty cycle. If the incremental voltage is zero, then information about the possible changes are found from the measurement of current. If differential current is zero, then adjustment of the system voltage is bypassed. Otherwise, duty cycle is increased or decreased by step size. Then, the process repeats until MPP is obtained. This method is accurate with high speed of operation but is complex.

4 Conclusion Many different approaches of the inverter design are reviewed in the paper. From the literature reviewed, it can be concluded that the pure sine wave inverters are best suited for agricultural use. IGBTs can be chosen as the preferred switching devices as they are easy to drive and are better suited for high-frequency applications. The inclusion of isolation circuit provides high-current gate drive for switches by receiving low power input from the microcontroller. For ensuring maximum power efficiency from solar PV module, implementation of MPPT technique is necessary. One of the simplest methods of MPPT is Perturb and Observe, and it is also cost effective and gives a good control. For the generation of PWM signal, FPGA/microcontroller is better suited than discrete components, and they provide reprogrammability and better control. For the three-phase inverter design, SHE technique with LC filter provides less THD.

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References 1. Dileep DK, Bharath KR (2018) A brief study of solar home inverters. In: 2018 international conference on control, power, communication and computing technologies (ICCPCCT), Kannur, pp 334–339 2. Biju K, Ramchand R (2015) Control of a novel single phase grid connected solar PV/battery hybrid energy system. In: 2015 10th Asian control conference (ASCC), Kota Kinabalu, pp 1–4. https://doi.org/10.1109/ASCC.2015.7244436 3. Somani P, Vaghela DJ (2016) Design of HERIC configuration based grid connected single phase transformer less photovoltaic inverter. In: 2016 international conference on electrical, electronics, and optimization techniques (ICEEOT), Chennai, pp 892–896. https://doi.org/10. 1109/ICEEOT.2016.7754815 4. Dwivedy N, Rao SS, Kumar T, Gupta N (2017) Design and hardware implementation of 8051 micro-controller based single-phase inverter. In: 2017 innovations in power and advanced computing technologies (i-PACT), Vellore, pp 1–7. https://doi.org/10.1109/IPACT.2017.8244903 5. Chowdhury ASK, Shehab MS, Awal MA, Razzak MA (2013) Design and implementation of a highly efficient pure sine-wave inverter for photovoltaic applications. In: 2013 international conference on informatics, electronics and vision (ICIEV), Dhaka, pp 1–6. https://doi.org/10. 1109/ICIEV.2013.6572634 6. Hannan S, Aslam S, Ghayur M (2018) Design and real-time implementation of SPWM based inverter. In: 2018 international conference on engineering and emerging technologies (ICEET), Lahore, pp 1–6. https://doi.org/10.1109/ICEET1.2018.8338637 7. Li S, Zhang B, Xu T, Yang J (2014) A new MPPT control method of photovoltaic grid-connected inverter system. In: The 26th Chinese control and decision conference (2014 CCDC), Changsha, pp 2753–2757. https://doi.org/10.1109/CCDC.2014.6852640 8. Ouariachi ME, Mrabti T, Kassmi K, Kassmi K (2017) Design and realization of a single-phase inverter with numerical control based on an Atmega32. In: 2017 14th international multiconference on systems, signals & devices (SSD), Marrakech, pp 239–244. https://doi.org/10. 1109/SSD.2017.8166982 9. Ghosh G, Sinha V, Islam N (2016) 3-Phase, 400 V, 1 KW inverter design with sinusoidal waveform from A 12 V DC supply. Int J Adv Res Electron Commun Eng 5:2278–2909 10. Ogunyemi J (2013) Electronic simulation of phase shift circuit for three-phase pulse width modulated (PWM) inverter. Int J Eng Res Technol (IJERT) 2(11) 11. Rajpriya G, Ravi S, Zaidi AMA (2013) Design and development of MATLAB Simulink based Selective Harmonic Elimination technique for three phase voltage source inverter. In: 2013 international conference on advanced computing and communication systems, Coimbatore, pp 1–5. https://doi.org/10.1109/ICACCS.2013.6938734 12. Chakraborty TK, Rahman S, Rakib SH (2017) Simulation and implementation of microcontroller based gate drive circuit for three-phase MOSFET inverter. In: 2017 international conference on energy, communication, data analytics and soft computing (ICECDS), Chennai, pp 13–16. https://doi.org/10.1109/ICECDS.2017.8389717 13. Wareesri W, Po-Ngam S (2016) A three-phase PV-pump inverter with maximum power point tracking (MPPT) controller. In: 2016 13th international conference on electrical engineering/electronics, computer, telecommunications and information technology (ECTI-CON), Chiang Mai, pp 1–4. https://doi.org/10.1109/ECTICon.2016.7561272 14. Somani U, Jourdan C, Amirahmadi A, Grishina A, Hu H, Batarseh I (2014) Phase skipping control to improve light load efficiency of three phase micro-inverters. In: 2014 IEEE applied power electronics conference and exposition—APEC 2014, Fort Worth, TX, pp 2944–2949. https://doi.org/10.1109/APEC.2014.6803723 15. Sunita, Budhiraja S, Singh J, Bhat D (2016) FPGA based photovoltaic (PV) inverter with SPWM algorithm for photovoltaic system. In: 2016 5th international conference on wireless networks and embedded systems (WECON), Rajpura, pp 1–5. https://doi.org/10.1109/WECON.2016. 7993458

Two-Way Image Based CAPTCHA M. Poornananda Bhat and Rashmi Naveen Raj

Abstract CAPTCHA is a technology used to protect web applications from one of the malicious threats called BOT. CAPTCHA’s primary goal is to avail web services only to legitimate users and thereby foreseeing effective usage of web services. In this paper, a variant of image-based CAPTCHA is designed for visually challenged people. The main challenge is to identify human users from software robots. A novel two-way approach for image selection is designed to enhance the existing imagebased CAPTCHAs. Randomly generated homography transformation function is used to find a match between the two images. Image-based CAPTCHAs have overwhelmed the text-based CAPTCHAs, and the proposed approach promises a better test for legitimate users to accomplish higher web security while retaining ease of use. Keywords Web services · CAPTCHA · Image-based display · Internet security · Image matching

1 Introduction Security does not only confine to system, data and network but also extends its operation to online services. Due to rapid advancements in the web services, online facilities are widely used across the globe to ease shopping and physical transactions like banking, paying bills and purchasing travel or movie tickets and many more. Online services have a tremendous impact on individuals. E-commerce services relating to banking, trading and shopping are at fingertips if connected to the Internet. Hence, the Internet services are beneficial as well as prone to attacks. Attacks do not only limit to introduction of virus, worms to system but also aim at deliberately M. Poornananda Bhat (B) · R. Naveen Raj Information and Communication Technology, Manipal Institute of Technology, Manipal Academy of Higher Education, Manipal, India e-mail: [email protected] R. Naveen Raj e-mail: [email protected] © Springer Nature Singapore Pte Ltd. 2020 S. Kalya et al. (eds.), Advances in Communication, Signal Processing, VLSI, and Embedded Systems, Lecture Notes in Electrical Engineering 614, https://doi.org/10.1007/978-981-15-0626-0_37

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misusing the available web services by posting negative comments in the online shopping, share market portals and public groups. Therefore, detection and control measures are to be adopted to ensure effective utilization of online services. Security is of major concern in every aspect of information technology. Completely Automated Public Turing Test to Tell Computers and Humans Apart abbreviated as CAPTCHA is built to prevent non-human actors utilizing web services. Thus, CAPTCHA serves as a tool to identify human operators using online web services and acts as a measure of security. Online web services can be benefited by anyone with the knowledge of Internet fundamentals. The consumer community also extends physically challenged group. The concept is to solve the test in order to gain entry to the online transaction portals with minimum effort and time. Generally, CAPTCHA methods are designed to incorporate invariant recognition, segmentation and parsing abilities to successfully identify human users. Most online web services provide CAPTCHA as a primary activity to avail utility from respective applications to differentiate human user from software programmed robot referred to as BOT. BOTs are non-human actors, created by hackers to prevent effective utilization of web resources. Therefore, CAPTCHA acts as an initial Turing test, which a human user must qualify before being granted of web service. CAPTCHA is of three categories, text-based, image-based and audio-based. Categories of CAPTCHA are: 1. Text-based: The original form of CAPTCHA is text-based, in which a distorted text is displayed, and these texts are a combination of alphabets and numbers. The alpha-numeric characters’ placement plays a key role in devising text-based CAPTCHA. Text can be displayed over varied backgrounds with noise inclusion. A sample text-based CAPTCHA is shown in Fig. 1. Segmentation can be

Fig. 1 Text-based CAPTCHA

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deployed to increase complexity in the ordering of characters. User must identify the displayed text. 2. Image-based: An image-based CAPTCHA is the display of colored or black and white objects. The primary objective is either to identify an image from a set of images or an object from an image. A view of image-based CAPTCHA is shown in Fig. 2. Segmentation in image context includes angle of sight, angle of inclination and size of the object in the image and the intensity of colored images regarding pixels. 3. Audio-based: Audio-based CAPTCHA refers to the pre-recorded voice, played to identify the word or characters in the audio stream. Audio is the least preferred option while designing CAPTCHA system as it is helpful usually for the visually challenged people with eyesight issues. A view of audio-based CAPTCHA is shown in Fig. 3. Audio can be streamed with noise to complicate the hearing from easily understandable recording. Practically, any set of operations can be performed on categorized sets to deduce complexity in identification. Consequently, image displays can also be laid to have a perfect match in terms of pictorial identification. Strictly, image-based CAPTCHA Fig. 2 Image-based CAPTCHA

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Fig. 3 View of audio-based CAPTCHA

stands out to be better than the other two since humans are very good at pattern matching than BOTs and hence to some extent proves to be optimal. In this paper, an image-based CAPTCHA system is designed to identify matching objects from two sets of images. Compared to technique of selecting multiple images from a single set of images, the effort by aged people is reduced far more in the proposed method. To understand the ineffective resource utilization by BOTs, consider an instance where thousand resources are granted for an application. Resource allotment will happen on one to one requirement basis in case of legitimate human user accessing the available resources. But if the same is to be accessed by BOTs, then BOTs consume entire thousand resources irrespective of its requirement at one burst time interval. Thus, BOTs misusing the resources intentionally causes unnecessary depletion of available resources which otherwise could be benefited for effective usage and long run. One should also ensure that CAPTCHA should be solvable by visually challenged group at the cost of preventing BOTs. There is a requirement of a user-friendly CAPTCHA to be devised incorporating usability feature which is language-independent scheme and hence applicable for every age group, and thus, complexity levels can also be enhanced by deploying human characteristic observations. As a measure, a stronger version of image-based CAPTCHA is proposed by introducing two-way image-based approach. Two-way image-based CAPTCHA approach deals with providing two sets of images as a test to humans wherein a user must select one object of similar type from both the sets. User can gain access to web application only after identifying and selecting the correct match of object from two sets of images. The programmed robots cannot easily identify an object from two sets as humans do because robots detect objects by pixel calculation mechanism. Hence, robots will calculate two unique pixel sets for one image in the display. Thus, robots fail to identify the right selection that is accurate pixels from the calculated set because they lack thinking, deciding and judging capabilities and therefore results in denial of access to the web services. In this way, robots cannot gain access to web application, and thus, services are not misused and wasted and can be utilized effectively on requirement basis.

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The paper organization is as follows: Existing CAPTCHA techniques are discussed in Sect. 2. Section 3 describes the work proposed. Section 4 describes implementation and results. Section 5 describes conclusion and future scope.

2 Literature Survey Origin of CAPTCHA and review of the existing work is discussed in the following section.

2.1 Origin of CAPTCHA AltaVista was the first website to utilize a straightforward CAPTCHA that produced pictures of arbitrary content. It utilized the CAPTCHA to keep clients from misusing its free URL accommodation utility. In 2000, Udi Mamber of Yahoo was scanning for approaches to keep bots from joining the online talk rooms to post pointless and counterfeit promotions. Scientists at Carnegie Mellon University took up the issue and continued to evaluate alluring qualities of CAPTCHAs. The exploration created a few sorts, including the Gimpy kind. Gimpy sort is the base dimension form of CAPTCHA. At present, CAPTCHAs have picked up a high acknowledgment and is being used in every web access, for example: free email servers, online ticket reservations, online sale locales, file sharing sites and so on. Blocking of computerized URL submission to the search engines influenced the need for improvement in security by adapting to the changing user interfaces and technology. This altogether gave rise to the concept of CAPTCHA [1]. It is a concern of programmers to overcome and defend the spam agents intruding into the highly secured systems. CAPTCHAs are also developed on usability features depending on the education, solving ability, object recognition and range of ages using the service. To train computers to recognize the displays is very hard as it involves programs to detect pixel patterns regarding images and optical character recognition is performed by segmenting the characters and identifying the underlying character by plotting it on the graph [2]. So, all these tasks are to be manually fed to computers if they are to pass the CAPTCHA test, which is extremely cumbersome. Hajjdiab et al. [3] have introduced a visual CAPTCHA system in which computer generates random images and user has to match the feature point in both the images. The proposed system does not require any image database. Clark et al. [4] have proposed a visual CAPTCHA method in which arbitrary pictures are created by the system, and the user has to coordinate a component feature between two images. The relation between the two pictures depends on an arbitrarily created homography transformation function. Saha et al. have [5] used questionnaire-based CAPTCHA system in which diversified questions are displayed and user has to answer these questions to gain access

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to Internet resources. The proposal was tested by users of both genders as well as with different backgrounds and has proved to be better. The CAPTCHA algorithm requires the user to have some level of logical reasoning knowledge. Datta et al. [6] have proposed image-based CAPTCHA in which different controlled distortions are applied to images. Author has measured human recognizability based on an extensive user study, machine recognizability is measured on contentbased image retrieval (CBIR) and coordinating calculations. Gossweiler et al. [7] have another CAPTCHA method that depends on identifying an image’s upright orientation. In this method, an image is displayed with random orientation, and user has to rotate the image to get into its upright position. This mechanism requires an observation of the regularly perplexing substance of an image and such assignments are mostly performed well by humans and generally machines fail. The principle points of interest of this CAPTCHA method over the customary content acknowledgment systems are that it is language-free and does not require content passage. Ali et al. [8] have designed a puzzle CAPTCHA framework by utilizing an imagebased CAPTCHA. CAPTCHA is implemented using HTML, JavaScript, J Query and Cascading Style Sheets (CSS). The user interface will display main image from a database of 200 jpg format images. The main image is divided into many parts and each part is displayed in another box. User has to drag the various parts and arrange them so as to get a main image. Banday et al. [9] have proposed a multilingual based IN-CAPTCHA system applicable especially for regional online web services offered in various languages. All the websites which would like to avail IN-CAPTCHA service should register with IN-CAPTCHA server. The communication between the website and server is secured by generating public and private keys for each website during registration. Whenever the user requests for the resource, user will be authenticated by verifying the private key. Tang et al. [10] have proved breaking of text-based CAPTCHA using deep learning techniques and have proposed novel image-based CAPTCHA system. Proposed CAPTCHA is based on understanding of semantic information deep learning techniques and pixel-level segmentation. Attack system designed by authors includes image preprocessing such as converting color to binary image, noise removal and color filling segmentation. Using deep learning-based attack system, authors could attack top 50 websites which proves the inefficiency of text-based CAPTCHA. Image-based CAPTCHA system applies various styles to a main image and user has to click on various style-transferred regions which will be informed through short descriptions. Osadchy et al. [11] have proposed deep learning-based CAPTCHA system. Authors have proved that CAPTCHA based on introducing simple noise to the image can be easily attacked using deep learning techniques. Authors have proposed to introduce immutable adversarial noise which can withstand various attacks. Powell et al. [12] have proposed image-based CAPTCHA system in which a composite complex image is displayed. Authors will be given instructions to identify multibiometrics like fingerprint, eyes, face and so on. The designed system was tested

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on 1900 users and was found to be more accurate as well as resistant to various attacks on CAPTCHA. Kulkarni et al. [13] have designed mobile device-specific pedometric CAPTCHA system. In this CAPTCHA system, the user has to walk minimum five steps to gain access to registration page. In registration page, once again user login ID and password will be verified. So, CAPTCHA is applicable only for mobile devices when the person is also under movement.

3 Proposed System A novel two-way image-based CAPTCHA is proposed to prevent BOTs from gaining access to online web services. The workflow of our proposed system is shown in Fig. 4. There are two steps to gain access to web resources: authentication phase and CAPTCHA phase. In the authentication phase, the user credentials are verified against the data provided by the user at the time of registration to the respective online web portals to account for the valid and genuine human user. Hence, login page of respective online web portals is the initial step to enter the online service application. Successful login directs to our designed CAPTCHA page. This CAPTCHA phase requires human interaction activity. Solving two-way image-based CAPTCHA is the activity to be performed by every user to be detected as human user and not a bot. CAPTCHA system must satisfy the basic properties [11] like easy for humans to solve, hard for software programmed robots to solve and must be supported by a large and dynamic set of test cases. The architecture of the proposed CAPTCHA system is shown in Fig. 5. The working of the algorithm is explained with following steps: Step 1. User logs in with name and password and hits the login button. Step 2. User gets directed to the CAPTCHA page and is prompted to identify the correct images with matching objects from the two sets of images. Matching images are displayed at random locations in both the grids. User must select two images from each of the sets and click on submit button. Step 3. If the user has clicked the correct matching images, then he can successfully utilize the respective online web service. Here, food website is used for testing purpose.

Fig. 4 Workflow

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Fig. 5 Architecture of two-way image-based CAPTCHA

The processing steps are also explained in the form of flowchart in Fig. 6. The following features make our proposed system more robust than the existing system. • Care is taken to refresh displayed images after every attempt and is achieved by implementing random image display from image database. • Also, the database used does not contain any information about the placing or order of image display, thus avoiding the attackers to access CAPTCHA algorithm even if they could break the database. Since CAPTCHA approval is implemented at user end, load on the server is reduced. • After every user attempt, the CAPTCHA page displays images of random objects in random pattern. Thus, the periodicity of an image of given objects is not fixed and is completely unpredictable. • Another factor governing the CAPTCHA complexity is the display of unique images of same objects with optimal similarity, and hence making this CAPTCHA stand ubiquitous from the rest. The match to be performed contains the same entities from image sets with varied color, orientation and backgrounds.

4 Implementation and Result Analysis An image database is created which consists of high definition images relating to easily recognizable entities that we see around and all are aware of. Two-way imagebased CAPTCHA’s framework is partitioned into two equal halves. Both the partitions comprise a grid with nine cells. High definition images of objects like animals, electronic gadgets, environment and many such which are easily identifiable by humans are placed in each cell of both the grids. Image positioning in the grids is based on a randomly generated homography transformation function, which refreshes the page after every single user attempt to solve the CAPTCHA. HTML language constructs are used to implement the CAPTCHA. The random image placement function is implemented using Hypertext Preprocessor (PHP) to dynamically place

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Fig. 6 Process flowchart

image objects to the allocated cells of the grids. PHP scripting is used to perform user’s session activities and also for implementing key functional modules of the system: Randomizer and Image Matching algorithm. Internally every image is identified by a unique number and is matched by a number comparison operator. A login page is designed as shown in Fig. 7, and only after successful login, user is directed to CAPTCHA system. The image database is placed in the servers. The image placing pattern is thus arbitrary and is hence not easily predictable. The user succeeds in qualifying the test only if the selected object from both the images matches and thus the CAPTCHA verifies the user as human operator and hence a user can navigate to the next page of the application. The user must solve the test by matching images of similar objects from both the grids and matching is performed by clicking the checkbox provided. Internally, the matching of the image is carried out using the

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Fig. 7 Authentication phase—initial login page

comparison algorithm. At least one object in both the image sets will be found same to guarantee the working of the test. In the case of a mismatch, the login of the user is prohibited. The images are loaded from image database into the division tags in HTML and a checkbox provision is set for each of the image selection as shown in Fig. 8. If the user ticks the correct checkbox pertaining to similar objects, the image comparator validates the user as human actor and thus the CAPTCHA page opens the appropriate website and the success scenario is shown in Fig. 9. The image comparison gives either success or failure result which is displayed as a notification message. Once a selection is found to be successful, then the user is directed to next page, that is, respective web portal on clicking the login button. In case of a failure,

Fig. 8 Two-way CAPTCHA system

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Fig. 9 Successful login directing to the food website portal

the page reverts to the initial user authentication page as shown in Fig. 7 and the procedure continues. An experimental investigation is conducted to calculate the ease of use and measure the convenience of our proposed CAPTCHA framework. In the investigation, ten volunteers were included. The volunteers are students of age group 23–26, also from diverse majors and distinctive rank dimensions. Each one of them knew about the PCs and has been exposed to a practically identical CAPTCHA framework. Each user was asked to understand ten CAPTCHA issues. For each test, the time is taken by the user to pick one object in the subjective images and its contrasting match in the parallel arrangement set is recorded. The user can make up to three primers beforehand demonstrating another course of action of images. Because of the continuous examination, we recorded the average response time as 9.36 s for the ten volunteers. CAPTCHA section 508 compliance standard [14] necessitates giving a chance for the visitor to request a different CAPTCHA when the current one is difficult to solve. People with visual impairments usually have a problem with low contrast images, small-sized text. These challenges are overcome by carefully choosing and presenting the CAPTCHA images. The algorithm requires the user to identify only the patterns involved in the image and does not require to identify either the color or minute details of the images. Hence, the proposed algorithm is more suitable for users with visual impairments as well as for color-blind users.

5 Conclusion In this paper, we exhibited a novel image-based CAPTCHA, a way to deal with the fundamental shortcomings of the CAPTCHA presented in the existing systems.

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The primary favorable feature of our proposal is that it depends on image coordinating methodology. Coordinating of two images of a similar feature is common and is instinctive for people, however, is of high complexity for programming robots particularly under added noise and disfigurement. Each time two arrangements of similar images are displayed from the image database which is bulky and troublesome for the aggressor or programming bots to recognize the position of an image on each test. Sufficiently a great segment of the image repository is generated and, in this manner, defeating CAPTCHA turns out to be significantly tedious. In our methodology, the image positions are arbitrarily created, and image placement detection and analysis are hard and cannot be effectively anticipated by the software robots. Two-way image-based CAPTCHA fits fast execution for visually challenged group users and practically has a boundless supply of images and also, CAPTCHAs are successful at crushing spammers, Spoofers and web index crawlers who intend to damage web services. We conducted broad tests to prove the usability of proposed system, and development of two-way image-based CAPTCHA system has successfully met the objective. As a part of future work, we propose to apply image organizing strategies on every course of action of images to enhance the security features. Also, the work can be tested across users of different age group. Likewise, the work may be extended to devise calculations that utilize artificial intelligence to tune different parameters for twisting, disfigurement and jumbling of items utilized in the image CAPTCHA. Acknowledgements The authors would like to thank Manipal Institute of Technology, Manipal, for all the resources granted as per the requirements. Compliance with Ethical Standards The study involved only development, validation and feedback on the technical aspect of the software. Hence, clearance from only the Information and Communication department committee was obtained. Informed consent was obtained from all volunteers included in the study.

References 1. Vaithyasubramanian S (2016) Review on development of some strong visual CAPTCHAs and breaking of weak audio CAPTCHAs. In: 2016 International conference on information communication and embedded systems (ICICES), IEEE 2016, pp 1–4 2. Kolupaev A, Ogijenko J (2008) Captchas: humans versus bots. IEEE Secur Priv 6(1):68–70 3. Hajjdiab H (2017) Random image matching CAPTCHA system. ELCVIA Electron Lett Comput Vision Image Anal 16(3):0001–13 4. Pope C, Kaur K (2005) Is it human or computer? Defending E-commerce with CAPTCHAs. IT Prof 7(2):43–49 5. Saha SK, Nag AK, Dasgupta D (2015) Human-cognition-based CAPTCHAs. IT Prof 17(5):42– 48 6. Datta R, Li J, Wang JZ (2009) Exploiting the human–machine gap in image recognition for designing CAPTCHAs. IEEE Trans Inf Forensics Secur 4(3):504–518 7. Gossweiler R, Kamvar M, Baluja S (2009) What’s up CAPTCHA?: a CAPTCHA based on image orientation. In: Proceedings of the 18th international conference on World wide web, ACM 2009, pp 841–850

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8. Ali FABH, Bt Karim F (2014) Development of CAPTCHA system based on puzzle. In: 2014 International conference on computer, communications, and control technology (I4CT), IEEE 2014, pp 426–428 9. Banday MT, Sheikh SA (2014) Service framework for dynamic multilingual CAPTCHA challenges: IN-CAPTCHA. In: 2014 International conference on advances in electronics computers and communications, IEEE 2014, pp 1–6 10. Tang M, Gao H, Zhang Y, Liu Y, Zhang P, Wang P (2018) Research on deep learning techniques in breaking text-based captchas and designing image-based captcha. IEEE Trans Inf Forensics Secur 13(10):2522–2537 11. Osadchy M, Hernandez-Castro J, Gibson S, Dunkelman O, Pérez-Cabo D (2017) No bot expects the DeepCAPTCHA! Introducing immutable adversarial examples, with applications to CAPTCHA generation. IEEE Trans Inf Forensics Secur 12(11):2640–2653 12. Powell BM, Kumar A, Thapar J, Goswami G, Vatsa M, Singh R, Noore RA (2016) A multibiometrics-based CAPTCHA for improved Online security. In: 2016 IEEE 8th International conference on biometrics theory, applications and systems (BTAS), BTAS 2016 13. Kulkarni S, Fadewar HS (2017) Pedometric CAPTCHA for mobile Internet users. In: 2017 2nd IEEE International conference on recent trends in electronics, information & communication technology (RT (RTEICT), RTEICT 2017 14. Section 508 CAPTCHA: how to make CAPTCHA comply with access board section 508 standards [online]. Available https://captcha.com/accessibility/section508-captcha. html. Accessed: 22 Apr 2019

Performance Comparison of Semi-Z-Source Inverter and Full-Bridge Inverter M. Megha and V. Ansal

Abstract In this paper, the performance comparison of Semi-Z-Source Inverter and Full-Bridge Inverter is presented. The Semi-Z-Source DC-DC converter is utilized in its inverting mode. The number of switches used and the current conduction path of Full-Bridge Inverter is double that of Semi-Z-Source Inverter. Hence, Semi-ZSource Inverters are preferred in inverter applications. Since the voltage gain curve for Semi-Z-Source Inverter is nonlinear, Modified Sinusoidal Pulse Width Modulation technique is used to produce the required pulses for the switches. This paper also describes the modeling and analysis of Semi-Z-Source Inverter in continuous conduction mode. The dynamics introduced by the Z-network of Z-Source converter is considered for the ac small-signal model. The output of Semi-Z-Source Inverter and Full-Bridge Inverter is simulated in MATLAB/Simulink environment. The performance of these two inverter topologies is compared. Keywords Feed-Forward control · Full-Bridge inverter (FBI) · MATLAB · Modified sinusoidal pulse width modulation (MSPWM) · Semi-Z-Source inverter (SZSI)

1 Introduction Lately, because of the energy crisis, sustainable energy Distributed Power Generator (DG), for example, photovoltaic (PV) cells, thermo-electric generation (TEG) modules, wind turbines, and fuel cells are becoming more prominent in various industrial and household applications [1]. The output of sustainable energy DGs is always a DC voltage, so an inverter interface must be used for grid-connected applications [2, 3]. Recently, numerous inverter techniques have been proposed and studied. M. Megha (B) · V. Ansal Department of Electronics and Communication, N.M.A.M. Institute of Technology, Karkala, India e-mail: [email protected] V. Ansal e-mail: [email protected] © Springer Nature Singapore Pte Ltd. 2020 S. Kalya et al. (eds.), Advances in Communication, Signal Processing, VLSI, and Embedded Systems, Lecture Notes in Electrical Engineering 614, https://doi.org/10.1007/978-981-15-0626-0_38

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Because of the size, cost, and weight issues, transformers having high frequency are preferred for future applications [4]. There is a two-phase approach for the inverter techniques having high-frequency transformer. The first stage has an isolated regulator, and the second stage contains FBI [5]. The regulator present in the first stage is designed to have high efficiency, high voltage gain, and soft switching [6]. The FBI for the second stage can use high-frequency switches with Pulse Width Modulation (PWM) technique or line-frequency switches in order to reverse the voltage. In many cases, a FBI with line-frequency switches is utilized to minimize the cost and switching loss. In order to minimize the cost and to improve the working of the system, a solitarystage transformer-less SZSI topology was suggested [7–9]. By using the distinctive LC network, a shoot-through zero state is included to substitute the conventional zero state of the inverter, and this results in enhancement of the output voltage. Different types of PWM techniques to control the ZSI are proposed depending on different techniques of positioning the shoot-through zero state [10]. SZSIs are used in applications like the three-phase motor drive for Hybrid Electric Vehicles (HEVs) or three-phase PV or grid-connected wind power generation systems [11]. The doublygrounded feature is absent in majority of these techniques except [12]. But only one cycle control is explored for Z-Source in [12]. Section 2 analyzes the working principle of a single-phase FBI and forms statespace equations. Section 3 explains the functioning of the solitary-stage non-isolated SZSI, which is less expensive and has doubly-grounded feature. This circuit can obtain the equivalent output voltage as the conventional FBI with only two active switches. To yield sinusoidal voltage, the SZSI uses the nonlinear voltage gain curve to produce a modified voltage reference. Experimental simulation is performed using MATLAB/Simulink tool, and the outcomes are discussed in Sect. 6.

2 Full-Bridge Inverter The working principle and mathematical model for the single-phase FBI are explained in this section. Its functioning is based on bipolar voltage switching with Sinusoidal Pulse Width Modulation (SPWM) technique. All the components are expected to be ideal. Schematic of single-phase FBI is shown in Fig. 1. The switching devices have two states of operation with control variable u ∈ {0, 1}. If S1 and S4 are on, then u = 1. If S2 and S3 are on, then u = 0 [13]. State I: S1 and S4 are ON, then u = 1. Based on SPWM, the Full-Bridge circuit can produce a positive half sine wave. The equivalent circuit is shown in Fig. 2. The state-space equation with respect to the circuit topology can be written as follows:

Performance Comparison of Semi-Z-Source …

Fig. 1 Single-phase full-bridge inverter

Fig. 2 Equivalent circuit of state I

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Fig. 3 Equivalent circuit of state II

⎧ di (t) Vin − VC f (t) Lf ⎪ = ⎪ ⎨ dt Lf i L f (t) VC f (t) ⎪ dVC f (t) ⎪ ⎩ = − dt Cf RC f

(1)

State II: S2 and S3 are ON, then u = 0. Based on SPWM, the Full-Bridge circuit can produce a negative half sine wave. The equivalent circuit is shown in Fig. 3. The state-space equation with respect to the circuit topology can be written as follows: ⎧ −Vin − VC f (t) ⎪ ⎪ ⎨ di L f (t) = Lf ⎪ ⎪ dVC f (t) = i L f (t) − VC f (t) ⎩ dt Cf RC f

(2)

Equations (1) and (2) are combined having the control variable u ∈ {0, 1} to form Eq. (3): 

di L f (t) dt dVC f (t) dt



 =

0 1 Cf

−1 Lf −1 RC f



 Vin  i L f (t) + L f (2u − 1) VC f (t) 0

(3)

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3 Semi-Z-Source Inverter SZSI is a DC-to-DC converter. It delivers both positive and negative voltages and is represented in Fig. 4. Figure 5 shows the voltage gain curve of SZSI. D is taken as the duty cycle of switch S1 . This converter can be transformed into an inverter after applying a correct Pulse Width Modulation technique. The range of values for the duty cycle D is from 0 to 2/3. The number of switches is lessened to half in SZSI in comparison with FBI. MOSFET and IGBT are the two options for switching device in SZSI. The current flow is bidirectional in nature, and it has unidirectional voltage blocking characteristics. The voltage gain curve of SZSI is nonlinear in nature, and hence, a MSPWM technique is used to yield the sinusoidal voltage. Fig. 4 Semi-Z-source inverter

Fig. 5 Operating region of SZSI with respect to the duty cycle

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3.1 Working Principle of SZSI Figure 5 represents the voltage gain curve of SZSI. The X-axis is the duty cycle of S1 , and the Y-axis is the voltage gain of SZSI. When S1 conducts, S2 is OFF and vice versa. The red solid line shown in Fig. 5 depicts the range of duty cycle (0-2/3) for which SZSI yields the equivalent voltage range (+Vin to −Vin) as the FBI. AsD varies from (0 to 1/2), SZSI yields the positive output voltage, and AsD varies from (1/2 to 2/3), and the inverter yields the negative output voltage. When D is equal to 1/2, the SZSI produces zero voltage. The equivalent circuit for the two states of operation of SZSI in one switching period is shown in Fig. 6. The equivalent circuit for State I when the Switch S1 is conducting is shown in Fig. 6a. When S1 is on, the inductor current increases as the two inductors are charged by the input voltage source and the capacitor C1 . The equivalent circuit for State II when switch S2 is conducting is shown in Fig. 6b. When S2 is on, the inductor current decreases due to the energy given out by it. Figure 6 represents the reference direction of capacitor voltage and inductor current. Following are the steady-state equations derived based on the two states of operation of SZSI: 1 − 2D Vo = Vin 1− D VC1 =

D Vin 1− D

I L 2 = −Io IL1 = −

D Io . 1− D

(4) (5) (6) (7)

Equation (8) represents the output voltage of the inverter. Equation (9) defines the modulation index. Substituting Eqs. (8) and (9) in Eq. (4) is to obtain Eq. (10).

Fig. 6 Working modes of SZSI: a state I S1 is ON and b state II S2 is ON

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D  = 1 − D is the duty cycle of the switch S2 and is derived as in Eq. (11). The relationship of the output voltage and the input voltage in terms of duty cycle for a FBI is linear. Hence, the duty cycle can be changed in sinusoidal manner to acquire a sinusoidal output voltage. But the relationship between input voltage and output voltage of a SZSI is nonlinear. Thus, it is not possible to obtain the sinusoidal output voltage by varying the duty cycle in sinusoidal manner. Hence, an equivalent nonlinear modified duty cycle is utilized to produce the right sinusoidal output voltage [14]. Different duty cycle reference as shown in Eqs. (10) or (11) can be used. Vo = V sin ωt V Vdc

(9)

1 − M sin ωt 2 − M sin ωt

(10)

M= D=

(8)

1− D =

1 . 2 − M sin ωt

(11)

3.2 Modified Sinusoidal Pulse Width Modulation Technique The duty cycle D for switch S1 and the duty cycle 1 − D for switch S2 are obtained as in Eqs. (10) and (11), respectively. Figure 7 depicts the Modified Sinusoidal Pulse Fig. 7 Modified sinusoidal pulse width modulation technique for SZSI

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Width Modulation technique. Because of the nonlinear relationship between the voltage gain and the duty cycle, a nonlinear sinusoidal PWM technique known as Modified Pulse Width Modulation is used to yield sinusoidal wave. The switching pulse of switch S2 is generated by the reference voltage given by the Eq. (11). The switch S2 turns ON when the magnitude of the reference sinusoidal wave is larger than that of the carrier triangular wave and vice versa. The reference sine wave for switch S1 is given in Eq. (10). The operation of switches S1 and S2 is in complementary mode. The modulation index M has a range (0–1). The gate pulse of switch S2 is easier to calculate. Hence in real time, the formation of pulse of S2 is selected. When M is equal to 2/3, the pulse of S1 and S2 is shown in Fig. 7.

3.3 Modeling Technique Two main state variables considered for the small-signal modeling of the SZSI are capacitor voltage and inductor current. The equation can be given as follows: T

x(t) = i L 1 (t)i L 2 (t)vC1 (t)vC2 (t) .

(12)

It is assumed that the impedance network has lossless passive components for the small-signal modeling of Semi-Z-Source Converter (SZSC). The forward voltage drop and the ON resistance for S1 and S2 are ignored. An independent voltage source Vdc is the input, and R being the load is resistive. For State I mode of activity, the differential equations administrating the framework are composed as x(t) ˙ = A1 · x(t) + B1 · u as shown in Eq. (13). ⎤ ⎡ 0 0 0 i L 1 (t) 1 ⎢ ⎥ ⎢ d ⎢ i L 2 (t) ⎥ ⎢ 0 −R L2 L2 = ⎢ 1 dt ⎣ vC1 (t) ⎦ ⎣ 0 C1 0 vC2 (t) 0 C12 0 ⎡

⎤⎡ ⎤ ⎡ 1 ⎤ 0 i L 1 (t) L1 ⎢ 0 ⎥ 0⎥ i L 2 (t) ⎥ ⎥⎢ ⎢ ⎥ ⎢ ⎥[V ] + ⎥ 0 ⎦⎣ vC1 (t) ⎦ ⎣ 0 ⎦ dc vC2 (t) 0 0

(13)

For State II mode of activity, the differential equations administrating the framework are composed as x(t) ˙ = A2 · x(t) + B2 · u as shown in Eq. (14). ⎤ ⎡ 0 0 −1 0 ⎤⎡ ⎤ ⎡ ⎤ 0 i L 1 (t) i L 1 (t) L1 ⎢ ⎥ −R −1 ⎥ ⎢ ⎥ ⎥ ⎢ 0 0 0 d⎢ ⎥⎢ i L 2 (t) ⎥ ⎢ L 2 ⎥ L2 ⎢ i L 2 (t) ⎥ = ⎢ + [Vdc ] ⎢ ⎥ dt ⎣ vC1 (t) ⎦ ⎣ C11 0 0 0 ⎦⎣ vC1 (t) ⎦ ⎣ 0 ⎦ vC2 (t) vC2 (t) 0 0 C12 0 0 ⎡

(14)

The DC steady-state equations illustrating the SZSC by taking high switching frequency into consideration can be written as

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0 = (D A1 + (1 − D)A2 )X + (D B1 + (1 − D)B2 )U.

(15)

By solving Eq. (14), the steady Eqs. (4) to (7) are acquired. Perturbations are ˆ in order included to the input voltage represented as vˆ dc (t) and duty cycle as d(t) to determine the small-signal model. The equations for small-signal space can be generalized as .







ˆ X = (D A1 + (1 − D)A2 ) · X + (D B1 + (1 − D)B2 ) · U + [(A1 − A2 )X + (B1 − B2 )U ]d(t)

⎡

0 0 . ⎢ 0 −R ⎢ X = ⎢ −D LD2 ⎣ C1 C1 0 C12



⎡ D ⎤ ⎡ 1 ⎤ ⎤ ⎡ 0 0 0 L11 0 L1 L ⎢ 11 ⎢ D−1 ⎥ ⎢ 0 0 1 0⎥ 0⎥ ⎢ L2 ⎢ L2 ⎥ ⎥ ⎥ ⎢ L 2 ⎥ · +⎢ ⎥ · U + ⎢ −1 1 ⎥· X +⎢ 0 0⎦ ⎣ 0 ⎣ 0 ⎦ ⎣ C C 0 0⎦ 1 1 0 0 0 0 0 0 0 0

D−1 L1 D L2





(16)

⎤ ⎥ ⎥ ⎥ · U. ⎦ (17)

Applying Laplace transform for Eq. (17), Eqs. (18)–(21) are acquired. Substituting vˆ dc = 0 in Eqs. (18)–(21), the control-to-capacitor voltage transfer function G vd (s) is acquired. The equations become s L 1 · iˆL 1 (s) = (D − 1)ˆvC1 (s) + D vˆ dc (s) +

Vdc ˆ d(s) (1 − D)

s L 2 · iˆL 2 (s) = −R iˆL 2 (s) + D vˆ C1 (s) + (D − 1)ˆvdc (s) + sC1 · vˆ C1 (s) = (1 − D)iˆL 1 (s) + D iˆL 2 (s) +

Vdc ˆ d(s) (1 − D)

iˆL 1 ˆ d(s) (1 − D)

sC2 .ˆvC2 (s) = iˆL 2 (s).

(18) (19) (20) (21)

The output voltage of the SZSI is equal to the capacitor voltage vC2 . The smallsignal expression for capacitor voltage vˆ C2 can be written as the combination of input voltage and duty cycle perturbations in the linear form as: ˆ vˆ C2 (s) = G vdc (s).ˆvdc (s) + G vd (s) · d(s).

(22)

Input-to-capacitor voltage transfer function G vdc (s) and control-to-capacitor voltage transfer function G vd (s) present in Eq. (22) are expressed in Eqs. (23) and (24), individually [15]. Since input voltage is DC source, the output voltage is expressed as   1 (D − 1)L 1 C1 s 2 + D 2 (1 − D) − (1 − D)3   G vdc (s) = C2 s L 1 L 2 C1 s 3 + R L 1 C1 s 2 + (1 − D)2 L 2 − D 2 L 1 s + R(1 − D)2 (23)

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Fig. 8 Block diagram of feed-forward control method for SZSI

  1 D L 1 C1 s 2 + (1 − D))Vdc − 1−D L 1 IL1 s D + 1−D 1   G vdc (s) = C2 s L 1 L 2 C1 s 3 + R L 1 C1 s 2 + (1 − D)2 L 2 − D 2 L 1 s + R(1 − D)2 (24) ˆ vˆ C2 (s) = G vd (s) · d(s).

(25)

3.4 Feed-Forward control for SZSI Figure 8 demonstrates the control block diagram of the Semi-ZSI. Robustness and simplicity are the key points of interests of the feed-forward voltage control technique ˆ According to the in this inverter. The input voltage vmv is modified to get d(s). Eq. (26), the block G vd (s) gives the inverter voltage vinv [15]. G vd (s) =

vˆ C2 (s) . ˆ d(s)

(26)

4 Total Harmonic Distortion The quality analysis of the Pulse Width Modulated voltage is performed in time domain. It is done based on voltage ripple Normalized Mean Square (NMS). The voltages are normalized with respect to a DC bus. The successive averaging operations performed on a PWM period and on a fundamental AC help acquire voltage ripple NMS. Due to the asymptotic assumption, these two averaging operations become independent [16]. THD for single-phase FBI and SZSI is shown in Figs. 9 and 10, respectively.

Performance Comparison of Semi-Z-Source …

Fig. 9 THD for single-phase FBI

Fig. 10 THD for single-phase SZSI

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The voltage THD is calculated after obtaining the voltage ripple NMS value using the following equation:

THDn (m), % = n m NMSAC n

 2NMSAC n (m) m

· 100[%].

(27)

(non-negative) voltage level count of the converter (2 for a two-level inverter); modulation index, 0 < m